[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

evandro added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; HsiangKai wrote: > evandro wrote: > > HsiangKai

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

HsiangKai marked an inline comment as done. HsiangKai added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:9 +/// +/// This file describes the RISC-V instructions from the standard 'V', +/// Vector instruction set extension. asb wrote: >

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

HsiangKai marked an inline comment as done. HsiangKai added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>;

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

asb added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:9 +/// +/// This file describes the RISC-V instructions from the standard 'V', +/// Vector instruction set extension. Please add similar language as in RISCVInstrInfoB.td to indicate

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In D69987#2079524 , @rogfer01 wrote: > The patch as it stands now LGTM and I think it can be committed. Is there any > objection remaining? > > Any further

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

evandro added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; HsiangKai wrote: > evandro wrote: > > Methinks

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

fpallares added a comment. I'm not a reviewer but the patch LGTM, thanks for all the changes @HsiangKai. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D69987 ___

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

rogfer01 added a comment. The patch as it stands now LGTM and I think it can be committed. Is there any objection remaining? Any further comments @simoncook @asb? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

HsiangKai marked an inline comment as done. HsiangKai added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>;

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

evandro added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; Methinks that these constraints `WidenV`,

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

evandro added a comment. It looks pretty GTM. At this point, I'd be fine with accepting this patch as the major issues seem to have already been addressed. Should there be any other minor issue, it could be addressed later. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

HsiangKai added a comment. In D69987#2074265 , @MaskRay wrote: > Drive-by comment: the clang side change isn't tightly coupled with the LLVM > side changes. It should be a separate patch. Create https://reviews.llvm.org/D81188 for clang side change.

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

MaskRay added a comment. Drive-by comment: the clang side change isn't tightly coupled with the LLVM side changes. It should be a separate patch. Comment at: llvm/test/MC/RISCV/rvv/add.s:1 +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v < %s \ +# RUN:

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

HsiangKai added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D69987 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

fpallares added a comment. I've added a couple more inline comments. I've also noticed that we aren't emitting the aliases for unmasked instructions, for instance: (input → output) vnot.v v8, v4, v0.t → vnot.v v8, v4, v0.t ​vnot.v v8, v4 → vxor.vi v8, v4, -1 AFAICT RISC-V

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

fpallares added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2283 + unsigned Src2Reg = Inst.getOperand(1).getReg(); + if (DestReg == Src2Reg) +return Error(Loc, "The destination vector register group cannot overlap"

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

HsiangKai marked an inline comment as done. HsiangKai added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2283 + unsigned Src2Reg = Inst.getOperand(1).getReg(); + if (DestReg == Src2Reg) +return Error(Loc, "The destination

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

fpallares added a comment. Hi Kai, I've added an inline comment regarding constraint validation: Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2283 + unsigned Src2Reg = Inst.getOperand(1).getReg(); + if (DestReg == Src2Reg) +return Error(Loc,

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

fpallares added a comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D69987 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

HsiangKai added a comment. In D69987#1853986 , @HsiangKai wrote: > Update to version 0.8-draft-20191213. Hi Roger, I have updated it to 0.8-draft-20191213 in February. It is the same as version 0.8. Sorry for that I did not update the commit message.

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

rogfer01 added a comment. @HsiangKai: just to confirm and to avoid confusion for other reviewers. > Assemble/disassemble RISC-V V extension instructions according to version > 0.8-draft-20191004 in https://github.com/riscv/riscv-v-spec/. Is the patch against the spec published in

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

HsiangKai added a comment. Is this patch ready to land? Are there any comments or suggestions I missed? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D69987 ___

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

simoncook added a reviewer: simoncook. simoncook added a comment. This is looking good, overall the patch is nicely laid out which has made it easy to compare against the spec. I've made a few comments, mostly about ordering of instructions so that they are identical to the spec. One