-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Kevin O'Connor
Sent: Sunday, June 08, 2008 11:38 PM
To: coreboot@coreboot.org
Subject: [coreboot] latest legacybios update
Hi,
I've made some recent progress with legacybios. The code will now
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of bari
Sent: Sunday, June 08, 2008 11:52 PM
To: [EMAIL PROTECTED]
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] V2 Orders of Initialization of Devices
Joseph Smith wrote:
Does the order of
Hello,
Does anyone know the mathematical formula for converting memory clock cycles
into microseconds (us)??
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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On 07/06/08 21:23 -0700, Chris Kilgour wrote:
http://www.whiterocker.com/gpxe/
FYI - At this point I don't plan to submit any patches to gPXE as my
approach is rather hackish and still experimental.
I really like this patch:
http://www.whiterocker.com/gpxe/libpayload-lplconsole.patch
We
Hello,
Does anyone know the mathematical formula for converting memory clock
cycles
into microseconds (us)??
1 MHz means 1 million clock cycles per second, so 1 clock cycle per
microsecond.
166 MHz - 166 clock cycles per microsecond.
Thanks,
Myles
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I can't use svn protocol, because my firewall permits only the
standard ports for ftp, http and https, etc. So, I accessed
the filo-0.5 URI:
http://openbios.org/viewvc/trunk/filo-0.5/?root=FILO
Next, I clicked the Download GNU tarball link with URI:
On Sun, Jun 08, 2008 at 11:37:40PM -0400, Kevin O'Connor wrote:
I plan on hacking coreboot-v2 so that it deploys the tables to the
top of ram instead of 0xf. I then plan on having legacybios
locate the tables (by looking at the coreboot table) and then copy
the subset of tables that must
On Mon, 9 Jun 2008 09:53:02 -0600, Myles Watson [EMAIL PROTECTED]
wrote:
Hello,
Does anyone know the mathematical formula for converting memory clock
cycles
into microseconds (us)??
1 MHz means 1 million clock cycles per second, so 1 clock cycle per
microsecond.
166 MHz - 166 clock
On Mon, Jun 09, 2008 at 01:06:08PM -0400, Joseph Smith wrote:
Does anyone know the mathematical formula for converting memory
clock cycles into microseconds (us)??
1 MHz means 1 million clock cycles per second, so 1 clock cycle
per microsecond.
166 MHz - 166 clock cycles per
Peter Stuge wrote:
Do we really want these BIOS tables to be created by coreboot?
If yes, why shouldn't LegacyBIOS simply be included in coreboot?
I definitely think it should. We have half a legacybios in there for VGA
init anyways.
Obviously as an option. Or, rather, as a dependency
On Mon, 09 Jun 2008 19:20:30 +0200, Stefan Reinauer [EMAIL PROTECTED]
wrote:
Peter Stuge wrote:
Do we really want these BIOS tables to be created by coreboot?
If yes, why shouldn't LegacyBIOS simply be included in coreboot?
I definitely think it should. We have half a legacybios in
Peter Stuge wrote:
I still don't want coreboot to know about BIOS tables at all.
Alas, it already does, there is both PIR and ACPI.
Because they are required by Linux.
Do we really want these BIOS tables to be created by coreboot?
probably.
If yes, why shouldn't LegacyBIOS simply be
On Mon, Jun 09, 2008 at 01:23:21PM -0400, Joseph Smith wrote:
If yes, why shouldn't LegacyBIOS simply be included in coreboot?
I definitely think it should. We have half a legacybios in there
for VGA init anyways.
Obviously as an option. Or, rather, as a dependency when you choose
the
On Mon, 9 Jun 2008 19:14:32 +0200, Peter Stuge [EMAIL PROTECTED] wrote:
On Mon, Jun 09, 2008 at 01:06:08PM -0400, Joseph Smith wrote:
Does anyone know the mathematical formula for converting memory
clock cycles into microseconds (us)??
1 MHz means 1 million clock cycles per second, so
On Mon, Jun 09, 2008 at 11:23:51AM -0600, Marc Jones wrote:
I still don't want coreboot to know about BIOS tables at all.
Alas, it already does, there is both PIR and ACPI.
Because they are required by Linux.
Wasn't that supposed to change though? Does anyone know what happened
with the
On Mon, Jun 09, 2008 at 01:36:29PM -0400, Joseph Smith wrote:
Does anyone know the mathematical formula for converting memory
clock cycles into microseconds (us)??
1 MHz means 1 million clock cycles per second, so 1 clock cycle
per microsecond.
166 MHz - 166 clock cycles per
On Mon, 9 Jun 2008 19:47:24 +0200, Peter Stuge [EMAIL PROTECTED] wrote:
On Mon, Jun 09, 2008 at 01:36:29PM -0400, Joseph Smith wrote:
Does anyone know the mathematical formula for converting memory
clock cycles into microseconds (us)??
1 MHz means 1 million clock cycles per second,
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello all,
I'm trying to get the Asus M2V-MX SE working (K8T890/VT8237S) it has AM2 socket.
CPU is semperon model 127 fam f
Currently there is some problem with memory, I have attached the log.
I have no clue what might be wrong. The module is 512MB
On Mon, 9 Jun 2008 19:39:50 +0200, Peter Stuge [EMAIL PROTECTED] wrote:
On Mon, Jun 09, 2008 at 11:23:51AM -0600, Marc Jones wrote:
I still don't want coreboot to know about BIOS tables at all.
Alas, it already does, there is both PIR and ACPI.
Because they are required by Linux.
On Mon, Jun 09, 2008 at 09:50:30PM +0200, Rudolf Marek wrote:
I dont understand why:
...
Setting variable MTRR 02, base: MB, range: 0200MB, type WB
...
The range is only to 200MB ???
I believe this is hex, so 512MB decimal.
I have no other DDR2 module to check.
Could you test the
On Mon, Jun 09, 2008 at 05:48:11PM -0400, Joseph Smith wrote:
On Mon, 9 Jun 2008 23:43:10 +0200, Peter Stuge [EMAIL PROTECTED] wrote:
On Mon, Jun 09, 2008 at 03:15:46PM -0400, Joseph Smith wrote:
How hard would it be to add a nanoseconds delay to delay.h?
It would probably have to be a
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Peter Stuge wrote:
On Mon, Jun 09, 2008 at 09:50:30PM +0200, Rudolf Marek wrote:
I dont understand why:
...
Setting variable MTRR 02, base: MB, range: 0200MB, type WB
...
The range is only to 200MB ???
I believe this is hex, so 512MB
Rudolf Marek wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello all,
I'm trying to get the Asus M2V-MX SE working (K8T890/VT8237S) it has AM2
socket.
CPU is semperon model 127 fam f
I have no clue what might be wrong. The module is 512MB 533MHz single DDR2
with
CAS4.
It
On Tue, Jun 10, 2008 at 12:53:01AM +0200, Rudolf Marek wrote:
Hum it seems that there is some watchdog somewhere, it resets the
board even in while (1) {} loop. It seems to take 4 seconds. The
IT8712 seems to have one. Will investigate further.
4 seconds reminds me of the hardware power switch
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Peter Stuge
Sent: Monday, June 09, 2008 6:03 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] Memory clock cycles - microseconds (us)
On Mon, Jun 09, 2008 at 05:48:11PM -0400, Joseph Smith
gcc -m32 -Wall -Os -fomit-frame-pointer -fno-common -ffreestanding
-fno-strict-aliasing -Wno-unused -nostdinc -imacros ../config.h
-I../include -I/usr/lib/gcc/i486-linux-gnu/4.1.2/include -MD -c printf.c
-o printf.o
What does this with -E show? This is really weird.
ron
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coreboot mailing
On Mon, Jun 09, 2008 at 07:03:46PM +0200, Peter Stuge wrote:
On Sun, Jun 08, 2008 at 11:37:40PM -0400, Kevin O'Connor wrote:
http://www.coreboot.org/pipermail/coreboot/2008-May/034688.html
I'm basically advocating option (c).
Do we really want these BIOS tables to be created by
On Mon, Jun 09, 2008 at 09:37:45PM -0400, Joseph Smith wrote:
See where I am going with this?
Sorry, not at all.
Of course it would be nice to not spend more time than neccessary
on waits during RAM init.
But nanosecond precision is more difficult than microsecond
precision, and unless there
Busy wait is a loop of some number of NOP instructions, as opposed to
relying on some CPU peripheral such as a timer to signal elapsed
time. The number of NOP instructions has to be calculated from the
current CPU frequency.
That seems more complicated than it needs to be. Here is what I am
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