Carl-Daniel Hailfinger wrote:
On 14.11.2008 19:54, ron minnich wrote:
On Fri, Nov 14, 2008 at 10:52 AM, Stefan Reinauer [EMAIL PROTECTED] wrote:
Carl-Daniel Hailfinger wrote:
We're missing one crucial piece which is necessary to get PIC to work:
The linker. PIC
Corey Osgood wrote:
Should we just succumb to the way a factory BIOS does it? Initialize a
minimal amount of ram with the default chipset timings in initram,
then do a full blown ram init once we've got some real memory to work
off of? Or would that not solve the problem?
I have not
coreboot-v2 has been giving the following error:
PCI: 00:01.0 init
set power on after power fail
RTC Init
Invalid CMOS LB checksum
PNP: 002e.1 init
I have put some debugging in rtc_checksum_valid of mc146818rtc.c to
output the variables, and got
PU model AMD Athlon(tm) 64 X2 Dual Core
On 15.11.2008, at 11:47, Chris Lingard [EMAIL PROTECTED] wrote:
coreboot-v2 has been giving the following error:
PCI: 00:01.0 init
set power on after power fail
RTC Init
Invalid CMOS LB checksum
PNP: 002e.1 init
I have put some debugging in rtc_checksum_valid of mc146818rtc.c to
output the
Stefan Reinauer wrote:
On 15.11.2008, at 11:47, Chris Lingard [EMAIL PROTECTED] wrote:
coreboot-v2 has been giving the following error:
The first sum is the 'normal of bios checksum' while the second is an
extended checksum.
You can correct it by changing a setting with nvramtool
On 14.11.2008 17:33, FENG Yu Ning wrote:
On 11/14/08, Carl-Daniel Hailfinger [EMAIL PROTECTED] wrote:
Index: flashrom-atmel/flash.h
===
--- flashrom-atmel/flash.h (Revision 3751)
+++ flashrom-atmel/flash.h (Arbeitskopie)
On 14.11.2008 04:17, Carl-Daniel Hailfinger wrote:
The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with
On Thu, Nov 13, 2008 at 8:17 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
This is needed for some Intel boards.
Patch attached for Gmail users.
Signed-off-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Index:
Author: hailfinger
Date: 2008-11-15 14:55:43 +0100 (Sat, 15 Nov 2008)
New Revision: 3754
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
trunk/util/flashrom/spi.h
Log:
The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
The AT45 series SPI chips are
On 15.11.2008 14:26, Myles Watson wrote:
On Thu, Nov 13, 2008 at 8:17 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
This is needed for some Intel boards.
Patch attached for Gmail users.
Signed-off-by: Carl-Daniel
This patch makes it so there's not so much extra information in pnp_info.
IRQs and DRQs just need values. It also moves enable to the end so it
doesn't look like it needs to be set in superio.c. It just needs to be set
in the dts. I decided that it makes sense to create a serial port and
All unknown SPI chips claim to have status UNTESTED for
probe/read/erase/write. That's incorrect. Since the chips are unknown,
read/erase/write are unavailable for them. And if probe worked, they
wouldn't have needed the generic vendor match in the first place. Mark
those chips as BAD for
Author: uwe
Date: 2008-11-15 17:13:12 +0100 (Sat, 15 Nov 2008)
New Revision: 1029
Modified:
coreboot-v3/mainboard/via/epia-cn/stage1.c
Log:
Fix EPIA-CN build in v3 by dropping duplicated stop_ap() definition (trivial).
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Uwe Hermann [EMAIL
Author: uwe
Date: 2008-11-15 17:17:12 +0100 (Sat, 15 Nov 2008)
New Revision: 1030
Removed:
coreboot-v3/superio/via/vt1211/superio.c
Modified:
coreboot-v3/superio/via/vt1211/stage1.c
Log:
Drop non-working, copy-paste superio.c file (trivial).
The build system isn't even using it so far, but
See patch.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Fix the incorrect VIA VT1211 LDNs, add a comment for each of them.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Index:
See patch.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Fix some incorrect entries in superio/winbond/w83627hf/dts.
The hardware monitor defaults as per datasheet are 0x / 0, but on
hardware that
[EMAIL PROTECTED] wrote:
Log:
The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
Then they do not belong in the flashrom code at all.
//Peter
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On 15.11.2008 18:50, Peter Stuge wrote:
[EMAIL PROTECTED] wrote:
Log:
The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
Then they do not belong in the flashrom code at all.
Why?
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
--
coreboot mailing list:
Anyone know if USB ports have power feedback protection. What I mean by
that is if I use the LPCflasher as a inline flasher with a PLCC32 socket
plug, flash the chip and then power up the motherboard, I don't want the
VCC's from the motherboard to short out the flasher and or the USB port
from
On 15.11.2008 17:20, Uwe Hermann wrote:
Fix the incorrect VIA VT1211 LDNs, add a comment for each of them.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
--
coreboot mailing list:
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Uwe Hermann
Sent: Saturday, November 15, 2008 10:12 AM
To: coreboot@coreboot.org
Subject: [coreboot] [PATCH] v3: Fix parts of the Winbond W83627HF dts
See patch.
Fix some incorrect entries in
On Sat, 15 Nov 2008 16:09:58 -0500, [EMAIL PROTECTED] wrote:
Host USB ports are supposed to use a MosFET with internal current sense
for
power protection. The FET signals the O/S when its current threshold is
being
exceeded and then the O/S suspends the port and removes power.
If you
Hi
You could diode isolate the vin to a buck boost to isolate it's input and you
can diode isolate its output to create a pseduo isolated regulator that would
prevent reverse bias from being a big problem.
Typically, the output stage of a buck/buck-boost regulator is an inductor-
capacitor.
Joseph Smith wrote:
I wasn't really ready to release this yet
Very similar to the cheaplpc orignally by Andy Green of warmcat.com
it was orphaned a few years ago and then adopted by cheaplpc.com.
Have a look there. The software is there too.
//Peter
--
coreboot mailing list:
On Sun, 16 Nov 2008 00:20:07 +0100, Peter Stuge [EMAIL PROTECTED] wrote:
Joseph Smith wrote:
I wasn't really ready to release this yet
Very similar to the cheaplpc orignally by Andy Green of warmcat.com
it was orphaned a few years ago and then adopted by cheaplpc.com.
Have a look there.
On Sat, Nov 15, 2008 at 2:29 PM, Joseph Smith [EMAIL PROTECTED] wrote:
Anyone know if USB ports have power feedback protection. What I mean by
that is if I use the LPCflasher as a inline flasher with a PLCC32 socket
plug, flash the chip and then power up the motherboard, I don't want the
VCC's
Author: hailfinger
Date: 2008-11-16 02:22:18 +0100 (Sun, 16 Nov 2008)
New Revision: 1031
Modified:
coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c
coreboot-v3/northbridge/intel/i945/stage1.c
coreboot-v3/southbridge/intel/i82801gx/smi.c
On Sat, 15 Nov 2008 18:50:23 -0500, Tom Sylla [EMAIL PROTECTED] wrote:
You will have a target PC for which you are developing firmware.
Some sort of PCB or protoboard with one PLCC socket and one PLCC
stacking connector will be plugged into the ROM socket of that PC.
A ROM device will be
Author: hailfinger
Date: 2008-11-16 02:52:08 +0100 (Sun, 16 Nov 2008)
New Revision: 1032
Modified:
coreboot-v3/superio/winbond/w83627thg/stage1.c
coreboot-v3/superio/winbond/w83627thg/superio.c
Log:
Drop duplicated functions from W83627THG SuperI/O stage1 code and fix
up a function
Yes, I will get the datasheet and send you a recommened link when I get
back to my office Monday
From: Joseph Smith [EMAIL PROTECTED]
Date: 2008/11/15 Sat PM 06:44:34 EST
To: [EMAIL PROTECTED]
CC: Peter Stuge [EMAIL PROTECTED], coreboot coreboot@coreboot.org
Subject: Re: [coreboot]
On 15.11.2008 00:02, ron minnich wrote:
The thing almost builds now.
Fixed the 'array of pointers' in a way that will work for now. Many
other fixes. superio updated.
I slapped a meaningful changelog on the superio changes and committed
them in r1032.
Regards,
Carl-Daniel
--
On Sat, 15 Nov 2008 20:55:30 -0500, [EMAIL PROTECTED] wrote:
Yes, I will get the datasheet and send you a recommened link when I get
back to my office Monday
Ok thanks, can you point me to an example schematic on the web
somewhere?
Thanks I would really appreciate it.
--
Thanks,
Joseph
Carl-Daniel Hailfinger wrote:
All unknown SPI chips claim to have status UNTESTED for
probe/read/erase/write. That's incorrect. Since the chips are unknown,
read/erase/write are unavailable for them. And if probe worked, they
wouldn't have needed the generic vendor match in the first
On Sat, Nov 15, 2008 at 6:14 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
Attached are the non-committed parts of your patch.
It would be great if someone besides me could look at extracting chunks
and merging them.
Thanks. I hope somebody will pick these up. I am gone next 7 days so
On Sat, Nov 15, 2008 at 4:49 AM, Chris Lingard [EMAIL PROTECTED] wrote:
Stefan Reinauer wrote:
On 15.11.2008, at 11:47, Chris Lingard [EMAIL PROTECTED] wrote:
coreboot-v2 has been giving the following error:
The first sum is the 'normal of bios checksum' while the second is an
extended
On Fri, Nov 14, 2008 at 10:02 PM, Corey Osgood [EMAIL PROTECTED] wrote:
Sure there are, CN700 in v2 uses a safe (read: slowest possible) set of
timings that seems to work on all the memory I've thrown at it. AFAIK DDR2
doesn't like running too much slower then spec, but it can handle quite a
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