On 2011.07.15 03:35, Scott Duplichan wrote:
Thanks for the clock code. It works on asrock e350m1 with the attached
patch.
Wow, great!
Thanks a lot for testing it. Did you also try full autodetection, or did
you just try forced base/type/ldn?
Regards,
/Pete
--
coreboot mailing list:
Also, if it's not too much to ask and if the code works without
FORCE_PANIC, I wouldn't mind finding out where it breaks if not using
the 48 MHz init (using forced base/type/ldn).
I have now committed your patch to svn. Will still need to figure out
what the best approach might be with
Patrick Georgi (patr...@georgi-clan.de) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/103
-gerrit
commit 8fc9a65e9d4579e64d7a6470c2ab7b4ed61a1aec
Author: Patrick Georgi patrick.geo...@secunet.com
Date: Thu Jul 7 15:41:53 2011 +0200
libpayload:
Patrick Georgi (patr...@georgi-clan.de) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/104
-gerrit
commit 40fcefcdcfa74405fc3c6fba571557520d4c3096
Author: Patrick Georgi patrick.geo...@secunet.com
Date: Tue Jul 12 15:02:04 2011 +0200
libpayload:
the following patch was just integrated into master:
commit e1bf4df28b64e4758f3220afb37f14fcea97669d
Author: efdesign98 efdesig...@gmail.com
Date: Wed Jul 13 16:43:39 2011 -0700
Add the AMD Family10 Agesa code
This change officially adds the Agesa code for the AMD Family 10
Patrick Georgi (patr...@georgi-clan.de) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/105
-gerrit
commit 85b688852fe4d3d3e5b76edbb91cdd553d7bd3ca
Author: Patrick Georgi patrick.geo...@secunet.com
Date: Tue Jul 12 15:50:54 2011 +0200
libpayload:
Hi folks;
I've got a MSI350IA-E45 board, which is a AMD fam 14h board with a AMD
SB700/800 southbridge. I'd like to contribute by porting coreboot to the
board, but I'm not sure where to start; there's no LPC header!
I threw together a patch-cable for my secondary LPC bios, and the board
doesn't
#177: Not compiling coreBoot
-+--
Reporter: darkshvein@… | Owner: stepan@…
Type: defect|Status: new
Priority: major | Milestone:
Component: coreboot | Keywords:
#178: linux kernel hang while boot from SATA SSD on EPIA CN
---+--
Reporter: ryzhovsergey@… | Owner: stepan@…
Type: defect |Status: new
Priority: major | Milestone:
#179: Coreboot on GigaByte GA-8IEXP ver. 1.2
--+--
Reporter: BlackSheep0@… | Owner: stepan@…
Type: enhancement|Status: new
Priority: minor | Milestone: Going mainstream
Component:
Hello Andrew,
AMD SB800-ish southbridges will only selectively fetch BIOS from LPC or SPI
based on straps. Your board won't fetch from LPC unless you change the strap
(which are unknown resistors on your board).
Your best option is SPI in-system programming, and you can just use the SPI
header
Am Freitag, 15. Juli 2011 15:06:32, Tadas Slotkus schrieb:
If our codebase is ready, I mean the
default settings build the right image, we may want to provide similar
tool too.
I fear this will only work reliably once we have vendor adoption
(because they're free to change board designs while
Am Freitag, 15. Juli 2011 04:11:47, Hongyuan Zhu schrieb:
Unpacked and patched ... ok
Building GMP 5.0.1 ... failed
make[1]: *** [build] 错误 1
make: *** [crossgcc] 错误 2
look in build-gmp/, there will be a log file detailling the problem
(crossgcc-build.log)
Patrick
--
coreboot mailing
Am Freitag, 15. Juli 2011 04:01:55, Tadas Slotkus schrieb:
I found out difficulties with pci access functions in CAR as they tend
to eat memory dynamically - with malloc calls. Any suggestions?
Try to determine how much memory it uses and what the patterns are. If
the code never frees until the
So, It's been quite a while (5 years) since I have submitted anything
substantial to the OE project. It looks like I may be getting back into
this some, however. I have a couple of minor changes/additions after
this, so please let me know if I am missing the process somehow.
I am CC-ing the
On x86, and ELF image file may be stored as a coreboot payload. This
image file may be a kernel or a kernel+initrd.
Documentation on this has been started on the coreboot wiki:
http://www.coreboot.org/Mkelfimage
We have seen success using the mkelfimage utility to construct a
kernel+initrd
On x86, and ELF image file may be stored as a coreboot payload. This
image file may be a kernel or a kernel+initrd.
Documentation on this has been started on the coreboot wiki:
http://www.coreboot.org/Mkelfimage
We have seen success using the mkelfimage utility to construct a
kernel+initrd
Dear Raymond,
I am putting you in CC not knowing if you read the lists.
Am Freitag, den 15.07.2011, 10:55 -0600 schrieb Raymond Danks:
The correct commit summary is
mkelfimage: Add version c045b4cc from Git (initial recipe)
On x86, and ELF image file may be stored as a coreboot
Dear Raymond,
thank you for your patch!
Am Freitag, den 15.07.2011, 10:55 -0600 schrieb Raymond Danks:
On x86, and ELF image file may be stored as a coreboot payload. This
image file may be a kernel or a kernel+initrd.
Documentation on this has been started on the coreboot wiki:
Frank Vibrans III (efdesig...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/102
-gerrit
commit 2df301924ace4d1792e60424091ff29745a3f658
Author: Tadas Slotkus devta...@gmail.com
Date: Fri Jul 15 03:41:11 2011 +0300
Libpayload: default
Frank Vibrans III (efdesig...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/103
-gerrit
commit 5fe8ae6b88a091abd58da2aa4e81c247bae1d59f
Author: Patrick Georgi patrick.geo...@secunet.com
Date: Thu Jul 7 15:41:53 2011 +0200
libpayload:
Frank Vibrans III (efdesig...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/101
-gerrit
commit deb36c32e1de7344d9df157be6fbe9b3293fd0bc
Author: Steven A. Falco sfa...@coincident.com
Date: Thu Jul 14 19:56:50 2011 -0400
Do not use C
Frank Vibrans III (efdesig...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/104
-gerrit
commit 2ebc01624221519a82119286b121e218bb5a2df7
Author: Patrick Georgi patrick.geo...@secunet.com
Date: Tue Jul 12 15:02:04 2011 +0200
Frank Vibrans III (efdesig...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/105
-gerrit
commit d1ce5cef9b95d4309bc2b9a80cb08c3cc21b6f7d
Author: Patrick Georgi patrick.geo...@secunet.com
Date: Tue Jul 12 15:50:54 2011 +0200
Frank Vibrans III (efdesig...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/97
-gerrit
commit 4c33370274f7f0568d55421ed5024e79c0e6d548
Author: efdesign98 efdesig...@gmail.com
Date: Wed Jul 13 17:16:13 2011 -0700
Add AMD Family 10
Thanks Paul. I am putting together new patches to address your feedback
on style guide, mailer line-feed, and patch format/commit policy.
As far as the build configuration this was tested on is concerned, this
is Ubuntu 10.04 x86_64-linux targeting i686-oe-linux using a one-off of
the
When using SeaBios you can select another payload (flashrom)
to execute instead of loading OS. Also for payload development,
little
trimmed SeaBios with CBFS support could be used - this invokes
flashrom
or the development payload or even another full-featured SeaBios.
This works with
Frank Vibrans III (efdesig...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/109
-gerrit
commit ba66858bbb5708c1add2aab61f70106154132b4e
Author: efdesign98 efdesig...@gmail.com
Date: Fri Jul 15 17:10:43 2011 -0700
Add xhcbios and
It seems like it might not be able to read SPD at all. It is possible
your DIMM has SMBus signaling difficulty when run at 400 KHz. You could
try running the SMBus at the default frequency (93750 KHz) by removing
the last statement in function setupFch in file dimmSpd.c:
static void
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