Re: [coreboot] TXE and Descriptor bin management in Coreboot

* Mayuri Tendulkar [160714 00:50]: > Ok, so do we need to ask Intel if we use Intel baytrail processor? How we can > create this descriptor.bin? Please have a look at util/ifdtool and util/ifdfake for our tools dealing with Intel Firmware Descriptors. The most

Re: [coreboot] TXE and Descriptor bin management in Coreboot

Ok, so do we need to ask Intel if we use Intel baytrail processor? How we can create this descriptor.bin? What we observed is if we use descriptor.bin, and not TXE, still system boots up fine. Need to understand the impact of not having TXE. But if we don't use descriptor, it seems system is

Re: [coreboot] TXE and Descriptor bin management in Coreboot

Hi Mayuri, The descriptor.bin file is relatively specific to each board. This sets the soft-straps, gives information about the ROM chip being used on that particular board, and sets the sizes of the areas on the SPI ROM. As for the TXE/ME/SPS/xxx binary, this would be specific to the CPU/SOC

[coreboot] TXE and Descriptor bin management in Coreboot

Hi Team I would like to know how we can handle TXE and descriptor bin in Coreboot? Is there any generic file for Intel processors which can be used rather than any proprietary bin files? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of

Re: [coreboot] How to read the gpio status?

* ��?�?��?? [160713 06:39]: > When write 0x7000 write to SC_GP_LVL, Can read the 0x00 from SC_GP_LVL. > everytime. Are you by any chance doing an 8 bit read (0x00) instead of a 16 bit read (0x)? Stefan -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] ARM Trusted Firmware build issue

* Martin Roth [160713 16:57]: > We can't roll the entire toolchain back to binutils 2.25 because of > the RISC-V work. Is it reasonable to roll back to binutils 2.25 for > just the ARM toolchain builds? No, that is not feasible. The cross toolchain builder has seen a fair

[coreboot] A word on releases

Hi people, we have had a great first year with regular coreboot releases. Exactly 12 months ago, we released coreboot 4.1, the first release after the 4.0 release in 2011 and our "classic" branch in 2014. Since then we have had 4 successful releases, both Patrick and Martin went through the

Re: [coreboot] ARM Trusted Firmware build issue

Le mercredi 13 juillet 2016 à 12:47 -0600, Martin Roth a écrit : > Ok, I tested updating the code from '.align x,0' to '.align x'.  This > updates the padding from 0x00 to nop instructions, and does work with > GAS 2.26. > > I've submitted a pull request for the arm-trusted-firmware repo: >

Re: [coreboot] ARM Trusted Firmware build issue

Ok, I tested updating the code from '.align x,0' to '.align x'. This updates the padding from 0x00 to nop instructions, and does work with GAS 2.26. I've submitted a pull request for the arm-trusted-firmware repo: https://github.com/ARM-software/arm-trusted-firmware/pull/664 Martin On Wed, Jul

Re: [coreboot] Help on setting clock speed in coreboot

Mayuri, Yes, the easiest way to check if your custom HW is working, to try TX/RX using Linux Distros Ubuntu or Fedora 24 (I use for all INTEL HW testings ONLY Fedora 14 and up (latest F24), since I am very very familiar with Fedora). With putty package, I (at least, not the last) am very familiar

Re: [coreboot] Help on setting clock speed in coreboot

Mayuri Tendulkar wrote: > serial is still having some issue and keeps giving out some garbage, > not sure what is the problem. Please share an oscilloscope capture image of the very first character sent out on the TX pin after power-on. //Peter -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Help on setting clock speed in coreboot

Zoran Stojsavljevic wrote: > (with Intel BIOS Vendors - IBVs helping you) As far as I know the 'I' in IBV stands for Independent. Regarding the original problem that the serial port output is garbled, please share a scope capture of the UART TX pin from power-on to get further help with

Re: [coreboot] Help on setting clock speed in coreboot

Hi Zoran Thanks for ur suggestions. When I mentioned I got brkthru means- I was able to bringup coreboot with seabios and Ubuntu linux up on my customized board with E3845. Display comes up fine. But serial is still having some issue and keeps giving out some garbage, not sure what is the

Re: [coreboot] Help on setting clock speed in coreboot

> We got some brkthru today. Though serial still shows garbage, *we got bios up and then OS also*. > USB, display came up, but serial still no luck. I assumed in my answer that your reference INTEL Valley Island board with E3825 works with serial port. Did not get the point. Did you get Coreboot

Re: [coreboot] ARM Trusted Firmware build issue

Hi, Le mercredi 13 juillet 2016 à 08:57 -0600, Martin Roth a écrit : >   Thanks for posting about this.  I've spent some time looking into > this as well, but in my usual fashion, I didn't communicate what I > found in a responsible fashion.  Here's what I posted in a code > review: Looks like I

Re: [coreboot] ARM Trusted Firmware build issue

Hi Paul, Thanks for posting about this. I've spent some time looking into this as well, but in my usual fashion, I didn't communicate what I found in a responsible fashion. Here's what I posted in a code review: > The current binutils (2.26) is failing to build the current >

[coreboot] ARM Trusted Firmware build issue

We spent some time yesterday evening on IRC investigating why the ARM Trusted Firmware (ATF) doesn't build with the current toolchain from coreboot's crossgcc. It turns out it is a complex issue on the assembler's side. I have opened a bug upstream about it, with all the details we could find:

Re: [coreboot] How to read the gpio status?

*> When write 0x7000 write to SC_GP_LVL, Can read the 0x00 from SC_GP_LVL. everytime.* Please, try to do the following exercise: [1] WR 0x1000 to SC_GP_LVL, then RD the value out of it: what it is? [2] WR 0x2000 to SC_GP_LVL, then RD the value out of it: what it is? [3] WR 0x4000 to SC_GP_LVL,