Re: [coreboot] How to understand register address on x86?

Hello 김유석, Here is the alghoritm how you'll calculate the address: SLOTCAP address (B0:D1-4:F0:Offset 0x54[31:19]). There are 16 bits for PCIe space: [1] 8 most significant bits for buses (256 maximum); [2] 5 bits for device ids (32 maximum) per bus; [3] 3 bits for functions (8 maximum) per

Re: [coreboot] SMBIOS table enablement in coreboot

Hi Mayuri, Do you have GENERATE_SMBIOS_TABLES enabled in your config? On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar < mayuri.tendul...@aricent.com> wrote: > Hi > > We are using coreboot for our board based on Intel Baytrail 3845. > > > > When we use *dmidecode –t *to get DDR details, we get

Re: [coreboot] Question about PCIe separate reference clock

On Fri, Jan 13, 2017 at 6:01 PM, Zheng Bao wrote: > About "Asynchronous clock mode on mainboard side", I guess. > > > Both the device and bridge have the fields "slot clock configuration" and > "common clock configuration". > Again assuming the mainboard side is CPU (some

Re: [coreboot] Question about PCIe separate reference clock

About "Asynchronous clock mode on mainboard side", I guess. Both the device and bridge have the fields "slot clock configuration" and "common clock configuration". On our board, both the"slot clock configuration" of device (E8860) and bridge are 1. Does it mean the "on mainboard" side it

Re: [coreboot] Question about PCIe separate reference clock

Hi Zheng, Schematic is simple and OK. I assume you are trying to run Wolf VPXxx-E8860- or similar GPU borad. You can't do much there if there is a hardware problem but it is most possibly a software setup problem. VPX does not have incomming clock so it is by default in async_clock mode. The

[coreboot] Using as default external monitor for booting in x230

Hi all, First thanks to all for such an amazing job, I just realized that Coreboot is already working in the lenovo x230, and I am really thinking in flash it and give a try :) But since I have a mod in my x230 for having FHD (edp screen), somehow I will need to somehow setup on the bios that

[coreboot] New Defects reported by Coverity Scan for coreboot

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 32 new defect(s) introduced to coreboot found with Coverity Scan. 12 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New

[coreboot] SMBIOS table enablement in coreboot

Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode -t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is