Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard

I see PSP blobs are included in the coreboot (3rd party) so not sure if that is the issue. Anyone who has worked or tested or added patches on this board, please let me know if you have any suggestions. On Wed, Apr 26, 2017 at 2:35 AM, taii...@gmx.com wrote: > Doesn't that

Re: [coreboot] Unable to run QEMU for Intel Rangeley Mohon Peak

Hi Martin, Thanks for the info. -Dhanasekar On Wed, Apr 26, 2017 at 7:00 AM, Martin Roth wrote: > Hi Dhanasekar, > > You built a BIOS for Mohon Peak, and it's not running on QEMU? I > wouldn't expect that to work. That's why we have the coreboot builds > that are

Re: [coreboot] Unable to run QEMU for Intel Rangeley Mohon Peak

Hi Dhanasekar, You built a BIOS for Mohon Peak, and it's not running on QEMU? I wouldn't expect that to work. That's why we have the coreboot builds that are specifically for QEMU. You wouldn't expect to be able to pull the BIOS off of one board, drop it onto another board and have it work,

Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard

Doesn't that board need PSP blobs? (what a shame) Maybe that is the issue you are having. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer

Managed to get it working with serial input now. Found a few issues with my patch. Will send a new, tested version out. On Tue, Apr 25, 2017 at 11:48 AM, Julius Werner wrote: > Did you check that all implementations use unsigned? >> > > Yes, all the ones that I'm now aware

Re: [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer

> > Did you check that all implementations use unsigned? > Yes, all the ones that I'm now aware of used unsigned, 32-bit. > I am able to build it, I just had to figure out how and install some >> dependencies. But I tried booting it on an HP Chromebook 14 2013 (falco) >> and it doesn't seem to

Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard

​Yes, that is correct; I actually struggled with this sort of problem for a while, on my system the issue was that it would get past coreboot to stop within SeaBIOS execution. Does your system have usb ports? If it does, the usb enumeration happens within coreboot, so a test might be to see

Re: [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer

On Tue, Apr 25, 2017, 20:15 Julius Werner wrote: > I'm very concerned with compatibility. You can't guarantee that coreboot >> and payload match. And in case of mismatch you get a memory corruption that >> is very hard to trace. Can we please change signature of cbmem

Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard

Hi, Thanks for the steps, I appreciate it. If I understand correctly I would be able to use this tool when Linux boots with coreboot. But the issue I have is, coreboot not coming up on the board rather I am not sure if it's coming up because I don't see anything on the screen and there is no

Re: [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer

> > I'm very concerned with compatibility. You can't guarantee that coreboot > and payload match. And in case of mismatch you get a memory corruption that > is very hard to trace. Can we please change signature of cbmem entry? I would rather allow older implementations to continue working as

Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard

​ Hello , cbmem is a utility located in .../coreboot/util/cbmem. You will have to fully boot into linux to use this coreboot utility. You will also have to have the ability to re-flash your coreboot rom because there are some coreboot configuration changes. What I do to install and run is as

Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard

I included the microcode updates but no luck. The PCI IDs seem to be correct for Mullins [Radeon R3 Graphics] ( http://pci-ids.ucw.cz/read/PC/1002). *There is no serial port in the Olive Hill Plus board*. *What are my options*? Also how do i use this tool in util/cbmem/ ? I am using the default

[coreboot] Intel ME The Way of the Static Analysis

slide: https://www.troopers.de/downloads/troopers17/TR17_ME11_Static.pdf video: https://www.youtube.com/watch?v=2_aokrfcoUk -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] New Defects reported by Coverity Scan for coreboot

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1374543: Possible Control flow issues (DEADCODE)

[coreboot] Confusing about displayed POST CODE values

Dear all, I'm using Intel Leaf Hill CRB with coreboot. Sometimes, the postcode value is "08". But sometimes it shows "8" only. Are they the same postcode? If not, what is difference? Thanks and BRs, Toan -- coreboot mailing list: coreboot@coreboot.org

[coreboot] Unable to run QEMU for Intel Rangeley Mohon Peak

Hi All, I am trying to boot Intel Atom Rangeley Sever CPU (Mohon Peak) with coreboot bios and GRUB2 as a Playload. After including GUB2 with Coreboot and running " qemu-system-x86_64 -bios build/coreboot.rom -serial stdio" command,I am getting following error, *" warning: TCG doesn't support

Re: [coreboot] [Apollo-lake]How to create Apollo-lake IFWI.bin for coreboot coding use

Dear Andrey, Thanks your reply, attached file is my sitting XML file , I'm Use Intel (R) Flash Image Tool. Version: 3.0.11.1131, thanks. -James