Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

Hi Nico, The fact that the prior release on GitHub did not include release notes is why I assumed it would work for the -U, when, in fact, it did not - and instead managed to turn the CRBs into boat anchors. First time I've ever seen an FSP be able to completely take down a CRB to where it

Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

Hi Jay, On 08.01.2018 19:35, Jay Talbott wrote: > The release notes for the Kaby Lake FSP on github says it's specifically > just for KabyLake-H. It makes no mention of supporting KabyLake-U. sorry, I might be just blind. But there don't seem to be release notes for the version from June:

Re: [coreboot] 16 GPUs on one board

On Thu, Jan 4, 2018 at 1:33 PM, Arthur Heymans wrote: > Hi > > What target are you on? > > Coreboot tries to locate all PCI BAR's below 4G in the PCI_MMIO region and > above the lower DRAM > limit (the rest of the DRAM is mapped above 4G). Typically a GPU takes > around 256M

Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

Nico, The release notes for the Kaby Lake FSP on github says it's specifically just for KabyLake-H. It makes no mention of supporting KabyLake-U. I initially attempted to use the version that was uploaded to GitHub back on June 22nd, which is the version that caused the bricking of the RVP7

Re: [coreboot] coreboot community meeting January 5th, 2017 report

Thanks for providing this summary. On Fri, Jan 5, 2018 at 8:34 AM, Arthur Heymans wrote: > Dear coreboot community > > This is the report of yesterdays community meeting: > > General coreboot news & Discussion > == > > There is patch [1] up

Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

Hello Jay, On 06.01.2018 07:13, Jay Talbott wrote: > Be careful using the public Kaby Lake FSP from github for SkyLake-U or > KabyLake-U processors… my first attempt resulted in two different CRBs > (one RVP7 and one RVP15) becoming boat anchors – even restoring the > original BIOS made no

Re: [coreboot] 16 GPUs on one board

I have had this issue in regards to SR-IOV, - at the moment coreboot only supports 32Bit MMIO unfortunately one can't have too many graphics devices or network interfaces apparently. Considering the success of the OpenBMC port fund it would be nice if we could get a fund going to fix this if

Re: [coreboot] BDX-DE PCI init fail

Hello Hilbert, After work (somewhere around 19:00 PM CET), I'll look into your logs. Please, stay tuned. I am simply sold out, and have no time for anything else... I will have some advises for you, hopefully! Zoran ___ On Mon, Jan 8, 2018 at 11:57 AM, Hilbert Tu(杜睿哲_Pegatron)

[coreboot] Logging from within romstage? Problems initializing uart

Hi all, I have been asked to clean up my patch enabling SuperIO uart on the intense-pc: https://review.coreboot.org/#/c/coreboot/+/22737/ The SIO1007 is supposed to properly initialize the UART in the sio1007_enable_uart_at(), but when I call it nothing seems to happen and the uart doesn't end

Re: [coreboot] Recommended workflow with Chromebook support

On Fri, Jan 5, 2018 at 6:19 PM, wrote: > Folks, > This question is directed at the Coreboot developers who target a > Chromebook device. > > Do you tend to do bulk of development and testing within chromiumos > coreboot tree or directly in coreboot.org tree? > > As we get

Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

Hi Toan Le, For Sasby Island, which is based on KBL U, you'll need corresponding blobs(me descriptor & ucode). Use kblrvp7 as starting point. And based on schematic(of Sasby Island) & your requirement(interface/device), you may have change settings(like gpio, devicetree.cb etc). Make sure you

Re: [coreboot] EARLY_CBMEM_INIT for Geode LX platforms

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 Hi Kyösti, if you can support us and provide some guidance about correct way of approaching below issue we would appreciate that. On 12/14/2017 04:56 PM, Michal Zygowski wrote: > Hello Everyone, > > As a result of incoming 4.7 release many boards

Re: [coreboot] EARLY_CBMEM_INIT for Geode LX platforms

Hi Piotr I never worked with Geode LX codebase, my impression is that EARLY_CBMEM_INIT may not be worth the trouble. Visit comments in cpu/amd/geode_lx/msrinit.c: "set up about 500Mb of memory", "doesn't really matter", "WARNING", "probably incorrectly set here". That's enough to tell me you may

Re: [coreboot] BDX-DE PCI init fail

Hi David, When I saw following message, I got different result when using different payload for coreboot: == Returned from FspNotify(EnumInitPhaseReadyToBoot) Jumping to boot code at 000ff06e(7eff6000) CPU0: stack: 00129000

Re: [coreboot] How to properly conform with GPLv2 for Coreboot and SeaBIOS on an embedded system

Hi Ian. > Ian Lewis wrote: > I do have one question: You clearly have no issue for your compliance. But, > do you tell your OEM customers that they need to provide the GPL license to > their customers as part of their product packaging, We do have a sticker on each component which tells that

Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

Dear Naresh, Thanks a lot for your advice. I'm finding correct blobs for KBL U. I'll update once I get result. 2018-01-07 22:05 GMT+07:00 Naresh G. Solanki : > Hi Toan Le, > > For Sasby Island, which is based on KBL U, you'll need corresponding > blobs(me