Re: [coreboot] [RFH] Status of the Lenovo X201

On 28.04.2018 17:34, Kyösti Mälkki wrote: > On Sat, Apr 28, 2018 at 3:41 PM, Nicola Corna wrote: >> April 27, 2018 12:29 PM, "Nicola Corna" wrote: >> With config PARALLEL_CPU_INIT=y so SMP / SMM init in initialize_cpus() will never call

Re: [coreboot] [RFH] Status of the Lenovo X201

On Sat, Apr 28, 2018 at 3:41 PM, Nicola Corna wrote: > April 27, 2018 12:29 PM, "Nicola Corna" wrote: > >>> With config PARALLEL_CPU_INIT=y so SMP / SMM init in initialize_cpus() >>> will never call wait_other_cpus() at all. That actually regressed in >>> my

Re: [coreboot] lenovo x220, tool to extract binary blobs from BIOS update

On 26.04.2018 11:44, diffusae via coreboot wrote: Do you think, that integrate the microcode updates into the coreboot image should be enough? To be safe in case of CVE-2017-5715? No, AFAIK, these updates do nothing on its own. They only add control capabilities that your OS has to use (or be

Re: [coreboot] Why do we have FSP-S

Nico (Huber), > So it's time for an FSP3.0 that was designed with the community, I'd say. You talk (in this email, at least) too much. :-)) I wish you a Good Luck. You'll need it (all the luck in this and others' Worlds). And much more than that! Even Captain Jean-Luc Picard (Star Trek Next

Re: [coreboot] [URGENT] Full List of AMD-based boards that are going to be removed from coreboot unless people cough up a board status update

This is a *personal* opinion, not supported by anyone else I suppose, but: I don't think it's unreasonable to ask that people send in board status 2 times a year. That's it. It makes it easier for potential users, and for people maintaining the tree. Sound ok? ron -- coreboot mailing list:

Re: [coreboot] [URGENT] Full List of AMD-based boards that are going to be removed from coreboot unless people cough up a board status update

Hi Piotr, On 28.04.2018 15:16, Piotr Król wrote: > Second thing that IMO is problematic in board status is assumption > that system have to boot with vanilla coreboot. This is problematic > when you have to use customized version of SeaBIOS or any other > payload used for booting system. The

[coreboot] No boards are removed from coreboot (was Re: [URGENT] ... BS ...)

Hello, to say it one more time: It was never intended to remove boards from coreboot. All that was discussed is to stop pretending that things work (that don't) and instead keep them on branches where it's easier to keep them working (if somebody has interest). If that will happen again, it will

Re: [coreboot] x220: cannot modify nvramcui options with newest coreboot (git a96e31b)

Hello,What about rewrite CMOS checksum from OS with zero value for resetting CMOS parameters on boot process?./coreboot/util/nvramtool -c [VALUE] 27.04.2018, 23:20, "Mat" :I've gathered more details about the problem. coreboot version that works is 9d0aa99 (Nov 24, 2017). 

Re: [coreboot] [URGENT] Full List of AMD-based boards that are going to be removed from coreboot unless people cough up a board status update

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 04/28/2018 02:37 PM, Mike Banon wrote: Hi Mike, > > PC Engines alix1c - AMD LX - 2017-09-17 PC Engines alix2d - AMD LX > - 2017-09-17 PC Engines apu1 - AMD Family 14h (AGESA) - 2017-09-05 > PC Engines apu2 // apu3 // apu4 // apu5 - AMD

[coreboot] Why do we have FSP-S

Hello coreboot folks, hello Intel and Google coreboot developers, back on Tuesday, some of us discovered a commit on gerrit [1] that implements (another) foreign interface inside coreboot. Discussing it didn't go well and I kind of bursted. I feel sorry about that now (especially because I got

[coreboot] [URGENT] Full List of AMD-based boards that are going to be removed from coreboot unless people cough up a board status update

There are a lot of nice AMD-based coreboot-supported boards which have an outdated board_status and are at risk of removal. The majority of these boards (with the exception of PC engines apu2//3//4//5) - do not require a closed source AMD PSP binary to run, and ( also compared to many Intel boards