[coreboot] Re: Directly boot the image of Linux for RISC-V

Done! reference: https://github.com/hardenedlinux/coreboot-HiFiveUnleashed/tree/opensbi-test -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024 -- Original -- From: "Philipp Hug"; Date: Thu, Apr

[coreboot] Directly boot the image of Linux for RISC-V

is used as the coreboot payload. Code reference: https://github.com/hardenedlinux/coreboot-HiFiveUnleashed/tree/r1 Whether to consider adding opensbi to 3rdparty? Do you have any suggestions? XiangWang -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020

[coreboot] Re: Please help me adapt coreboot to HiFive-Unleashed

Thank you very much, I have been changing the starting address of BBL through objcopy, I did not expect to modify the link script. By using the code provided by sifive (https://github.com/sifive/freedom-u-sdk), the Linux startup is successful. Thanks again !!! -- 王翔 安全研

[coreboot] Re: Please help me adapt coreboot to HiFive-Unleashed

patible = "sifive,maskrom0"; reg = <0x 0x0001 0x 0x8000>; reg-names = "mem"; } rom@a00 { compatible = "ucbbar,cacheable-zero0"; reg = <0x 0x0a00 0x 0x0200>; reg-names =

[coreboot] Re: Please help me adapt coreboot to HiFive-Unleashed

(a4) # 80212000 8020039e:f4bff0ef jalra,802002e8 > Does bbl print its logo (the RV banner)? Yes, bbl print its logo. -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024 -- Original -

[coreboot] Please help me adapt coreboot to HiFive-Unleashed

. -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] The problem of coreboot porting to fu540

This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code. So there is no status information for hart0. -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024 This is the code

[coreboot] The problem of coreboot porting to fu540

10 55 10 80280078: 17 56 db 00 13 06 86 f8 ``` -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] riscv: how to running coreboot on HiFive Unleashed?

yUSB1, 12:14:37 > > Press CTRL-A Z for help on special keys > > > > coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock > starting... > Boot mode: 15 > Couldn't load romstage. Thank you for your help. 在2018年11月27 10时56分, "王翔"写道: I am sure my

Re: [coreboot] riscv: how to running coreboot on HiFive Unleashed?

I am sure my uart configuration is 115200 8N1 on /dev/ttyUSB1. I have a power cycle after the burn is complete. 在2018年11月26 18时03分, "Jonathan Neuschäfer"写道: Hi! On Mon, Nov 26, 2018 at 02:54:46PM +0800, 王翔 wrote: > I try to running coreboot on HiFive Unleashed, but nothing c

[coreboot] riscv: how to running coreboot on HiFive Unleashed?

I try to running coreboot on HiFive Unleashed, but nothing come from uart. I tested by the following steps: 1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card. 2. Change MSEL to 11 and boot linux 3. Copy coreboot.rom via scp 4. Write coreboot.rom to /dev/mtd0 by flashcp. 5. Change

[coreboot] riscv: how to running coreboot on HiFive Unleashed?

MSEL to 15 and boot coreboot. No response on uart. Do you have any suggestions? -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Loading Linux payloads on RISC-V

; to mean "somewhere useful"? Did I miss something? On Tue, Sep 25, 2018 at 10:32 PM 王翔 wrote: This elf file is position-independent and can be loaded to any location. We can add a simple script to handle it. 1. Convert vmlinux to binary by objcopy, the binary file name is flat_fi

Re: [coreboot] Loading Linux payloads on RISC-V

This elf file is position-independent and can be loaded to any location. We can add a simple script to handle it. 1. Convert vmlinux to binary by objcopy, the binary file name is flat_file 2. Write a simple assembly file (tmp.S), convert binary to object, the file name is obj_file ``` .section

[coreboot] Doubts about link scripts

I try to read link scripts of coreboot. In addition to the x86 platform, code segments and data segments are contiguous during the bootblock/romstage phase. However, only CAR/SRAM can be used as memory in the bootblock/romstage stage, this should be separate from the flash where the program is

[coreboot] Whether coreboot has restrictions on the bootblock program, cannot use static variables with initial values.

I am try to read the code that cache-as-ram of bootblock stage. And found that just cleared the memory and did not initialize the data segment code. So, I want to ask : "Whether coreboot has restrictions on the bootblock program, cannot use static variables with initial values." Looking

Re: [coreboot] Fw:Re: I want to submit some code, but there aresomeproblems.

>``` >if (running_on_hart(active)) { ... } >``` >Yes, these codes are clearer. > >/* > * If your code needs to temporarily block multiple-threads, do this: > * SMP_PAUSE(active)// `active` is hartid of working thread > * ... single-threaded work ... > * SMP_RESUME() > * ...

Re: [coreboot] Fw:Re: I want to submit some code, but there aresomeproblems.

> Oh! SMP_PAUSE actually jumps here! I would *not* expect that, when I > read code like this: > > SMP_PAUSE(active); > foo(); > bar(42); > SMP_RESUME(); > > Something like the following would be a lot clearer for me: > > if (mhartid() == active) {

[coreboot] Fw:Re: I want to submit some code, but there are someproblems.

>On Tue, Jul 03, 2018 at 04:23:07PM +0800, 王翔 wrote: >> I want submit some code to support temporarily block multiple-threads. > >But this code can't pass check by `checkpatch`. >What is the error that checkpatch prints out? >If you can't see it, try running > util/l

[coreboot] I want submit some code, but there are some problem

I want submit some code to support temporarily block multiple-threads. But this code can't pass check by `checkpatch`. This code look like this: ``` #define barrier() {asm volatile ("fence" ::: "memory"); } /* * If your code needs to temporarily block multiple-threads, do this: *

[coreboot] I want to submit some code, but there are some problems.

I want submit some code to support temporarily block multiple-threads. But this code can't pass check by `checkpatch`. This code look like this: ``` #define barrier() {asm volatile ("fence" ::: "memory"); } /* * If your code needs to temporarily block multiple-threads, do this: *

Re: [coreboot] Why coreboot for riscv does not support multi-core?

> In short: Because it was easier to delay the problem until later. > >On Thu, May 17, 2018 at 03:55:37PM +0800, 王翔 wrote: >> The current code does not set the stack pointer for hart alone. >> The Linux kernel runs in s-mode and cannot set the stack pointer for m-mode. >&

[coreboot] Why coreboot for riscv does not support multi-core?

The current code does not set the stack pointer for hart alone. The Linux kernel runs in s-mode and cannot set the stack pointer for m-mode. If m-mode does not have a separate stack for hart, then m-mode cannot save any state about the current hart. Is it necessary to initialize the stack

[coreboot] Problem about GPIO

I try to porting coreboot to msi's Motherboard(H110 chipset). I read GPIO config from PCR config space under linux. But the value I got was very strange. eg: //DW0 and DW1 cannot be 0x according to the data sheet PIN:GPP_C6 DW1,DW0:, FUNC:(null) PULL:NATIVE

Re: [coreboot] Problem with super io NCT6793D

Thank you very much. 王翔 -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024 -- Original -- From: "Nico Huber"; Date: 2018年4月9日(星期一) 晚上11:56 To: "王翔"; "coreboot"; Subject: Re: [c

[coreboot] Problem with super io NCT6793D

I want to porting coreboot to MSI's motherboard. However, the super io of this motherboard is the NCT6793D. Which chip is like NCT6793D? Or give me datasheet of the NCT6793D. Thank you very much. -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024

[coreboot] Doubt about SPD init in Skylake

2DramCh1 FSPM_UPD->FspmConfig->RcompResistor FSPM_UPD->FspmConfig->RcompTarget If you can help me extremely grateful ! ! ! -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] doubts on FSP

AP' (read-only, size 256) 'COREBOOT' (CBFS, size 2096896) It is at least possible to perform the read action on every section listed above. ``` ------ 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https

[coreboot] x86 : Puzzles about init IDT

ode *) THEN GDTR(Limit) ← SRC[0:15]; GDTR(Base) ← SRC[16:79]; FI; FI; FI; -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org ht

[coreboot] x86 : Puzzles about reset code

jmp _start16bit .previous - What is the meaning of hand coding? In 16-bit mode, the last two bytes are ignored. -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] riscv: How to implement configstring

or other SOC? If this is done through coreboot, maybe a global variable is more appropriate. This avoids modifying the link script. -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org

Re: [coreboot] riscv: How to debug (王翔)

On Friday,June 9, 2017 at 12:34 PM,王翔 wrote: >On Friday,June 9, 2017 9:17 AM, Jonathan Neuschäfer wrote: >>On Thu, Jun 08, 2017 at 05:32:31PM +0800, 王翔 wrote: >>> I try to debug coreboot with **spike**. >>> I has apply the **8250 usart patch** to **spike**. >>I

Re: [coreboot] riscv: How to debug (王翔)

On Friday,June 9, 2017 9:17 AM, Jonathan Neuschäfer wrote: >On Thu, Jun 08, 2017 at 05:32:31PM +0800, 王翔 wrote: >> I try to debug coreboot with **spike**. >> I has apply the **8250 usart patch** to **spike**. >I haven't updated the patches at [1] in a while. Please check i

[coreboot] riscv: How to debug

`https://review.coreboot.org/coreboot.git` -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] BUG : riscv register address is incorrect

320 write_csr(/*scounteren*/0x321, 7);//this address shoud fix to 0x106 ``` I have already submitted a patch. https://review.coreboot.org/#/c/20043/ -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot

[coreboot] Some qustion about riscv implement

. This may destroy the stack of M privilege level. -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot