Re: [coreboot] [SMSC SCH3114] Super I/O issues

Hi Kkonstantin, just by any chance, do you tried to use baytrail and _not_ fsp_baytrail? best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgp3x2tSOzAOf.pgp Description: OpenPGP digital

Re: [coreboot] [SMSC SCH3114] Super I/O issues

the SerIRQ line of the LPC. Best Regards, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgp_fB6iyYM4b.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https

[coreboot] how users can control additional features?

able based on nvram, so we don't need SMM) Any other idea? Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgp044W2B7E3t.pgp Description: OpenPGP digital signature -- coreboot mailing list

[coreboot] Berlin Usergroup Meeting 30. August Thursday @AfRA

want to flash your laptop, send me a notice in advance. Certain things might need to prepared for your device. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpWlqyqL9NkA.pgp Description: OpenPGP

Re: [coreboot] Intel GMA: Backlight brightness driver

Hi Patrick, thanks for your work. Are there any documentation or description what Mailbox 3 support is? Where it come from? Best, lynxis pgpns9PEdQQOA.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Reproducible builds

Hi Tom, only the coreboot region itself should be reproducible. The BIOS flash contains multiple regions (or call them "partitions"). Only the bios region, which contains coreboot and the payloads is reproducible. And so far I know, only SeaBIOS as payload is reproducible. GRUB might be

Re: [coreboot] New Subscriber

> > 3) About the EC > > Is it possible to create a full EC, which I can flash on the > > mainboard chip with the raspberry pi?, or does an open source EC > > already exist for the T420 (I just found one for T400 on > > libreboot). Is the EC store on another chip? > It is stored on another chip,

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Hi Stefan, we have two versions in the tree a) fsp baytrail b) non-fsp baytrail but with mrc.bin as meminit Do you tried to use coreboot (w/o FSP) + u-boot instead? Or is this out of scope? Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221

Re: [coreboot] Where is the serial number stored on the thinkpad ivy/sandy bridge laptops

4 based). src/drivers/i2c/at24rf08c/lenovo_serials.c best, lynxis ps: The at24 also contains your lenovo bios password. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpGxBMTsGzA5.pgp Descrip

Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

Hi Martin, I would like to take a look on your brick. Do you come to the meeting? Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpnw3bRwBsfl.pgp Description: OpenPGP digital

Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

> No. Using a pomona 5250 clip to program a wson-8 chip on board is > possible, according to > https://www.coreboot.org/Board:lenovo/t430s#Preparation . > > I have used this method to program my t430s. I never tried it. Thanks for the tip! pgpfgMJvE6iPn.pgp Description: OpenPGP digital

Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

On Mon, 18 Sep 2017 02:17:56 + Persmule wrote: > Why solder is needed? X230 is in-system > programmable with even a ch341a. Some boards come with a WSON8 spi flash. Or is there another way to do in-system-programmable without an SPI clip? pgptkJnKAnoej.pgp

Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

recommend you to update the EC to the newest firmware. The EC firmware is updated together with the bios, so updating the vendor bios/uefi is enough. We can also desolder your spi chip, programm it and put it back. But that's also a way I wouldn't recommend doing to often. Best, lynxis -- Alexander

Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin

lin https://afra-berlin.de/ best, lynxis Ps. If you want to flash your laptop, send me a notice in advance. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgplCDf4OcrNP.pgp Description: Open

Re: [coreboot] Lenovo X1 carbon 3460 Screen stays black

/OzAMekv0TpRGsFj Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpdaVsxbTzGN.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org

[coreboot] Berlin Usergroup Meeting 10. August Thursday (different location)

/ best, lynxis Ps. If you want to flash your laptop, send me a notice in advance. Certain things might need to prepared for your device. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpPqGnu78IM7.pgp

Re: [coreboot] question on SMM

On Fri, 30 Jun 2017 04:25:06 + ron minnich wrote: > there's something I am certain I don't understand about SMM on intel > chipsets. > > The question is pretty simple. Consider a system with a recent intel > chipset and flash. Is there some special secret sauce that

Re: [coreboot] GPG public key for corboot release signatures

according to the website)? More signatures are better ;). Choose your own trust anchor. I've signed it after it was released. Best, lynxis Alexander Couzens <lyn...@fe80.eu> Key fingerprint = 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 Martin Roth (coreboot developer) <m

Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

tp://www.thinkwiki.org/wiki/Problem_with_unauthorized_MiniPCI_network_card > this method does not work on X201. it doesn't work with vendor bios, but you're using coreboot, so it's working. I've used 2 wifi cards in my x201 for years ;). best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +49151232

Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

On Thu, 13 Apr 2017 19:53:17 +0200 Marek Behun wrote: > Alexander, > on the X230 I am putting the card into the slot for the WiFi card. I > took out another 802.11ac WiFi card and put in this one (COMPLEX > WLE900VX-7A). So if I remove port 47 and it will work on X201, it

Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

slock, but no idea if this is a problem ;). The other solution would be, try to put the (x201) CL_DATA_WLAN/CL_DATA1 (me link) in tri state on the chipset side, but no idea if this is even possible on the chipset. Best, lynxis ps. x230 doesnt have a pcie capable wwan port -- Alexander Couzens mail

Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

magic init procedures. Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpBV4kwOC13i.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] ThinkPad X201/X230 and COMPEX WLE900VX-7A wifi module

en on pcie level, not sure if the power is cut as well. Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpjht8sl2rmU.pgp Description: OpenPGP digital signature -- coreboot ma

[coreboot] 33c3 congress organisation

hi, the chaos communication congress is knocking at the door. I started a pad to track the hardware which is there for hacking. https://pads.ccc.de/coreboot-33c3 best, lynxis ps. there is also a wiki link https://events.ccc.de/congress/2016/wiki/Assembly:Coreboot -- Alexander Couzens mail

Re: [coreboot] [RFC] Explicitly use C11 (was: Setting C99 by default)

I like the idea of using C11. best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpeL_QoOUuik.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Powersavings: 8W of difference between bios and coreboot

to the H8S and not to the Thinker. There is a way to community to the Thinker using different I/O address. - |Chipset| - | | LPC | --- | H8S | --- | | SPI | - |Thinker| - best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn

Re: [coreboot] hackathon in Berlin next weekend 12-14.

On Tue, 09 Aug 2016 11:15:34 +0200 Paul Menzel <paulepan...@users.sourceforge.net> wrote: > Dear Alexander, > > > Thank you for announcing the event on the list. > > > Am Montag, den 08.08.2016, 18:00 +0200 schrieb Alexander Couzens: > > some people are vis

[coreboot] hackathon in Berlin next weekend 12-14.

hi, some people are visiting Berlin for a hackathon next weekend (12-14) The hackathon will taken place at the Finowstr. 2a. It's between the subway station U Samariter, U Frankfurter Str. Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg

Re: [coreboot] How can extract descriptor.bin from bios image?

Hi, use ifdtool -x best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] account for lava hardware testing

On Thu, 9 Jun 2016 20:32:59 +0200 Alexander Couzens <lyn...@fe80.eu> wrote: > hi, > > I would like to integrate gerrit into my jenkins to build coreboot and > do hardware tests with lava. > The jenkins can built a coreboot image and deploy + test the image via > lava on

[coreboot] account for lava hardware testing

used by jenkins jobs: https://code.fe80.eu/lynxis/coreboot-configs best, lynxis ps. it's github auth if somebody want access, just ask. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604

Re: [coreboot] ThinkPad x220 - Status

IOS. The last time I tried it, I had a lot of problems. [3] Thanks for your feedback. Feel free to create tickets or updating the x220 wiki page. Best, lynxis [3] https://ticket.coreboot.org/issues/37 -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg:

Re: [coreboot] openbios in config?

ng it. best, lynxis [1] https://review.coreboot.org -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpOmfUFk3jIL.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@

[coreboot] sign fsfe radio lock down statement

hi, https://fsfe.org/activities/radiodirective/statement IMHO: this lockdown is also one thing against coreboot, because the hardware has to be locked downed. Can we sign it? Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

losed devices? This would ensure, you're not measurring a brightness difference. best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpVK1IakYQG5.pgp Description: OpenPGP digital signature

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

Hey, I guess the vendor bios activate pci clock power save and similiar options. Some are supported by coreboot, but not activated by default. I can only guess, but the native vga init might also miss some power management features. best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu

Re: [coreboot] Issue Tracker down?

online again. best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpmscepbw7ZV.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot

Re: [coreboot] coreboot 4.4 release coming soon

Lenovo: - t400 - tested by CaptainCoward - boot - x201 - broken - doesn't boot - x220 - works @Martin: Can you create a rc1 tag for this? Everybody would against test the same revision. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78

Re: [coreboot] On Intel Boot Guard

best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpbt2kdKkWCI.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Cleaning up old commits in gerrit

nice you're doing this. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpWNnaQ9mQyP.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot

Re: [coreboot] [GSoC 2016] ROM-O-Matic project

ase of the spi. Most x220 have a spi in a SOIC8, but some have a WSON or mlp8 case. I had problems with my x220 because I desolered the wson chip and soldered a SOIC8 which wasn't quite supported by coreboot. I say the "normal" coreboot user wouldn't do that ;). They only use a clip. Best,

[coreboot] tpm api merge

is for now? It would give zaolin more time to fix the problems and give the reviewer also more time to look over?! Best, lynxis https://review.coreboot.org/#/c/10542/ -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6

Re: [coreboot] [GSoC 2016] ROM-O-Matic project

o support coreboot. zaolin is doing installation partys at his hackerspace, too. And may others do the same. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpJWmFx26_Hk.pgp Description: OpenPGP

Re: [coreboot] Coreboot X230 step-by-step

sible. the main problem is the lenovo bios update. It's still unknown how it's updating the rom. But the lenovo protects the bios region from writing. AFAIK there is a *scratch* region writeable possible for bios updates. best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...

Re: [coreboot] ThinkPoint under coreboot

what's thinkpoint? -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] berlin coreboot user group meeting 17.02.2016 18:00

hey, the next coreboot user group meeting is on 17.02. at 1800 as usual at club discordia / cccb. everybody is welcome. I'll take some flasher with me, but it's still a good idea to send me an email so everything is prepared for your coreboot installation ;) best, lynxis -- Alexander Couzens

[coreboot] baytrail + fsp_baytrail

hi, baytrail and fsp_baytrail shares a lot of code. Any ideas how we can merge these? best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpC5sBA7aEX0.pgp Description: OpenPGP digital

Re: [coreboot] [ANNOUNCE] SeaBIOS 1.9.0

https://review.coreboot.org/#/c/12566/ -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] ThinkPad X120e/X140e

version. x121e is the name for two baords, one based on amd and one on intel. just ask in the irc for mue or me. best, lynxis ps. nice nickname ;) -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604

Re: [coreboot] setting up a bug tracker

Hi, I've setted up a bug tracker. https://ticket.coreboot.org/ login/registration via openid, google. New users need a confirmation by zaolin or me. If there is anything missing, I'm happy to receive any feedback. Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu

Re: [coreboot] Understanding BIOS I/O Adresses

booting, you can read from the card it's last byte sent to that ioport 0x80. No idea what for the others io codes are. best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpSS46Mmfizh.pgp

Re: [coreboot] setting up a bug tracker

uff. Should we try let's encrypt? Best lynxis On Thu, 5 Nov 2015 09:15:41 -0800 "Alex G." <mr.nuke...@gmail.com> wrote: > Let's try it. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 86

[coreboot] screwdriver 0.3.0 released

://www.coreboot.org/BBB_screwdriver [2] https://github.com/lynxis/bbb_screwdriver_builder [3] http://repo.fe80.eu/screwdriver/0.3.0/omap/generic/default/openwrt-0.3.0-omap-beagleboneblack-sdcard-vfat-am335x_evm.img -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221

Re: [coreboot] screwdriver 0.3.0 released

s well. Although I believe there > was one earlier in the Wiki. any thoughts how to do that? could you write a small draft on what you exactly mean? best, lynxis ps. a pull-request is also welcome ;) -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390

Re: [coreboot] Rangeley SoC FSP and Mohon Peak board support

Hi David, that's great! Welcome to the coreboot. Best, Alex -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpc4hB9_dFjo.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

Re: [coreboot] Emergency: Talks needed for coreboot conference in Bonn

+0200 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2...@gmx.net> wrote: -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpEYEDT5aE9B.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.corebo

[coreboot] Berlin User Group Meeting 21.Sep

Hi folks, I'm starting a User Group in Berlin. The first meeting will take place on 21. Sep. in the CCCB. For more information about the location take a look on https://berlin.ccc.de/wiki/Club_Discordia Best, lynxis PS: Yes it's Monday evening and it's open for everyone. -- Alexander Couzens

Re: [coreboot] Berlin User Group Meeting 21.Sep

Opps, I forgot to mention the time ;) 21.Sep 20:30 pgpHZ5795WI5M.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] mute button on X200

/Kernel/Reference/ACPITricksAndTips you want to know which _QXX function is called. maybe that one is empty in the coreboot aml for h8s.. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpzoxv46bi4D.pgp Description: OpenPGP digital signature

Re: [coreboot] mute button on X200

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Would it help if I include logs here? If so, which logs? ectool will also show some timers, which are counting upwards in the dump. Last time I've looked at the ECDT (x201) it doesn't contain any additional information. There are multiple ways to

Re: [coreboot] mute button on X200

be handled by _Qxx function. cheers, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgp8jqJcFI8bE.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot meeting @chaos communication camp

I'm looking forward to meet you. At the moment we only have a small /tmp table in the BER village, in the big yellow tipi tent. On the table lies some thinkpads ;). But this table isn't yet final. Best, lynxis pgpKwu2PEp0Ex.pgp Description: OpenPGP digital signature -- coreboot mailing list:

[coreboot] coreboot meeting @chaos communication camp

-- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpBQ4n8qc2Nv.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] T400 screen issue / EDID handling

' build reproducible, which isn't it atm. Best lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpULr62CkR9s.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo

[coreboot] rtc migrations / century byte used

the multiusage, because it makes problems atm. best lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgp1G3trEpMNg.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] On Intel Boot Guard

to look into a x240 flash image. If you have such board it would be nice if you can send me a copy of the flash image via private mail. Cheers, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpFImtjh7IHP.pgp Description: OpenPGP digital

[coreboot] force https on review.coreboot.org

is much more worse than stealing wiki cookies. PPS. Please write a +1 if you're supporting this opinion. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgps5UlmahVsD.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot

[coreboot] device_t or struct device *|pci_devfn_t

device_t with pci_devfn_t http://review.coreboot.org/#/c/9250/ Add device_t to device ops acpi generators. http://review.coreboot.org/#/c/9598/ -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpkkZhvqlZu5.pgp Description: OpenPGP digital signature

Re: [coreboot] Automated test system: Nominations wanted

recovery? Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpF1rHpIAbnY.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] H8 EC question

Hi Charles, it would be nice if you could extend the wiki page http://www.coreboot.org/EC:lenovo/x201 I'ven't found anything yet, what's x201 specific. A good source of EC behaviour is the OEM ACPI Tables (dsdt) and the thinkpad acpi lkernel module. Best, lynxis pgp7LXb8sn3EF.pgp

Re: [coreboot] H8 EC question

That would be great! If you need to query the EC by ectool - there's a patch waiting for review at https://review.coreboot.org/#/c/8382/ Best, lynxis pgpS2wLMyPocj.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Coreboot reproducible builds

Hi Emilian, I chatted today with Holger from reproducible.debian.net and couldn't resist doing reproducible builds ;). These patches need additonal work, but they are working when the git tree is clean. You can test coreboot reproducible when building without payload. Or a more advanced way

Re: [coreboot] x201t + windows7

0x0001fc00-0x0001] reserved [0.00] BIOS-e820: [mem 0x0002-0x000237ff] usable -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpQMstxhcbMP.pgp Description: OpenPGP digital signature -- coreboot mailing list

[coreboot] jolla tabletswith or without intel boot guard?

Hi, FYI: I've created a ticket in jolla's ticket system. When I've received an answer I'll paste it here too. Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

Re: [coreboot] GSOC 2015 Preperations

informing prospective GSOC students about coreboot. Please be helpful to new faces in IRC and direct them to me or Patrick if they have questions. Regards, Marc -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpwcf_CxQe4D.pgp Description

[coreboot] x201t + windows7

Hi, I tried today a windows 7 installation usb stick and a cd disc. Both 32bit and 64bit. Both Windows' stopping at disk.sys and the hdd led on. 32bit: sometimes windows boots, most time not. Any ideas, what's wrong? Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn

Re: [coreboot] GSoC 2015

for coreboot? Is something missing? I would like to attend as student this year ;). Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 pgpfptqBwMcKY.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Plans for upcoming Broadwell Thinkpads

to say the least. No more Thinkpads for us... Is it used by Lenovo? I think I can boot a USB-Linux on a new Thinkpad within a friendly Lenovo Store. How can it tested? What registers must be read? Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile

Re: [coreboot] Internal Ethernet controller on Mohon Peak CRB failed to get activated

, lynxis - -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de mobile: +4915123277221 -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQIcBAEBCAAGBQJUqqGTAAoJEMKenaag34YEWukP/j0HO36Y9L/ruP2r1Jfk04Ti RqBIP1tzWVcBEjTTJqF55bO5+Dz5sWsbqTxYfdfWxYE+EOHyxm/eET2vgYNsL4Se

Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.

Hi Andrew, on my x201t I got the same problems. I bisect it to cbmem console: Locate the preram console with a symbol instead of a section. (commit 35382a6e, Change-Id: I3257b981e). @Gabe: Do you tested the commit with SeaBios as payload? @Andrew: You can also use a raspberry pi or a beaglebone

[coreboot] x201(t): function keys stopped working

the FN-keys working again when I'm query the EC from userspace. All remaining events in the queue will be processed now. I assume the bug comes with suspend in rare cases. Where can I put the EC query on wakeup? Best, Alex -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@jabber.ccc.de