Dear coreboot folks,
As some you know we at OSF are working on enabling Xeons in coreboot. We have
recently uploaded Skylake-SP which goes in src/soc/intel/skylake_sp. At the
same time we are working on enabling next generation SP processor. I was
wondering what may be a good way to structure the
On 07/05/2017 10:01 AM, Andrey Korolyov wrote:
The fourth/fifth points has very high likeness for the fact that the
regular kernel debugging would not help at all and I hardly imagine
myself spending few more days to manage firewire memory 'sniffer' to
work, though this method has highest
Hi,
On 05/31/2017 01:54 AM, Urs Ritzmann wrote:
What flash type were you emulating? I require a 1.8 Volt device with >= 128Mbit
size.
W25Q128FW, also 1.8v. What application do you use to drive em100?
Official one from Dediprog or the open linux one? Also, what em100
firmware# you have,
Hi
On 05/30/2017 12:36 AM, Urs Ritzmann wrote:
Is there a way to disable Quad IO Read(0xEB) from the flash descriptor region?
please try clearing bits 3 (Quad I/O Read Enable) and 2 (Quad Output
Read Enable) at 0x108 offset.
Andrey
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coreboot mailing list: coreboot@coreboot.org
Hi,
On 05/29/2017 06:29 AM, Urs Ritzmann wrote:
Are there any known quirks required to use the DediProg EM100-Pro flash
emulator with Apollo Lake?
The only quirk I know is that the emulated part must support SFDP. ROM
boot code is very sensitive to SFDP and will halt if there no response
Hi,
On 05/19/2017 08:17 AM, Peter Stuge wrote:
I think a more workable and sustainable solution is to enable more
people to grant write access. Another project uses an IRC bot for
this task, so that a group of trusted users on the IRC channel(s)
can grant write access immediately. It works
Hi,
On 03/29/2017 07:52 PM, Toan Le manh wrote:
Hi Andrey,
Even I tried flashing with IFWI .bin file released by Intel, the board
still doesn't boot.
ah, I think I misunderstood you. You were saying even stock
Intel-provided image didn't work. If that is the case yes, probably
Hi,
On 03/29/2017 06:48 PM, Toan Le manh wrote:
@Andrey: The flashing is OK, but the board doesn't boot anything. The
POST CODE is always "0".
Even I tried flashing with IFWI .bin file released by Intel, the board
still doesn't boot.
Where can I select "Use IFWI stitching"?
make nconfig,
Hi,
On 03/29/2017 04:29 AM, Toan Le manh wrote:
I got the LeafHill CRB from Intel, tried flashing SPI chip (Winbond
W25Q128FW) using BeeProg2C.
However nothing worked. The Status Code remained "0".
Are you saying the flashing didn't work OR board doesn't boot after?
If latter, did you select
Hi,
On 03/27/2017 01:05 PM, Denis 'GNUtoo' Carikli wrote:
Since until now, the code running on the management engine is:
- Signed by its manufacturer
- Proprietary software, without corresponding source code
It can desirable to run the least ammount possible of such
code, which is what
Hi,
On 03/16/2017 07:44 AM, Rafael Machado wrote:
/"Intel Boot Guard is intended to protect against this scenario. When
your CPU starts up, it reads some code out of flash and executes it.
With Intel Boot Guard, the CPU verifies a signature on that code before
executing it[1]. The hash of the
On 03/05/2017 10:58 AM, Gailu Singh wrote:
Hi Again,
I tried to find out the details for following error
ata1: SATA link down (SStatus 4 SControl 300)
As per status register description
SStatus 4 : Phy in offline mode as a result of the interface being
disabled or running in a BIST
On 02/25/2017 11:52 AM, Gailu Singh wrote:
Thank you once again for your help and support.
Managed to build the coreboot 16MB image with FSP, ifwi and
descriptor.bin and flashed it on the board. When power-on board, I see
Red LED (DS3B1) is ON that seems to be some error. User guide only
On 02/25/2017 11:05 AM, Gailu Singh wrote:
Thanks Andrey,
Manage to extract required blob with SplitFspBin.py.' I have prebuilt
IFWI binary. only missing part is to find/generate correct
descriptor.bin.
just dd if=fitimage.bin bs=4096 count=1 of=descriptor.bin
where fitimage.bin is output
On 02/25/2017 02:48 AM, Gailu Singh wrote:
>>you need a bunch of blobs (of course), most importantly fitimage.bin and fsp.
>>Please usehttps://review.coreboot.org/#/c/18479/3 as starting point.
>>That is for Leafhill. But once you apply that patch, select mainboard
>>intel/leafhill in 'make
Hi,
On 02/24/2017 09:19 PM, Gailu Singh wrote:
Hi Experts,
I have built coreboot image for Apollo Lake and trying to boot Oxbohill
CRB but no console or display at HDMI port.
you need a bunch of blobs (of course), most importantly fitimage.bin and
fsp.
Please use
Hi,
On 02/13/2017 11:16 AM, Nico Huber wrote:
On 13.02.2017 08:19, Andrey Petrov wrote:
For example Apollolake is struggling to finish firmware boot with all
the whistles and bells (vboot, tpm and our friendly, ever-vigilant TXE)
under one second.
Can you provide exhaustive figures, which
Hi,
On 02/13/2017 12:31 PM, ron minnich wrote:
Another idea just popped up: Performing "background" tasks in udelay()
/ mdelay() implementations ;)
that is adurbin's threading model. I really like it.
A lot of times, concurrency will get you just as far as ||ism without
the
Hi,
On 02/13/2017 10:22 AM, Timothy Pearson wrote:
For [2] we have been working on prototype for Apollolake that does
pre-memory MPinit. We've got to a stage where we can run C code on
another core before DRAM is up (please do not try that at home, because
you'd need custom experimental
Hi,
On 02/13/2017 12:21 AM, Zoran Stojsavljevic wrote:
IBVs can work on this proposal, and see how BIOS boot-up time will improve (by
this parallelism)
There is no need to wait for anybody to see real-world benefits.
The original patch where you train eMMC link already saves some 50ms.
Hi,
On 02/13/2017 06:05 AM, Peter Stuge wrote:
Andrey Petrov wrote:
Nowadays we see firmware getting more complicated.
Sorry, but that's nonsense. Indeed MSFT is pushing more and more
complicated requirements into the EFI/UEFI ecosystem, but that's
their problem, not a universal one.
I
Hi there,
tl;dr:
We are considering adding early parallel code execution in coreboot. We
need to discuss how this can be done.
Nowadays we see firmware getting more complicated. At the same time CPUs
do not necessarily catch up. Furthermore, recent increases in
performance can be largely
Hi,
On 01/21/2017 02:30 PM, Paul Menzel via coreboot wrote:
Dear coreboot folks,
Playing around with the trace feature of the Dediprog EM100Pro, I
noticed several flash ROM accesses until the payload is loaded.
Are there ways or strategies to preload the whole flash ROM chip
content into
привет,
On 11/03/2016 01:17 PM, Vasiliy Tolstov wrote:
> I don't know enough about Intel to tell you whether your board is
> using BootGuard or how you would find that out, though. If it does,
> you're probably out of luck. (If it doesn't, it's true that you still
> need blobs... but you can
Hi Rolf,
I think blobs aren't uploaded yet because ApolloLake has not been
officially announced.
You should try contacting Intel to get the blobs. I know Intel does
offer blobs to certain customers who use FSP-based solutions.
Andrey
On 06/21/2016 06:25 AM, Rolf Evers-Fischer wrote:
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