We will need to define the "hidden" entry in host _crs to be match with
E820 "reserved" entry? They may cause some manual work, maybe we can have
some code change to make it automatically?
Tim Wawrzynczak via coreboot 于2022年8月23日周二 04:27写道：
> Hello fellow coreboot folks,
>
> I recently
Issue #392 has been updated by Lance Zhao.
Do we believe we need to have extra protection to check A4GB is not zero as
well?
Need to see the debug print about A4GB and A4GS at this point.
Lance
Pawel Radomychelski 于2022年7月24日周日 17:00写道：
> Issue #392 has been updated by Pa
Issue #392 has been updated by Lance Zhao.
To save time, you can install a windbg yourself and run !anlyze -v to get the
detailed information. Then use !amli dl or other acpi debug provided by windbg
itself.
Bug #392: coreboot 4.16 & 4.17 - Sea
Issue #392 has been updated by Lance Zhao.
Output of minidump shows that's not acpi bios error.
4: kd> !analyze
Issue #392 has been updated by Lance Zhao.
If we can get a windows crash dump will be easier to debug the issue, we can
use windbg to open generated dump file(memory.dmp most of the time). Then the
detail info normally included,
Bug #392: coreboot
https://github.com/intel/FSP
I am not sure you can use tiger lake fsp on rocket lake or not.
Regards,
Lance
rainhe...@savelife-tech.com 于2022年4月21日周四
17:55写道：
> Hello:
> I'm Rainhenry Wang from SAVELIFE Technology of Yunnan Co., LTD
> Company. We are currently developing a computer
Stack idea is from
https://www.intel.com/content/www/us/en/developer/articles/technical/utilizing-the-intel-xeon-processor-scalable-family-iio-performance-monitoring-events.html
.
In linux, sometimes domain is same as "segment", I am not sure current
coreboot on xeon_sp already cover the case of
Yes, private is a state in between but not a result. I may want to have a
"private" commit first before set it to public visible.
Christian Walter 于 2021年11月12日周五 下午6:18写道：
> Yeah - no.
>
> The GPL allows you do keep your modifications private as long as you do
> not release them in any way. So
ow if it is related to the gpio
> setting.
> >
> > On Mon, 8 Nov 2021 15:31:34 +0800
> > Lance Zhao wrote:
> >
> > >
> https://u8209486.ct.sendgrid.net/ls/click?upn=5-2BjrOL6Sde2a9aQLMiEgaNTszOAtW4XhTn6W2SA205kvAu3ZG
https://review.coreboot.org/c/coreboot/+/29398
Have similar implementation on braswell, so as long as sc_init get
executed in ramstage the serial irq mode programming shall be working.
Zhiwen Zheng 于2021年11月6日周六 下午6:29写道：
> I add the following code to sc_init() in southcluster.c to enable
Hi Werner,
Shall we need to include other stage as well? Like verstage and postcar,
since IDT_IN_EVERY_STAGE.
Lance
Samek, Jan 于2021年7月23日周五 下午4:26写道：
> Hi Werner,
>
> Thanks for the patch - I now have a successful GDB connection over UART on
> TGL.
>
> I was not sure whether to include the
Then those console.c and uart.h need to follow to include in every stage?
Samek, Jan 于2021年7月23日周五 上午12:15写道：
> Hello,
>
> I am currently developing on Intel TGLRVP-UP3, but this should be relevant
> for other TGL-based platforms and possibly all other that set
> CONFIG_IDT_IN_EVERY_STAGE=y:
>
I have commit https://review.coreboot.org/c/coreboot/+/28542/ before,
though I can't remember that's the same error behavior.
Lance Zhao 于2021年2月5日周五 下午10:30写道：
> Can't remember the detail but that maybe related to timer, i believe we
> have that build flag set when build payload from co
Can't remember the detail but that maybe related to timer, i believe we
have that build flag set when build payload from coreboot.
于 2021年2月5日周五 下午9:11写道：
> Hi,
>
> I have generated a payload from edk2 2017. When i booting with payload i
> got struck after the below message. The keyboard is
Do you have the failed DSDT table dumped? Even there's recent change around
NVSA, but looks that's different.
Raul Rangel 于2021年1月21日周四 上午4:24写道：
> Over the weekend I had the realization that SMI logging was enabled
> and interfering with WinDbg. Once I flashed a non-serial firmware
> WinDbg
Highly possible you don't need to connect live sessions using windbg, you
can analysis the generated dump file to simply open with windbg.
Raul Rangel 于2021年1月14日周四 上午6:21写道：
> I'm trying to boot the Windows 10 Installer on a picasso based device
> using coreboot + tianocore. I keep getting a
Why not force that in ACPI _CRS directly? And Linux OSPM will reassign the
memory resource base on CRS any way? You can take a reference from any DSDT
or
https://review.coreboot.org/c/coreboot/+/31822/5/src/soc/intel/braswell/acpi/lpc.asl
.
Lance
Rocky Phagura via coreboot 于2021年1月4日周一
What's the does not boot point to? Stuck in POST with some serial log, or
not even CPU is running.
d.verdi via coreboot 于2020年11月24日周二 上午6:49写道：
> Hi to all,
> I had this problem: when I start the computer with 1 cpu (opteron 6282se)
> everything is fine, if I add the second CPU, the computer
@Subrata Banik must have done so on other Intel
project.
In the near future, I think highly possible that CPX FSP will stick with
edk2-stable202005 for quite some time.
Jonathan Zhang (Infra) via coreboot 于2020年6月17日周三
上午3:15写道：
> Hi coreboot colleagues,
>
> Intel EDK2 header files are needed
Drop Win 7 for your case will be more realistic in the meantime.
Marshall Dawson 于2020年1月13日周一 上午9:09写道：
> > Please guys repair coreboot to support my laptop motherboard.
> https://github.com/coreboot/coreboot/pull/18
>
> Ryzen support is still a work in progress. Having coreboot work on your
https://github.com/IntelFsp/FSP that shall have all the current platform
that FSP can supported,
Matt B 于2019年9月29日周日 上午10:52写道：
> Hello,
>
> I'm trying to check the potential compatibility of the s1200kp intel
> server board. [1] It's mini-itx and supports ECC ram, making it attractive
> for
I agree as well, that will be more clear in implementation.
Lance
Felix Held 于2019年8月20日周二 上午3:26写道：
> Hi Patrick!
>
> > for improved runtime ACPI generation I would like to introduce a new
> member in
> > struct device_operations.
> > It would return the ACPI HID for the given device similar
https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/include
I don't believe FSP UPD have everything, they do have P-state I believe.
于2019年7月5日周五 下午1:30写道：
> Hi Lance,
>
> The settings are meant for BroadwellDE not Denverton.
>
> Are these options too supported in BroadwellDE for
That's Denverton? If the selection is not part of fspupd file
https://github.com/IntelFsp/FSP/tree/master/DenvertonNSFspBinPkg/Include,
then probably they only have default setting. We can't enable/disable those
option through FSP didn't mean those feature is not available.
Lance
Ashmita
https://doc.coreboot.org/lessons/lesson1.html got followed?
于2019年6月19日周三 下午10:12写道：
> On 2019-06-14 13:47, Patrick Georgi wrote:
> > Hey Mike,
> >>
> >
> /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c:546:19:
> >>
> >> note: in
It is hard to debug an ACPI problem from code I believe, but I would
recommend to capture the memory dump and using windbg to analyze the dump
file directly. That shall be easy for you as the following step
1.When system can boot up with GPU,Select "Complete Memory Dump" in "Start
and Recovery"
Tianocore master branch build from edk2 will break, but that had been quite
some time. Stable branch is working fine though.
On Mon, Jun 3, 2019, 3:28 AM Matt DeVillier
wrote:
> On Sun, Jun 2, 2019 at 1:27 PM Mike Banon wrote:
>
>>
>> Also, regarding the significant changes: " ### Tianocore
https://lore.kernel.org/patchwork/patch/822662/
It's same as earlier PCH like sunrisepoint
ron minnich 于2019年4月17日周三 下午3:46写道：
> I need some gpio experts.
>
> On an (e.g.) lewisburg, how does one enumerate the GPIOs and make them
> visible in sysfs as one does on ARM? Is the info in ACPI in
I am not sure how many of receiver still working at Intel or still working
in chrome team, but I think that's okay abandon support for Strago.
Nico Huber 于2019年4月13日周六 上午6:59写道：
> Hi all,
>
> I just noticed that there is a seemingly abandoned board that creates
> a lot of maintenance burden for
I have make quiet some mistake on coding style before and had been point
out several times on review :-). I still fell like an automatic formatting
can help myself and new comers.
Ron Minnich via coreboot 于2019年3月27日周三 上午10:03写道：
> On Wed, Mar 27, 2019 at 6:13 AM Patrick Georgi wrote:
> >
> >
The time I am using XDP on bay trail platform it was fine, but i was not
using coreboot then. What about you don't run any system debuger, just
simply hook up xdp to see the issue still there or not? If so, maybe some
xdp config itself.
On Wed, Mar 13, 2019, 7:33 AM Perkins, Graham (GB)
wrote:
She's not working at Intel any more, so I don't think there will be
response there.
On Wed, Feb 27, 2019 at 4:00 PM Frans Hendriks wrote:
> Hi,
>
> Still no response from MAINTAINERS.
>
> Is there a way have to trigger review/merge/reply?
> Or just keep waiting?
>
> Best regards,
> Frans
>
>
Yes you are right, .s is purely assembly file.
On Wed, Feb 13, 2019, 4:20 PM Kyösti Mälkki wrote:
>
>
> I am not sure you have access to some kind of XDP or Jtag, but an general
>> idea is after romcc complied the code may looks different. You may use
>> objdump to double check that, such as
I am not sure you have access to some kind of XDP or Jtag, but an general
idea is after romcc complied the code may looks different. You may use
objdump to double check that, such as compare the disasemble on DUT and
disasemble from objdump.
I have not been able to work on that platform before,
set PcdSmbusSpdWriteDisable to disable?
On Mon, Jan 14, 2019 at 8:28 PM Hilbert Tu(杜睿哲_Pegatron) <
hilbert...@pegatroncorp.com> wrote:
> Hi,
>
> Is there anyone can tell me how to change MCTRL.SPDDIS in Coreboot?
>
>
>
> The Intel Denverton blocks write permission to address A0~AE due to
>
Yes, I believe we should let mainboard to select CAR implementation instead
of force selection in soc Kconfig. I will suggest to remove that line.
On Tue, Nov 6, 2018 at 10:12 AM Nico Huber wrote:
> Hi coreboot fellows,
>
> I have always been confused that we have the option to use FSP's
>
weeks ago I was getting post
> code 0x34 "Invalid FSPM signature"; but I will try again.
> Coreboot engineers have been doing much work on integrating FSP to
> coreboot and may be the reason has been unstable.
>
> Jose.
>
> ‐‐‐ Original Message ‐‐‐
> On Wednesday
Feels like CoffeeLake RVP11 still been actively uploaded with newer
changes. But at least your coreboot code seems to be outdated, all of those
coffeelake-h related ID(CPUID and MCH/PCHID) had been up-streamed recently.
I will suggest you to sync up your code base and try again.
Lance
On Tue,
1) Will CMOS reset typically result in zeroed out CMOS? Should we
assume that it probably does? Is this a common case?
I don't think so, RTC will kepp on counting. We may assume so if only use
extended CMOS like 0x72/0x73.
On Sat, Oct 6, 2018 at 7:28 PM William McCall
wrote:
> Hey all--
>
>
Well said about open and auditable,
On Thu, Oct 4, 2018 at 10:53 AM wrote:
> If there are any mailing lists which are more suitable to this discussion,
> please mention them so we may subscribe to them and discuss this there.
>
>
> > David Hendricks hat am 4. Oktober 2018 um
> 19:00
Okay, then I believe we should leave the decision on CONFIG instead of
force lockdown blindly. As of now, that's still optional I believe.
On Thu, Sep 27, 2018 at 3:49 AM Nico Huber wrote:
> Am 26.09.18 um 22:26 schrieb Lance Zhao:
> > I am reading the "flash security recommendat
I am reading the "flash security recommendation" from PCH BIOS writer
guide now, it did say strongly recommend to take those actions. The EISS
feature to ensure BIOS region can only get modfiyed from SMM.
On Wed, Sep 26, 2018 at 7:01 AM Nico Huber wrote:
> Am 26.09.18 um 10:50 schrieb Patrick
I know UEFI payload have shell, where you can run disk operation or select
alternative boot device.
On Tue, Sep 18, 2018 at 12:51 PM Sebastian wrote:
> Could there be some mechanism to repair broken OS setups?
> Maybe chroot or like android does with factory reset?
>
> I mean, I've been using
Those devices have been fixed from chipset, I don't think any software side
can change that. I will prefer to have a quick scan of PCI spec 2.2 first,
which mentioned that clearly.
On Thu, Aug 30, 2018 at 11:44 PM Hilbert Tu(杜睿哲_Pegatron) <
hilbert...@pegatroncorp.com> wrote:
> Hi,
>
> In my
Without x2apic mode, APIC_ID register will not be moved by OS. Those
address normally had been tagged as reserved and will not be touched. I
believe that x2apic will apply for processors number more than 255, so
majority cases in coreboot didn't touch that area yet.
On Tue, Aug 28, 2018 at 7:50
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