Re: [coreboot] [RFH] Status of the Lenovo X201

April 30, 2018 5:51 AM, "qtux" wrote: > I wrote a patch [0] for the finalize code issue. It fixed master on my X201 too, thank you. Nicola -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFH] Status of the Lenovo X201

April 26, 2018 7:21 PM, "Kyösti Mälkki" wrote: > Well, smashed stack in romstage -error is no longer in the log, > possibly because this boot used MRC cache now. Could be, unfortunately I don't have first boot log, I'll grab it in the next test. > With config PARALLEL_CPU_INIT=y so SMP / SMM in

Re: [coreboot] [RFH] Status of the Lenovo X201

April 18, 2018 3:54 PM, "Kyösti Mälkki" wrote: > Having romstage stack smashed seems irrelevant for the no-boot issue. > That nehalem raminit code, struct raminfo, seems to eat a lot of stack > and an error message for that case was added with commit 2c3fd49. You > could try parent of that commit

Re: [coreboot] [RFH] Status of the Lenovo X201

Hi Paul, I can't make my X201 boot with the most recent commit: the screen turns on and it shows a blinking cursor, but that's all. Attached you can find the debug log: as you can see it has detected a stack smashing and it froze in a random point. I don't have the build config right now, but i

Re: [coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

September 3, 2017 12:24 AM, "Nico Huber" wrote: > TLDR; it would be a lot slower. > > Alas, there is no usual byte-program mode. Most chips do a 256B page > program which uses op code 0x02 too. For the SST25VF032B it's really a > 1B program. If you use that instead of the AAI write, you get lots

Re: [coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

September 2, 2017 5:39 PM, "Nico Huber" wrote: > Hi Nicola, > > On 02.09.2017 15:06, Nicola Corna wrote: > >> Hi, >> >> I have a Sapphire Pure Platinum H61 with coreboot and flashrom fails >> to erase the flash chip (corrupting the image); attach

Re: [coreboot] Removing Intel ME from the X230 coreboot

> The system did not poweroff after 30 min, but I would like to strip > down everything I can out of the intel ME. Your approach is > interesting. What is the minimal size you can presently get? > Hi, we didn't resized the resulting image, we kept it at 1.5 MB. > Using your python script on my 1

Re: [coreboot] More experiments with disabling the ME

Hi Persmule, for the ME in the board status repo I used a ME image extracted from a Chromebook C710 BIOS dump, you can find the same dump somewhere in the web. Once we repair our spare X220 we can resume the work on ME and, hopefully, reduce further the firmware size. Nicola -- coreboot mailing

Re: [coreboot] More experiments with disabling the ME

> Hi Federico,You guys seem to have successfully built a usable > coreboot image for > x220. Could you share its revision and config file? > I have never built > such usable image till now.Besides, is script file > me_cleaner.py downloadable somewhere?Persmule. Hi, you can find all the info about

[coreboot] X220t missing ACPI events

fortunately I have no experience of ACPI tables, but I can easily flash the original BIOS and provide any dump or log if needed. Any help? Thanks Nicola Corna -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] ifdtool newlayout errors

../util/ifdtool/ifdtool --newlayout layout.txt coreboot.rom If I use an unmodified layout as newlayout the result is the same (overlap + segfault). Suggestions? Thanks Nicola Corna -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot