eche...@free.fr wrote:
> No you didn't answer my question Peter, sorry!..
Sorry - I misunderstood.
> I simply don't understand (and this is why I pollute the coreboot
> ML with this blah-blah..) why ALL (I insist on capital letters
> _ALL_) the systems (consumer/office even .. industrial..) hav
eche...@free.fr wrote:
> (can we anymore speak about "owner"?..)
We can and we must, if we want to own anything at all.
Don't get tricked into merely consuming services and products;
take ownership and shape your reality.
eche...@free.fr wrote:
> But what has Netflix (or Sony, or the entertainm
Hi Ian,
Thank you for reaching out to the community with your very valid concerns!
You are asking exactly the right questions.
In the end, the community can't provide you with legal advice, but
what we can do is help with pointers to successful uses of GPL code,
and we can of course discuss pers
Ivan Ivanov wrote:
> Could it be the requirement of US Government - for all the consumer
> CPU to have backdoors ?
I guess that the private sector is a much stronger force...
Nico Huber wrote:
> watch Netflix in high resolution
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://
Zoran Stojsavljevic wrote:
> > please stop sending HTML emails. Your mails are often very hard to view.
>
> Better?
Yes! Thank you very much for fixing that setting. Like Nico I've also
struggled with parsing some of your replies. I think the new settings
help a lot!
Happy holidays
//Peter
--
Jay Goldfrapp wrote:
> Chipset Mobile Intel PM965
No. If you can do chipset development there exists a started 965
work-in-progress, which hasn't progressed in a couple of years.
> It has Intel AMT which I would like disabled. I heard that with older AMT
> implementations like this the flash can
Keith Hui wrote:
> I know I need to find a SOIC8 test clip and a SPI programmer (I think
> I'll try an Arduino solution first, with a Mega 2560 lying around)
Don't do that without a level shifter. The SPI flash is 3v3 only.
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://mail.c
Hey there,
Wolfgang Denk wrote:
> Multiple implementations of the same feature / multiple solutions
> for the same problem have never been a bad thing per se.
Not per se, but they have indeed been a bad thing with coreboot in
the past.
The coreboot project has always sought cooperation with hard
Hi Stefan,
Stefan Roese wrote:
> I'm facing a PCIe init related problem most likely caused in the
> Intel FSP in our BayTrail U-Boot port (not coreboot!). I hope you
> don't mind me posting this question on this coreboot list, since
> here many more people are present with Intel FSP knowledge.
I
Thierry Laurion wrote:
> ENABLE_IDE_COMBINED_MODE available for sp800 but not for sp700, for ewhich
> sp5100 is derived from:
..
> Suggested Workaround
> Disable combined mode by setting a platform BIOS callback option to CIMx
> called "SataIdeCombinedMode" to 0.
..
> Is there something i'm missing
dz6g...@tuta.io wrote:
> But please dont use freenode irc or any other IRC server that are
> blocking TOR users.
..
> Net neutrality is important. Please dont move coreboot into the
> situation that you cant register because of broken net neutrality.
This is a good point, thanks for bringing it up
Trammell Hudson wrote:
> On Wed, Oct 18, 2017 at 12:35:11PM +0000, Peter Stuge wrote:
> > These clips are test tools for occasional use, not development tools.
>
> Do you have a recommendation on better clips?
I don't. I was lumping all clips together. I've used the Pom
[799] via coreboot wrote:
> Do you have any recommendations if it makes sense to invest a bit
> more budget and buy a more expensive clip or will the quality be
> the same?
>
> The Pomona 5250 Clip:
> https://www.tme.eu/gb/details/pom-5250/test-clips/pomona/5250/
I have no idea about the clip you
Hey Alexander,
Alexandre Desnoyers wrote:
> I can tell you that this persimmon motherboard is booting on my own
> FT1 custom SoC design with very few changes.
Can we encourage you to post a patch to include your board into the
coreboot repository?
//Peter
--
coreboot mailing list: coreboot@co
Anshuman Aggarwal wrote:
> Out of curiosity, is this a limitation to what is possible in the BIOS
> or that nobody has found the need to do this sort of remote control
> using the BIOS yet?
There are a few things that you would need to consider.
For legacy compatibility you require a VGA BIOS wit
Nico Huber wrote:
> wear leveling
> ring buffer
> sanitation phase
> optimizing every update
> Defragmentation
..
> Might work?
Please don't invent a new format, don't reinvent JFFS2 and/or UBI..
Let's make CBFS work for this, please. Reusing the existing data
structure is incredibly valuable, ev
Nico Huber wrote:
> > We already have a simple coreboot-native key-value store: CBFS
>
> Well, I never looked close, but everybody kept telling me for years that
> CBFS is not designed for updates.
But it is!?
Not in-place updates, because CBFS isn't tied to eraseblock sizes,
but a CBFS entry co
Nico Huber wrote:
> In-flash variable format
>
>
> I like to keep things simple and assume that a key=value approach
> suffices (for this layer). Though, as we have certainly to deal with
> NOR flash chips (and their erase blocks), we can't just store things
> in a table t
Hi Cameron,
Cameron Craig wrote:
> I have managed to create a bootable image using an out of date copy
> of coreboot and U-Boot, provided by Intel under NDA.
coreboot code is always covered by the GPL, regardless of where it came
from. If Intel tries to bind you in a contradictory agreement I don
taii...@gmx.com wrote:
> see "# dmidecode"
>
> Under system information and base board information
>
> I am curious as to how it survives the coreboot flash re-write, maybe
> the EC?
The "IBM ThinkPad Embedded Controller -[ ... ]-" SMBIOS string?
That's the EC firmware build number and the EC
One7two99 via coreboot wrote:
> From a newbie perspective I'd like to get this information from one or two
> locations:
> 1) How to get Coreboot running (general part)
> 2) How to flash the X230
Sure thing - and I think it's great that you are working on more
concise docs!
The 1) is quite a larg
Martin Kepplinger wrote:
> what would you want to do? Analyse the image. If your BIOS fits in 4MB,
> you really only need to flash the last 4MB, and using a hardware
> flasher, you cut it out and flash it to the one 4MB chip. done.
"BIOS fits" means: if the allocated space for BIOS (as opposed to
(Please reply only to the list, rather than Cc:ing me. Your mailer
may have a list-reply plugin to automate that. Thanks a lot!)
One7two99 via coreboot wrote:
> One additional general question regarding the flashing on X230s.
As you document your experience, please investigate what is specific
fo
One7two99 via coreboot wrote:
> add which location should I place my extracted vga blob, so that it
> can be found during the Coreboot Build process
Paths entered during configuration reference the source root directory.
> What other settings are suggested to get proper vga initialization
> to b
Martin Kepplinger wrote:
> It's lying here as a brick.
Where is "here" ? What city?
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot
diffusae via coreboot wrote:
> > which EC do you mean? why would it be irritated?
>
> I mean the EC firmware of the x220, for keyboard, power management and
> battery, etc. Or is it located on a different chip? I see, it's not part
> of the flash chip layout.
Keyboard and power management tends t
diffusae via coreboot wrote:
> "Once you are running coreboot any subsequent flashes can be done
> internally, however you will have to force flashrom"
>
> https://www.coreboot.org/Board:lenovo/x220
>
> Is that really possible, without any risk? Doesn't it irritating the
> embedded controller? Ca
Ian Kelling wrote:
> It seems a bit odd to recommend users to use latest git sources on
> something that can easily cause their system to not boot.
If you want to overwrite your bootflash then you should ensure that
you will be able to recover from a non-working image.
Don't risk flashing a rando
Timothy Pearson wrote:
> > The fabulous thing about RISC-V is what makes ARM successful; there
> > can and will be multiple different silicon vendors, offering products
> > with many different features and tradeoffs.
> >
> > Some can be top performance but proprietary.
> > Some can be transparent/
ron minnich wrote:
> I don't think we can assume that an open, unlicensed instruction set
> guarantees open, unlicensed, blob-free CPUs and platforms.
This is of course absolutely accurate.
But a freely licensed ISA and implementation(s) thereof are *one step*
in the right direction, and a signif
Julius Werner wrote:
> while the program was running it mostly interacted with the BIOS directly.
Not in general - that is/was highly dependent on the program.
BIOS interrupt services offer a hardware abstraction, but they come
at a (high! interrupts are very expensive!) cost.
For anything perfo
Trammell Hudson wrote:
> Is there a current or historical reason for the ordering?
My best guess: They are stored in CBFS in the order that they appear
in RAM at run time. If so, no problem changing the order in CBFS.
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboo
Peter Stuge wrote:
> The MBR is irrelevant in the above scenario, it is never read.
..
> The payload directly reads the filesystem from disk, no boot sector is used.
To clarify, I mean code here. No code is read/loaded/used from MBR.
The partition table is read, but I expect that GRUB2 su
Zoran Stojsavljevic wrote:
> > But a bootloader built as a payload could also be built to use BIOS
> > interfaces. GRUB is one example of this.
>
> Let us assume the following configuration:
> FSP -> Coreboot -> Payload: GRUB2 -> Linux
>
> No legacy interrupts, correct?
Correct.
> So, what is t
Philipp Stanner wrote:
> Once coreboot jumped into SeaBIOS-code the latter is responsible for
> providing the right interface for interrupt services.
Sure, coreboot does not provide interrupt services. I did not mean to
claim that it does. Sorry if there was confusion.
> I guess it doesn't matte
Philipp Stanner wrote:
> As far as I understood the Intel Programmer's Manual the CPUs
> provide a 16-bit compatibility-mode in 64-bit-long-mode...
Every new CPU comes out of reset in 16-bit mode, just like 8086.
> I don't see a reason why it should be impossible to abolish Real Mode,
> Segment
Philipp Stanner wrote:
> > > Why would I want to address memory in RM with 32 Bits? I don't see
> > > any difference to using PM without Paging enabled.
> >
> > In a bootloader (after coreboot) you often want to call BIOS
> > interrupt services which assume real mode, because that was the
> > only
Zoran, Vincenzo,
BIOS and UEFI have higher privilege in the system than the OS kernel,
which has higher privilege than userland processes, which have higher
privilege than the user.
Any component with higher privilege can override, circumvent or
contradict parts of the system and users with lower
Jonathan Neuschäfer wrote:
> > I would like to have a list of all boards ever supported, along
> > with the last coreboot revision where they can be found.
>
> There is such a page in the wiki[2]. It's probably incomplete. It
> doesn't list commits, either.
>
> We could migrate it into git, maybe
taii...@gmx.com wrote:
> Does anyone know what TPM's are compatible?
Sorry, can't help with that.
> I also want to know what coreboot's tpm support is like these days, such
> as how can you perform an erase/reset like one could with a standard OEM
> bios.
Is that in the realm of the BIOS? Sea
I love it when you vent, Ron. :)
ron minnich wrote:
> I don't agree. You don't need links as long as you have google or its
> competitors or successors. But that's just me, no need to continue this,
Let's agree to disagree. Direct links are, well, direct; eliminating
an undesirable extra search s
Arthur Heymans wrote:
> https://gist.github.com/ArthurHeymans/c5ef494ada01af372735f237f6c6adbe
I note these differences from what I wrote up in the wiki:
(that may no longer be there though)
* CONFIG_BUCTS_BOOTBLOCK is now a thing (great! very neat!)
* updated flashrom patches
* use flashrom imag
taii...@gmx.com wrote:
> Things I want to do:
> payload menuconfig for common payload configurations such as disabling
> option roms, loading grub.cfg's from disks, etc.
> List of boards with verified special functionality (iommu, egpu, etc)
That sounds great!
//Peter
--
coreboot mailing list
ingegneriafore...@alice.it wrote:
> atp-get install qemu
>
> to install qemu on my Ubuntu 16.04 PC. Is it right ?
Probably, yes.
> For coreboot i need to use qemu-sh4 ?
No, the coreboot qemu target is for x86.
Use either qemu-system-i386 or qemu-system-x86_64. Maybe only the
first is correct.
Andrey Korolyov wrote:
> > What is the easiest and most stable way to do debug through EHCI USB port
> > instead of COM port? Is there any EHCI dongles on market that supports both
> > Linux and Windows as a host PC?
>
> I`ve never tried working with combination of the RPI and usb-ip to
> pass dwc
Philipp Stanner wrote:
> Why would I want to address memory in RM with 32 Bits? I don't see
> any difference to using PM without Paging enabled.
In a bootloader (after coreboot) you often want to call BIOS
interrupt services which assume real mode, because that was the
only mode, when the interrup
Philipp Stanner wrote:
> the more I want to contribute and learn about low-level-code the less I
> understand, it seems.
The x86 is a true rabbit hole. :)
> 2. When CB switches to PM - who generates and administrates the Page
> Tables and where?
Note that PM != paging. Neither coreboot no
Hello Konstantin,
Konstantin Novikov wrote:
> Yes, now I'm using VGA port. Yes, we'll commit our changes, but after we'll
> end port. S3 isn't working now, and we have some troubles with Super I/O,
> but we already did this work with b75-port.
You don't have to wait until you have finished everyt
Konstantin Novikov wrote:
> gma_setup_panel(dev)
> - this function was critical for us.
>
> gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
> DDI_INIT_DISPLAY_DETECTED);
> Without DDI_A_4_LANES in this row we saw the Linux Ubuntu output
Should this perhaps become a Kconfig option to be
Just came across this. Working HDL for the architecture we all love
to hate. Amazing study material, for learning PC. Complete with GPL
system and VGA BIOS.
https://github.com/marmolejo/zet
Apparently it runs Lemmings, Doom and Windows.
If you ever wondered what all those weird legacy register w
Paul Kocialkowski wrote:
> I am wondering what the best way to solve this would be.
..
> * Having larger fonts for hi-dpi displays
This should be the top priority, because it provides the best user
experience. (Ie. it looks the best.)
> * Scaling the font to reach a particular DPI (e.g. based on
Nico Huber wrote:
> > 0x42D3B3000 - working integrated graphics ROM !!!
> >
> > 0x42D305020 - working discrete graphics ROM (first working copy, the same)
> > 0x42E40DCD0 - working discrete graphics ROM (second working copy, the same)
>
> nice work! If these are physical addresses, dumping from L
Stefan Reinauer wrote:
> (it was just copy-catted around from my original i945 implementation)
> But I don't think that we should remove the knowledge from the code base.
So it is a technology showcase and not required code.
Those two should never be allowed to mix, and Patrick has found one
inst
ron minnich wrote:
> Ah gee Peter, thanks for making me look at a web page with this sentence:
> "Safeguarding the Future of Computing with Intel Embedded Security and
> Management Engine"
>
> My irony-meter immediately went to 11 ... million.
Ha! :)
I can really recommend eyeing through that bo
Rene Shuster wrote:
> Not an expert obviously, but I was under the impression the Digital
> Restriction Management was achieved through Widevine. No?
DRM requires hardware support to be useful. If the Widevine software
component was solely responsible for DRM then another software
component runnin
Patrick Georgi via coreboot wrote:
> * speaking of emails, pt 2: There's now limited support for
> accepting comments to changes in email replies. I'd need to enable
> it to work, but I hereby want to gauge interest in such a feature.
What exactly does it allow to do?
In general, I think this fea
Jonathan Neuschäfer wrote:
> I wonder if we should just import libfdt when we need to parse or
> modify devicetree blobs. A quick check on the libfdt.a on my
> system (x86_64) shows that the set of .o files takes about 15kB, so
> it's not huge.
If the license is compatible I think that's a good i
Константин wrote:
> Port80 is working now.
Great!
> Found bug is in LPC's early initialization code.
Would you please share your fix for the bug?
Or at the very least explain the bug you have found in more detail?
Thanks!
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://mail
Hi Rene,
Rene Shuster wrote:
> Where can I get Coreboot stickers?
You can use the artwork at https://www.coreboot.org/Logo to order
stickers in your favorite quality from a local supplier.
> What are your thoughts working together w/ UnixStickers.com, so that
> Coreboot would receive part of th
Hi Tiberiu,
Tiberiu wrote:
> We also offer an installation service of libreboot (fully free coreboot
> distro). Upon request, we can install libreboot also on other laptops
I'd like to encourage you (all vendors, really) to both emphasize and
engage with coreboot directly.
I know that I would re
First, I agree with the goal of lowering the administrative overhead
for write access to the wiki.
qma ster wrote:
> My proposal is to give the edit rights to all the subscribers of the
> coreboot/flashrom mailing lists
..
> I strongly believe that all the members of coreboot/flashrom
> mailing li
Martin Roth wrote:
> 146 Platforms currently scheduled for removal after 4.7 if no work is done
> to update them
This is a long list. Is the requirement actually on the individual
boards, or is it something that could be fixed in a single location
and then apply more widely?
//Peter
--
coreboo
taii...@gmx.com wrote:
> There should be an easier way for people to test stuff, I myself haven't
> bothered to do it yet as you need an openid, then a gerrit account,
It is unfortunately completely unsustainable to operate a publically
accessible read+write service without authentication and/or
First, thanks to everyone who is working hard to maintain a good tone
on the list. I certainly appreciate that.
While the ME and that it may have issues ;) is not so big news for many
in this community, this is an important news story for IT in general,
as it furthers the goal of platform and firm
Timothy Pearson wrote:
> In general static timeouts are not a good idea.
In general infinite loops are a worse idea.
> can it parse the ME descriptor and not even search for the HECI
> interface if the ME size is less than a certain value?
That's a good idea! But put the timeout in to begin wit
Zoran Stojsavljevic wrote:
> I am not sure what are you really trying to do,
Quantify data retention of unpowered memory.
> and, mostly WHY you are trying to do what you are trying to do?!
To challenge the assumption that data is lost without power.
It is an interesting area of research becaus
Sam Kuper wrote:
> GNUtoo in 2013:
> GNUtoo in 2013:
> phcoder in 2013:
> phcoder in 2014:
> Kl3 in 2015
>
> So, it would seem that during 2013-2015, native graphics init became
> operational within Coreboot for the X201.
TL;DR: That code was always poor, don't expect it to work reliably.
Don't
Berj K Chilingirian wrote:
> I was hoping to get some advice/guidance on how to disable the
> automatic refresh of the DRAM during the ROM stage of coreboot.
Reset the memory controller, or the entire platform.
Or, if you find no software solution, maybe you can use a fast FET or
logic gate on ch
Zoran Stojsavljevic wrote:
> since BSW (including APL-I, former BXT-I), there is ONLY USB 3.0 xHCI root
> hub.
It's too bad that EHCI has been removed.
The xHCI register model is broken in that it requires dedicated
hardware (registers) for each connected USB device, and Intel's xHCI
implementati
Stefan Reinauer wrote:
> > > > I never tried the web interface.
> > >
> > > We did, it failed us.
> >
> > What problems did people have with mumble-web, and where was the
> > websockets server running, relative to the mumble server?
>
> It was actually your mumble server.
I didn't have mumble-w
Thanks for sending out minutes!
Martin Roth wrote:
> * How do we feel about changing the coding style to move constants in
> comparisons to the left side? if (0 == x) instead of (x == 0)
>- The argument for doing this was that this style finds errors in any
> environment
>- Ron is very o
Patrick Georgi via coreboot wrote:
> 2017-03-17 13:17 GMT+01:00 Dumitru Ursu :
> > I never tried the web interface.
>
> We did, it failed us.
I wish someone would have mentioned that sooner.
What problems did people have with mumble-web, and where was the
websockets server running, relative to t
Martin Roth wrote:
> * board status uploads are still only a few boards. How do we improve usage?
Include it together with the default payload.
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
Rafael Send wrote:
> an old Thinkpad X61 with a custom motherboard in it.
Who made the new mainboard? You should ideally get their cooperation
for your project.
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
Iru Cai wrote:
> I have searched and downloaded two SMSC confidential document: a KBC1122
> preliminary datasheet and a KBC1122 BIOS porting guide. Is there any
> problem if I use them to write some code?
Obviously they are copyrighted works, so you can't contribute any
code which you may have cop
taii...@gmx.com wrote:
> The 30 minute thing begs the question of why does intel care so much
> about making sure people have ME functional?
It's part of the platform.
> It makes no sense to me.
I recommend reading the Platform Embedded Security Technology Revealed
book, ISBN 9781430265719.
Zoran Stojsavljevic wrote:
> Did not understand... I must admit! As of my best interpretation
> SeaBIOS has 5 functions which makes BIOS legacy:
>
> get and set variables, get and set real time clock, reset.
>
> Or maybe, something changed.
SeaBIOS implements a whole bunch of legacy BIOS servi
Andrey Petrov wrote:
> We are considering adding early parallel code execution in coreboot.
> We need to discuss how this can be done.
No - first we need to duscuss *if* this should be done.
> Nowadays we see firmware getting more complicated.
Sorry, but that's nonsense. Indeed MSFT is pushing
Paul Menzel via coreboot wrote:
> find out what parts take too long to read for example?
Nothing will "take too long to read" - the emulator always replies
quickly.
> Are there tools available to help work with these traces, and for
> example map certain areas to the corresponding code?
The add
Zoran Stojsavljevic wrote:
> crucial question from me: how Coreboot will work if instead SeaBIOS
> GRUB2 is the payload chosen
Instead of SeaBIOS reading MBR, GRUB2 will read its configuration
file and operate accordingly.
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://www.cor
Haleigh Novak wrote:
> I was wondering if anyone could take a few minutes and explain the
> proccess of how coreboots SeaBIOS payload (or even how coreboot
> itself) transitions into a Linux boot sequence to me?
SeaBIOS does nothing coreboot-specific, but uses the de-facto
standard BIOS method: Ma
Michal Widlok wrote:
> Peter: Is that really the case with old T400?
I don't have experience with T400, but on older models still it was
very much the case that the BIOS image had some information in it,
which was compared with the actual hardware at runtime, and in case
of mismatch the platform d
Michal Widlok wrote:
> Ron - I've lost original bios, my mistake.
I think that will be a problem. Lenovo BIOSes save some machine-specific
information in the flash ROM across updates, and I've so far not seen
a single Lenovo mainboard which does not require this information for
the vendor BIOS to
Timothy Pearson wrote:
> Populating all four slots closest to CPU1 with large ECC registered
> DIMMs is a surefire way to recreate the instability -- note a
> training failure is not common, the main issue is that the marginal
> routing causes severe memory corruption when the BKDG-recommended
> al
Andrey Korolyov wrote:
> > Buy another chip, make a breakout board, remove onboard chip, connect
> > probes to breakout board, connect breakout board to mainboard.
>
> Thanks, but this is a pretty time-consuming method if I need to tap
> four consecutive legs out of one hundred.
Yes for sure! In
Andrey Korolyov wrote:
> tap 0.5mm pitched packages - how it could be done
Buy another chip, make a breakout board, remove onboard chip, connect
probes to breakout board, connect breakout board to mainboard.
> i945, so initial porting has been done with very small effort, but
..
> raminit run af
Paul Menzel via coreboot wrote:
> How can I quit the payload, which probably means restart the system?
>
> Pressing ESC or Ctrl + Alt + Del don’t work.
Remember that coreboot jumps to the payload; the payload is
responsible for restarting. If Tint doesn't support that I think
you have to submit a
Paul Menzel via coreboot wrote:
> Are there ways or strategies to preload the whole flash ROM chip
> content into memory for faster access right after RAM is set up for
> example? What does that depend on? Does that make any sense at all?
That's called BIOS shadowing and was popular at least in th
Car.cuevas via coreboot wrote:
> Well actually, for me what's important is that I can be able to see
> through DP2 from the docker, If I can alter actually the backlight
> sequence, and setup the DP2 as the first one, but I have to say
> sorry because from your explanations I am not sure if it mean
I would also like to establish a classification. Thank you for making
a concrete suggestion.
Julius Werner wrote:
> So as a quick brainstorming, I'd rather suggest a ranking roughly like
> this to fairly reflect the risk the user is exposed to:
>
> A. Everything free.
> B. Non-essential component
Aaron Durbin via coreboot wrote:
> This was discussed around a month ago on #coreboot, iirc.
That's not really good enough, IMHO.
So far, coreboot was always self-contained. It even goes so far as to
build its own toolchain.
Creating mandatory dependencies which may actually not always be
necces
Trammell Hudson wrote:
> When I build coreboot 4.5 from the release sources it is necessary
> to download the coreboot-blobs-4.5.tar.xz file and it looks like there
> might be a dependency now on the 3rdparty/vboot tree as well since
> cbfs.h includes vb2_api.h:
>
> https://github.com/coreboot/cor
Haleigh Novak wrote:
> how exactly to I use the "$ cbmem -c" command, specifically where
> exactly in boot/start up process should I call it-
Not at all. Run cbmem once you have booted Linux.
> I cant call it from the OS,
Why not?
> I haven't been able to find anything on google relating to h
Piotr Król wrote:
> > > 3/ ./flashrom -p dediprog:voltage=1.8V -w solidrun.rom
> >
> > Why 1.8V? Is there a schematic available for this board?
>
> Please take a look at this:
> http://www.solid-run.com/wiki/doku.php?id=products:ibx:software:development:bios
Cool - thanks! The reason is simply t
sebastien basset wrote:
> For flashing board solidpc,
> 1/ plug power supply (without pressing the power button)
> 2/ connect dediprog on j8 connector( with good cable)
> 3/ ./flashrom -p dediprog:voltage=1.8V -w solidrun.rom
Why 1.8V? Is there a schematic available for this board?
//Peter
--
kitestramuort wrote:
> However it works very well in Linux with a small patch to the i915
> module that disables the LVDS lane and forces DP-3 to be detected
> as eDP.
Could you pass me a link to this patch please?
Thanks a lot
//Peter
--
coreboot mailing list: coreboot@coreboot.org
https://w
Philipp Stanner wrote:
> By the way:
>
> Is it true that coreboot consumes more power ( = shorter battery life)
> than vendor bios?
May be. coreboot supports a few hundred mainboards. It would be great
if you help collect some data.
It would be even greater if you find data points where coreboot
Trammell Hudson wrote:
> Do we require any sort of VGA init if the payload has the kernel
> framebuffer and mode support?
As far as I know the answer for more recent kernels is "sortof".
It used to be that i915 in the kernel was completely independent. It
would initialize GPU and turn on the pane
Zoran Stojsavljevic wrote:
> I programmed most of INTEL platforms using dediprog SF100: ATOM:
> from D4xx/D5xx (Pine Creek) series, TNC, BYT-M/I, BSW and CORE
> (IVB, HSW, BDX-DE, BDW-H, SKL-Y/U), whereas for some HSW-U series it was
> necessary to put platform in S5 state by shutting down them to
Michael Carbone wrote:
> I have been attempting to use a raspberry pi for spi flashing and when I
> use the 3.3v pin the raspberry pi doesn't power up as the chip draws too
> much power through the 3.3v pin for the raspberry pi to also run.
It's not the flash chip drawing current, it's the rest of
201 - 300 of 3195 matches
Mail list logo
