Hi,
The p5gc-mx is still supported (src/mainboard/asus/p5gc-mx in a git snapshot).
It seems the mainboard consists of i945GC northbridge and ICH7 southbridge
(82801GX).
Both are supported, in a fact I'm using a board with i945GM+ICH7 which is
almost the same.
However there may be some
Dne 10. 07. 22 v 13:16 Nico Huber napsal(a):
> Hello Petr,
>
> thanks for reporting this. Are you using your host toolchain to build
> coreboot by any chance (CONFIG_ANY_TOOLCHAIN)? or do you use `make
> crossgcc*`?
>
I do use CONFIG_ANY_TOOLCHAIN.
> On 10.07.22 0
Hello,
It seems since version 4.17 and since commit:
75226bb879837e2e4aa710aadb27dbadb4044ed3
Makefile.inc: Generate master header and pointer as C structs
The coreboot miscompiles the ROM image. At the beginning of the image
there should be usually something like:
"cbfs_master_header"
Clearing the memory creates a situation, where an access to NULL pointer is
actually valid. This causes a warning in the log:
clear_memory: Clearing DRAM -5000
Null dereference at eip: 0x7f3ca51d
clear_memory: Clearing DRAM
OK thanks for info
Petr
Dne 25. 04. 22 v 8:30 Arthur Heymans napsal(a):
> Hi
>
> 2M TSEG is hardcoded in nb/intel/i945/early_init.c so it should never have an
> 8M value.
>
> --
> Arthur
>
> On Mon, Apr 25, 2022 at 8:22 AM Petr Cvek <mailto:petrcve...@gmail.co
e goes up to 64MB, not 8M, but it's not documented in the
> official documentation.
>
> Kind regards,
> Arthur
>
> On Sun, Apr 24, 2022 at 11:54 PM Petr Cvek <mailto:petrcve...@gmail.com>> wrote:
>
> Thanks! I would never find the SMRR feature.
>
04. 22 v 18:56 Arthur Heymans napsal(a):
> Hi
>
> You want to align tseg for when smrr is supported by the CPU. I would just
> drop support for 1MB stolen memory.
>
> Arthur
>
> On Sun, 24 Apr 2022, 05:40 Petr Cvek, <mailto:petrcve...@gmail.com>> wrote:
>
&g
Hello again :-D,
I'm working on a code for a simultaneous use of IGD (GMA950) and x16 PCIe slot
GPU. I've made some success, but the code which handles the IGD initialization
is really weird.
The IGD is initialized by DEVEN register (DEVEN_D2F0 and DEVEN_D2F1 bits),
which is first written in
Hi,
Observing ACPI on my new ryzen machine it seems its UEFI can generate the state
of PS/2 mouse and keyboard accordingly to which one of them is connected or
disconnected. I was trying to add something like that to my Core 2 Duo testing
setup, but it seems there is no easy way how to export
Hi,
My board Kontron 986lcd-m (i945) sometimes fails in quick_ram_check_or_die()
with
RAM INIT FAILURE!
The failure occurs in about 33% of reboots. RAM modules are fine (multiple
memtest checks over the years), used RAM modules are rated with a reserve
(DDR2-800 compatible modules
Hello,
On i945 northbridge:
ASSERTION ERROR: file 'src/cpu/x86/smm/tseg_region.c', line 31
can be triggered by some configurations. The assert
ASSERT(IS_ALIGNED(sub_base, sub_size));
tests alignment of SMM base with SMM size. The problem is that IGD stolen
memory can offset
ave given up :))
>
>
glad to help
>
> Could you give me a hint, how this type of Rom could be handled ?
It should be supported by flashrom, so just get the supported SPI adapter.
Fingers crossed for making coreboot work.
Petr
>
> Am 12.01.21 um 20:03 schrieb Petr Cvek:
chipset ?
>
> Sorry for asking maybe not sensible questions, I have yet too few knowledge
> on these
> bios hardware concepts.
>
>
>
> Am 12.01.21 um 17:45 schrieb Petr Cvek:
>> Did you looked under black isolation stripes?
>>
>> There is one soic-8 a
Did you looked under black isolation stripes?
There is one soic-8 at the top of this photo
https://pasteboard.co/JJjRjLU.jpg
next to superio U49. There can be more chips under expansion cards.
BTW you can eliminate chips which doesn't have the standard SPI pinout (for
example you can try
Hi,
Well my system have only 4.10-637 coreboot version, so I don't know if it is
relevant.
My Kontron 986LCD-M (supported by coreboot) does the SMP without a problem.
Kernel 4.20.0-rc2 (I didn't see any problem with current slackware kernel too).
GPU is radeon RX460, kernel parameters
Dne 31. 10. 19 v 18:20 phakt--- via coreboot napsal(a):
> Hello,
>
> on FreeBSD forum there was a discussion about
> "FreeBSD friendly Motherboard compatible with Coreboot"
>
> link:
> https://forums.freebsd.org/threads/freebsd-friendly-motherboard-compatible-with-coreboot.68346/
>
>
> the
Hi,
I have/know only 10 years old boards.
usually it is not mapped to anywhere. Some older superIO chips (ITE) supported
to dump the values to the LPT port. There are cheap POST cards which can be
plugged into ISA, PCI or PCIe slots, but a least in the case of PCIe I don't
think they decodes
Hi,
I'm considering to innovate kontron 986LCD-M wiki page. According to the new
wiki it should be generated from /Documentation subdir of the coreboot source
tree.
Petr
Dne 08. 10. 19 v 9:01 Matt B napsal(a):
> Hello,
>
> Adding to this, it would also be good to have what
the problem is there is no gameport routed on the board, so this
allocation is overkill. Maybe the whole logical device could be disabled. Is
there MIDI and GPIO port 1/5 routed anywhere? I'm not sure if PNP autodetection
could be changed to ignore undefi
_time_from() defined anywhere.
Petr Cvek
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Hi,
sorry for delay it seems I didn't receive your answer.
My card is SAPPHIRE NITRO Radeon RX 460 4G D5 OC. I've read the sapphire cards
usually lacks dual vbios, so using the coreboot is probably the only way.
Petr
> > I was trying to upgrade my Kontron 986LCD-M setup to AMD Radeon RX460
>
flash chip needs to be disconnected
when using these busses and which pins of the chipset are connected to
SPI pins BOOT0 and BOOT1 (I suppose they are LPC/SPI/PCI priority?).
Thanks for any help.
Petr Cvek
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