[coreboot] Re: Monochrome coreboot logo as BMP?

Hi Nico, On Mon, 20 Nov 2023 at 02:45, Nico Huber wrote: > > Hi, > > On 19.11.23 19:39, Simon Glass wrote: > > Could I get your sign-off somehow? You could add it here, or reply on > > the U-Boot ML when I send the patch. > > oh, right. Signing off on my modificati

[coreboot] Re: RFC: Post-build control of serial console

Hi, Here is an updated version 2 of the RFC RFCv2: Post-build control of serial console It is annoying to have to create and maintain two completely different builds of coreboot just to enable or disable the console. It would be much more convenient to have a 'silent' flag in the image, which

[coreboot] Re: RFC: Post-build control of serial console

Hi Keith, On Tue, 12 Sept 2023 at 18:09, Keith Hui wrote: > > Hi Simon, > > > Why not CMOS RAM / VVRAM? > - If we allocate some space in CMOS for console / logging settings, > then it would allow a similar feature. But it involves changing > settings on the device. Each board would need to

[coreboot] Re: RFC: Post-build control of serial console

ry linker script. > Maybe this deserves another discussion as others stumbled on the desire to > pass data between stages too: https://review.coreboot.org/c/coreboot/+/76393 Yes we could plug into that...but I wonder how this works when the data is in CAR? Doesn't that make it hard to make the data ava

[coreboot] RFC: Post-build control of serial console

Hi, RFC: Post-build control of serial console It is annoying to have to create and maintain two completely different builds of coreboot just to enable or disable the console. It would be much more convenient to have a 'silent' flag in the image, which can be updated as needed, without needing to

[coreboot] Re: [PATCH v2 00/20] x86: efi: Fixes and improvements for coreboot

Hi, On Thu, 17 Aug 2023 at 18:27, Simon Glass wrote: > > This little series fixes various bugs and annoyances in coreboot and > coreboot64. > > With this both coreboot and coreboot64 start up and work reasonably well > on Brya (x86 Chromebook) and U-Boot can boot common Linu

[coreboot] [PATCH v2 00/20] x86: efi: Fixes and improvements for coreboot

new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch Simon Glass (20): x86: coreboot: Add IDE and SATA x86: coreboot: Enable standard boot x86: coreboot: Rearrange arch_cpu_init() x86: Set

[coreboot] [PATCH v2 20/20] x86: doc: coreboot: Mention 64-bit Linux distros

Add a little more detail as to why coreboot64 is preferred for booting Linux distros. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch doc/board/coreboot/coreboot.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot

[coreboot] [PATCH v2 16/20] x86: coreboot: Record the position of the SMBIOS tables

Make a note of where coreboot installed the SMBIOS tables so that we can pass this on to EFI. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch arch/x86/lib/coreboot/cb_sysinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib

[coreboot] [PATCH v2 10/20] x86: coreboot: Enable VIDEO_COPY

At least on modern machines the write-back mechanism for the frame buffer is quite slow when scrolling, since it must read the entire frame buffer and write it back. Enable the VIDEO_COPY feature to resolve this problem. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/dts

[coreboot] [PATCH v2 09/20] x86: coreboot: Align options between coreboot and coreboot64

These two builds are similar but have some different options for not good reason. Line them up to be as similar as possible. Signed-off-by: Simon Glass --- Changes in v2: - Update the malloc size too configs/coreboot64_defconfig | 7 +++ configs/coreboot_defconfig | 9 - 2 files

[coreboot] [PATCH v2 08/20] x86: coreboot: Drop USB init on startup

This is very annoying as it is quite slow on many machines. Also, U-Boot has an existing 'preboot' mechanism to enable this feature if desired. Drop this code so that it is possible to choose whether to init USB or not. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/cpu

[coreboot] [PATCH v2 07/20] x86: coreboot: Enable CONFIG_SYS_NS16550_MEM32

The debug UART on modern machines uses a 32-bit wide transfer. Without this, setting debug output causes a hang or no output. It is not obvious (when enabling CONFIG_DEBUG_UART) that this is needed. Enable 32-bit access to avoid this trap. Signed-off-by: Simon Glass --- (no changes since v1

[coreboot] [PATCH v2 06/20] x86: coreboot: Look for DBG2 UART in SPL too

If coreboot does not set up sysinfo for the UART, SPL currently hangs. Use the DBG2 teechnique there as well. This allows coreboot64 to boot from coreboot even if the console info is missing from sysinfo Signed-off-by: Simon Glass --- (no changes since v1) configs/coreboot64_defconfig | 1

[coreboot] [PATCH v2 03/20] x86: coreboot: Rearrange arch_cpu_init()

Init errors in SPL are currently ignored by this function. Change the code to init the CPU, reporting an error if something is wrong. After that, look for the coreboot table. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/cpu/coreboot/coreboot.c | 12 +--- 1 file

[coreboot] [PATCH v2 02/20] x86: coreboot: Enable standard boot

Enable bootstd options and provide instructions on how to boot a linux distro using coreboot. Signed-off-by: Simon Glass --- (no changes since v1) configs/coreboot64_defconfig| 14 ++ configs/coreboot_defconfig | 1 + doc/board/coreboot/coreboot.rst | 16

[coreboot] [PATCH v2 01/20] x86: coreboot: Add IDE and SATA

Add these options to permit access to more disk types. Add some documentation as well. Signed-off-by: Simon Glass --- (no changes since v1) configs/coreboot64_defconfig| 1 + configs/coreboot_defconfig | 9 + doc/board/coreboot/coreboot.rst | 20 3

[coreboot] [PATCH v3 2/2] x86: Update cbmem driver

to serial and video), use: setenv stdout serial,vidconsole,cbmem Signed-off-by: Simon Glass --- (no changes since v2) Changes in v2: - Update to support the new overflow mechanism drivers/misc/Kconfig | 8 drivers/misc/cbmem_console.c | 38

[coreboot] [PATCH v3 1/2] x86: coreboot: Update cbmem table

in src/lib/cbmem_console.c Signed-off-by: Simon Glass --- Changes in v3: - Drop __packed as it does nothing useful arch/x86/include/asm/coreboot_tables.h | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/i

[coreboot] [PATCH v2 2/2] x86: Update cbmem driver

to serial and video), use: setenv stdout serial,vidconsole,cbmem Signed-off-by: Simon Glass --- Changes in v2: - Update to support the new overflow mechanism drivers/misc/Kconfig | 8 drivers/misc/cbmem_console.c | 38 +++- 2 files changed

[coreboot] [PATCH v2 1/2] x86: coreboot: Update cbmem table

in src/lib/cbmem_console.c Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/include/asm/coreboot_tables.h | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 4d

[coreboot] Re: [SPECIFICATION RFC] The firmware and bootloader log specification

Hi Daniel, On Fri, 13 Nov 2020 at 19:07, Daniel Kiper wrote: > > Hey, > > This is next attempt to create firmware and bootloader log specification. > Due to high interest among industry it is an extension to the initial > bootloader log only specification. It takes into the account most of the >

Re: [coreboot] BIOS/CoreBoot/UBOOT

Hi, On 11 April 2018 at 16:39, Raymond Yeung wrote: > > I currently have a board that uses Intel Xeon D (previously codenamed > Broadwell DE). It boots up with BIOS/UEFI. I 'm exploring other oot-up > options here. > > > I'm not familiar with this early stage of system

Re: [coreboot] Any one have a experence the coreboot with u-boot?

+U-Boot and Bin On 29 November 2016 at 15:25, Julius Werner wrote: > edit: forgot the mailing list > > On Tue, Nov 29, 2016 at 2:24 PM, Julius Werner wrote: >> +Simon who maintains the U-Boot x86 port and might be interested >> >> In general, this