* Scott Duplichan sc...@notabs.org [110225 02:02]:
Stefan Reinauer wrote:
] +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
]if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it
]in romstage.c. Is there a chance to remove it from Kconfig instead?
Certainly the two
* Nathan Williams nat...@traverse.com.au [110225 03:08]:
When using Artec loader and no file system, use dev_name for initrd
instead of flashb.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Thanks, r141
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* Nathan Williams nat...@traverse.com.au [110225 03:34]:
load_linux_kernel() checks using_devsize, so we need to
clear it if we are using Artec loader without a file
system.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Thanks, r142
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* Patrick Georgi patrick.geo...@secunet.com [110225 13:02]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
payloads/libpayload/include/limits.h |2 ++
payloads/libpayload/include/stdint.h |5 +
2 files changed, 7 insertions(+), 0 deletions(-)
Acked-by: Stefan
new file mode 100644
index 000..ce7fe93
--- /dev/null
+++ b/payloads/libpayload/include/strings.h
@@ -0,0 +1,35 @@
+#ifndef _STRING_H
+#define _STRING_H
This should be _STRINGS_H otherwise it can/will conflict.
Otherwise
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
(-)
Nice!
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Is there some (public) documentation on how to use flashrom as a
payload, or is there a chance you could publish this?
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* Patrick Georgi patrick.geo...@secunet.com [110225 14:09]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
payloads/libpayload/bin/lpgcc |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Patrick Georgi patrick.geo...@secunet.com [110225 14:09]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
payloads/libpayload/include/pci/pci.h |1 +
payloads/libpayload/libpci/libpci.c |6 +-
2 files changed, 6 insertions(+), 1 deletions(-)
Acked-by: Stefan
* Alex G. mr.nuke...@gmail.com [110225 18:48]:
Find attached the version with the colloquial verbiage abridged.
Alex
Remove all occurences of outb(*, 0x80), and replace them with
post_code().
Create post_codes.h to store a central place for post codes.
Replace common post_codes with
* Peter Stuge pe...@stuge.se [110225 21:45]:
Patrick Georgi wrote:
+++ b/payloads/libpayload/include/stdint.h
@@ -27,4 +27,9 @@
* SUCH DAMAGE.
*/
+#ifndef __STDINT_H
+#define __STDINT_H
#include arch/types.h
+
+typedef unsigned long uintptr_t;
+#endif
What about 64
* Peter Stuge pe...@stuge.se [110225 21:48]:
Patrick Georgi wrote:
+int ffs(int i);
Wording in my ffs(3) page suggests that int can be 64 bit. We don't
care?
So far the only compiler I know where this could happen is MSVC. Since
we have an endless amount of GNUisms in all of our code that
* Patrick Georgi patr...@georgi-clan.de [110225 22:55]:
Am 25.02.2011 22:45, schrieb Stefan Reinauer:
Hm. If we touch it now, why not fix it so we don't have to care anymore?
Some smbus drivers (like the ICH7 one) are using inb already, and it
works fine.
I didn't want to block this task
for that matter)
On 02/25/2011 11:59 PM, Stefan Reinauer wrote:
refactored... should we move the delay function to a common place?
I can move it. Just which file ? Also, wouldn't this make a single patch
too hard to swallow?
Yes. I think you should remove all changes to smbus* files from
* repository service s...@coreboot.org [110224 08:43]:
Author: oxygene
Date: Thu Feb 24 08:43:37 2011
New Revision: 6378
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6378
Log:
Tyan/s2735 doesn't need to define its own hard_reset function anymore.
The southbridge already
* repository service s...@coreboot.org [110224 15:35]:
Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Thu Feb 24 14:54:10
2011(r6379)
+++
and BDG.
Signed-off-by:Rudolf Marek r.ma...@asssembler.cz
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Thanks,
Rudolf
Stefan
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* Scott Duplichan sc...@notabs.org [110224 05:03]:
The attached patch gets coreboot going on the ASRock E350M1 board.
This is an AMD family 14h Fusion board I bought for US $120, including
processor. The video option rom is from the supplied UEFI BIOS.
The patch modifies the persimmon
Any chance to move the SSDTs to the northbridge/southbridge/cpu
directory instead of having them live under mainboard?
* Scott Duplichan sc...@notabs.org [110224 07:05]:
Index: src/mainboard/asrock/e350m1/acpi/ssdt2.asl
===
---
for a hint on why it reports what it does to the SB.
]
]Marc
Also remember that the family 10h swap list problem still exists.
There are some old patches and discussion that might be useful.
Here is an example:
http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html
Acked-by: Stefan
* Georgi, Patrick patrick.geo...@secunet.com [110222 15:35]:
Am Donnerstag, den 17.02.2011, 20:05 +0100 schrieb Stefan Reinauer:
I agree we want this, though. Can you please put Makefile.inc in src/?
We currently have subdirs-y = ... util/cbfstool in there. That would be
++ugly with src
* Bao, Zheng zheng@amd.com [110223 03:31]:
The ldscript_fallback_cbfs.lb is only for the romstage. It does
nothing to change the building of ramstage. And it doesn't have area
like .data, which can be read and wrote.
From the attached build output, we can see that only crt0.romstage.o
On 2/19/11 12:45 PM, xdrudis wrote:
On Fri, Feb 18, 2011 at 10:19:31AM -0500, Ward Vandewege wrote:
Hi Xavi,
On Wed, Feb 16, 2011 at 02:45:02PM +0100, Xavi Drudis Ferran wrote:
Should I send a patch making a Kconfig option to not upgrade microcode
for fam10? Is there any interest
On 2/18/11 2:48 PM, Fengwei Zhang wrote:
Hi all,
I have a K8 board. I tried to change the DQS settings from a user
program, but I failed.
I printed out the DQS settings before my pci_write_long() function. I
also printed out the DQS settings after the pci writing. The results
are same.
My
On 2/19/11 6:51 AM, repository service wrote:
Modified: trunk/src/superio/smsc/lpc47n227/superio.c
==
--- trunk/src/superio/smsc/lpc47n227/superio.c Thu Feb 17 21:48:45 2011
(r6372)
+++
* Jørn Odberg jorn.odb...@gmail.com [110217 15:49]:
1) This is a Shuttle X27 , dual Intel Atom CPU 330.
This system is fairly similar to the Intel D945GCLF board that is
already supported by coreboot. You will have to adapt the SuperIO
settings in devicetree.cb and romstage.c to the ite/it8718f
* Keith Hui buu...@gmail.com [110217 05:52]:
Southbridge has...
bootblock.c for code required to make the whole ROM chip accessible
all ACPI stuff (will be a while before I can get to that)
There is some ACPI stuff in the northbridge, too. See Intel i945 and
sb i82801gx for an example.
one
$(call create_cc_template,smm,S))
Interesting. I think smm,S should have had -DASSEMBLY, too.
Well, even better would be to use __ASSEMBLY__ or __ASSEMBLER__ in the
code as defined by gcc for this purpose and not treat them differently
at all.
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
* Patrick Georgi patrick.geo...@secunet.com [110217 08:44]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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instead of/in addition to libpayload)
Thanks for the explanation. I felt a slight attack of panic when seeing
that stuff change so many lines of sufficiently advanced technology ;-)
I agree we want this, though. Can you please put Makefile.inc in src/?
Acked-by: Stefan Reinauer stefan.reina
* Patrick Georgi patrick.geo...@secunet.com [110217 10:24]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
Makefile | 223 ++---
Makefile.inc | 227
++
2 files
Acked-by: Stefan Reinauer reina...@google.com
On Wed, Feb 16, 2011 at 4:11 PM, David Hendricks dhend...@google.com wrote:
Hi,
Attached is a patch to add support for the SMSC MEC1308 embedded controller.
Unfortunately, the device ID it conflicts with another SMSC Super IO chip,
the FDC37M81x
.
Using adapted http://grub4ext4.googlecode.com/svn/trunk/ext4-support
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Modified:
trunk/filo/fs/fsys_ext2fs.c
This doesn't compile
Hi!
Thank you very much, Frank, Gary, Kenneth, Kerry, Kevin, Michael, Mike
and Zheng! And of course all the others that were involved! This is
great moment for coreboot, and we are all incredibly excited about this!
Those among the coreboot community that have done hardware ports before can
frank.vibr...@amd.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Vibrans, Frank frank.vibr...@amd.com [110213 22:47]:
Add AMD Agesa northbridge wrapper code. Patch 2 of 8.
This code provides cpu northbridge initialization for Family 14h cpus. It is
dependent on the AMD Agesa code.
Signed-off-by Frank Vibrans frank.vibr...@amd.com
Acked-by: Stefan
* Vibrans, Frank frank.vibr...@amd.com [110213 22:49]:
Add AMD CIMx SB800 wrapper code. Patch 3 of 8.
This code provides southbridge initialization for SB800 south bridges. It is
dependent on the AMD CIMx/SB800 code.
Signed-off-by Frank Vibrans frank.vibr...@amd.com
Acked-by: Stefan
of 8.
This code provides cpu early initialization for Family 14h cpus. It is
dependent on the AMD Agesa code.
Signed-off-by Frank Vibrans frank.vibr...@amd.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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. The former issue will be addressed
shortly, and the latter issue requires community assistance. This code
is dependent on the AMD Family 14h mainboard code.
Signed-off-by Frank Vibrans frank.vibr...@amd.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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...@amd.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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-by Frank Vibrans frank.vibr...@amd.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Антон Кочков anton.koch...@gmail.com [110214 22:02]:
superiotool: add support for producing xml files from C code
Signed-off-by: Anton Kochkov anton.koch...@gmail.com
Is it possible to make superiotool read those instead of the C
structures as its database?
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On 11.02.2011, at 01:38, Patrick Georgi patrick.geo...@secunet.com wrote:
lpgcc was too noisy in some cases
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
---
payloads/libpayload/bin/lpgcc |4 +++-
1 files changed, 3
On 11.02.2011, at 01:36, Patrick Georgi patrick.geo...@secunet.com wrote:
- Add assert.h
- Add arpa/inet.h
- Add assert-macro
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
---
payloads/libpayload/include/arpa/inet.h
On 11.02.2011, at 01:57, Patrick Georgi patrick.geo...@secunet.com wrote:
- Add FILE*
- Add stdout, stdin, stderr stubs
- Add fprintf that redirects to printf for stdout and stderr and fails
otherwise
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer
On 11.02.2011, at 02:00, Patrick Georgi patrick.geo...@secunet.com wrote:
If we have it, why not use it?
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
---
payloads/libpayload/include/assert.h |3 ++-
payloads
* Mark Marshall mark.marsh...@csr.com [110210 11:52]:
I found the same thing as you a while ago. The io_info structure in
pnp.h is never referenced by the code, and it's purpose is never
really defined anywhere. If you change the name to something else
(just in the header file) the code
* Peter Stuge pe...@stuge.se [110209 20:44]:
I checked the content of build/coreboot.rom and the last byte was
0x0a!! Which is written probably on the top of our EEPROM. Right?
but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!!
SECTIONS {
_ROMTOP = 0xfff0;
* Georgi, Patrick patrick.geo...@secunet.com [110208 11:26]:
More general question (shouldn't stop anyone from committing this
patch): Should we move hardware access code to directio and use its API
on all platforms (not just Darwin, and - in theory - win32)?
Though in that case, we might want
* Stefan Reinauer stefan.reina...@coreboot.org [110203 22:33]:
* Peter Stuge pe...@stuge.se [110129 21:26]:
See patch.
The new TAG-stable points to the very latest commit in seabios.git,
which may not be quite right, but both stable and master must be
using Kconfig.
//Peter
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: payloads/external/SeaBIOS/Makefile.inc
===
--- payloads/external/SeaBIOS/Makefile.inc (revision 6326)
+++ payloads/external/SeaBIOS/Makefile.inc (working
* Alex G. mr.nuke...@gmail.com [110202 20:23]:
Add GPL license headers to all files in src/cpu/amd/model_fxx
(except microcode).
Signed-off-by Alexandru Gagniuc mr.nuke...@gmail.com
Acked-by Alexandru Gagniuc mr.nuke...@gmail.com Trivial
Not trivial at all, but legally kind of troublesome.
Thanks to Patrick Georgi for finding this:
---
http://www.ohloh.net/p/coreboot/factoids/4229016
Very large, active development team
Over the past twelve months, 25 developers contributed new code to
coreboot.
This is one of
* xdrudis xdru...@tinet.cat [110130 20:59]:
Yes, it'd be mostly unneeded, but anyway the patch I sent does not
disable it in ramstage. So it still causes sprintf to consume
the double of bytes maybe beyond its buffers (and produce
unreadable messages). The idea can work, the perl script may
On 29.01.2011, at 06:34, Kevin O'Connor ke...@koconnor.net wrote:
SeaBIOS is moving to Kconfig. This will make it easier to configure
coreboot and seabios going forward. However, it will also break the
coreboot build in the short term. This patch, freezes the master
branch of coreboot's
* Danila Sukharev mam...@gmail.com [110130 06:00]:
Hi there!
I'm a QA guy interested in coreboot project. I have two mobos supported by
coreboot; also I have some QA and dev skills (but mostly QA).
I also have the ability to check the coreboot on some other mobos - I have
them
in my hands
* Georgi, Patrick patrick.geo...@secunet.com [110128 08:22]:
Am Donnerstag, den 27.01.2011, 18:16 -0800 schrieb Stefan Reinauer:
+#if defined(__ROMCC__)
+#define printk(BIOS_DEBUG, fmt, arg...) do {} while(0)
+#else
romcc doesn't support variadic macros. This only works because
patrick.geo...@secunet.com
nice!
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Georgi, Patrick patrick.geo...@secunet.com [110128 15:32]:
Hi,
attached patch inverses two arguments of cbfs-files-y and adapts its
users (one of which already used the new order). This is in reponse to
feedback that the original setup was too complicated.
New cbfs-files-y:
...@gmail.com
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Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if
a rare condition arises.
Based on findings by Alexandru Gagniuc
* Alex G. mr.nuke...@gmail.com [110128 13:05]:
Added PCI ID's for the functions of the VIA K8T800(Pro) and K8M800 chipsets.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
---
Although this is very trivial, I don't think I'm in the position to ack.
Alex
Hm.. Is there a chance to
* Patrick Georgi patrick.geo...@secunet.com [110127 15:15]:
Einfaches Textdokument attachment (20110127-1-less-magic-for-regex.diff)
Not a good changelog suggestion ;-)
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
* Patrick Georgi patrick.geo...@secunet.com [110127 15:07]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Patrick Georgi patrick.geo...@secunet.com [110127 15:07]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Patrick Georgi patrick.geo...@secunet.com [110127 15:07]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Patrick Georgi patrick.geo...@secunet.com [110127 15:07]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Mixed use of uint32_t and u32. Otherwise
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: nvramtool/accessors/layout-bin.c
* Patrick Georgi patrick.geo...@secunet.com [110127 15:07]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* trevor.davenp...@gmail.com trevor.davenp...@gmail.com [110127 02:56]:
Hi,
I've been trying to get coreboot to work a machine i have (http://
www.coreboot.org/pipermail/coreboot/2010-November/061987.html) but have so far
have not had any luck. I've tried most board types that are similar
to need this)
- src/pc80/usbdebug_serial.c is not needed
- some small console cleanups
Signed-off-by: Stefan Reinauer reina...@google.com
Index: src/include/usbdebug.h
===
--- src/include/usbdebug.h (revision 6307)
+++ src/include
up in, but this has
to do for now.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
+ if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
Do we want a wrapper like this?
#define read_cmos_option(option, default
* repository service s...@coreboot.org [110125 20:27]:
Author: stepan
Date: Tue Jan 25 20:27:23 2011
New Revision: 6298
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6298
Log:
Fix abuild
thanks to Kevin who came up with this
Not this is just to get this working. I think we
Nice work, Rudolf!
Index: src/mainboard/asrock/939a785gmh/romstage.c
===
--- src/mainboard/asrock/939a785gmh/romstage.c(revision 6298)
+++ src/mainboard/asrock/939a785gmh/romstage.c(working copy)
@@ -48,6 +48,9
random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Stefan
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,
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* Peter Stuge pe...@stuge.se [110124 00:35]:
I neither want to check the changes I make to the config file in to
the local repository
Can we please not use perl for this? sed can do it just fine.
Sure. Not all sed versions support in-place changes though, so the code
will have to handle
* Kevin O'Connor ke...@koconnor.net [110122 17:28]:
Use a tag (rel-0.6.1.3) for SeaBIOS stable checkouts instead of the
stable branch. The tag is a little safer because it prevents an
incorrect commit to the stable branch from being immiediately picked
up by coreboot users.
Note -
* Kevin O'Connor ke...@koconnor.net [110123 17:12]:
On Sun, Jan 23, 2011 at 07:43:59AM +0100, Peter Stuge wrote:
Kevin O'Connor wrote:
Use a tag (rel-0.6.1.3) for SeaBIOS stable checkouts instead of the
stable branch. The tag is a little safer because it prevents an
incorrect commit
Super I/O
Signed-off-by: Christian Ruppert id...@gentoo.org
Acked-by: Stefan Reinauer ste...@coreboot.org
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* Georgi, Patrick patrick.geo...@secunet.com [110120 14:34]:
Hi,
in preparation of teaching nvramtool to edit files instead of real
hardware, this patch abstracts CMOS accesses a bit more.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Signed-off-by: Stefan Reinauer ste
* Georgi, Patrick patrick.geo...@secunet.com [110120 14:35]:
Attached patch allows nvramtool to work on in-memory data.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer ste...@coreboot.org
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http
on cmos.default then.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer ste...@coreboot.org
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* Georgi, Patrick patrick.geo...@secunet.com [110120 14:38]:
This patch adds a -D option to tell nvramtool to work on data in a plain
CMOS image (as extracted by the nvramtool dump option, for example).
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Nice work!
Acked-by: Stefan
Please add a comment that this is needed for parsing the cmos_layout.bin
file in cbfs.
Acked-by: Stefan Reinauer ste...@coreboot.org
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* Yoo, Taik-Yon jaa...@gmail.com [110121 03:39]:
I built r6275 for my RS690/SB600 based box with debug level 8.
This box did not boot up.
The last displayed console message is `bsp_apicid=0x`.
This happens line 269 at src/console/vtxprintf.c.
...
num = va_arg(args, unsigned int);
...
* Nils njaco...@hetnet.nl [110120 23:59]:
I investigated this some more and i think i found the problem.
The crosscompiler is working ok now and my coreboot rom has the same size as
the one from the automatic build system of coreboot.org exept for the SeaBios
payload mine is 46881 bytes and
*pDCTstat)
{
pDCTstat-PresetmaxFreq = 800;
}
Is it safe to add this to the repository? I'm worried that people will
forget over time.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Stefan Reinauer ste...@coreboot.org
Index: src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
* Sven Schnelle sv...@stackframe.org [110117 21:46]:
Index: src/ec/acpi/ec.h
===
--- src/ec/acpi/ec.h (revision 0)
+++ src/ec/acpi/ec.h (working copy)
@@ -17,9 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor,
* Peter Stuge pe...@stuge.se [110117 03:25]:
repository service wrote:
+++ trunk/src/pc80/mc146818rtc_early.c Fri Jan 14 08:40:24 2011
(r6253)
..
static inline int do_normal_boot(void)
{
+ char *cmos_default = cbfs_find_file(cmos.default, 0xaa);
unsigned char
...@koconnor.net
Acked-by: Stefan Reinauer ste...@coreboot.org
Modified:
trunk/src/arch/x86/include/arch/interrupt.h
Modified: trunk/src/arch/x86/include/arch/interrupt.h
==
--- trunk/src/arch/x86/include/arch
* Nils njaco...@hetnet.nl [110113 15:42]:
Add Geode GX2 memmory descriptors.
Add a simple README file.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Thanks, Nils.
Thanks, r6274
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* Nils njaco...@hetnet.nl [110113 16:19]:
Hello all,
In the past i used coreboot without a VGAbios and used the linux framebuffer
driver and that works ok.
I am trying to get onboard early VGA running on my Geode GX2 board but until
now i have no succes.( the screen stays black until the
* Alex G. mr.nuke...@gmail.com [110114 16:37]:
Added preliminary support for the ASUS K8V-X SE and the VIA K8T800
chipset. Coreboot is able to finalize and load SeaBIOS, which boots from
IDE HDD or DVD. IRQ ACPI and MP tables are not yet complete.
Signed-off-by: Alexandru Gagniuc
* Bao, Zheng zheng@amd.com [110111 03:19]:
I personally like this patch, not because I did. It is easy to use and
handle. I am gonna signed-off-by it. If I get support, I will check it in.
Zheng
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Stefan Reinauer ste...@coreboot.org
); // Serial Port 2 Multi Function Pin
Select
break;
Can you please try and see if this does the job?
Signed-off-by: Stefan Reinauer ste...@coreboot.org
break;
case VT1211_ROM:
/* TODO: Error. VT1211_ROM doesn't have an I/O base. */
--
coreboot mailing
* Peter Stuge pe...@stuge.se [110119 07:55]:
Sven Schnelle wrote:
+++ src/ec/acpi/Makefile.inc(revision 0)
@@ -0,0 +1 @@
+driver-y += ec.c
..
+++ src/mainboard/roda/rk886ex/Makefile.inc (working copy)
@@ -18,7 +18,6 @@
##
ramstage-y += m3885.c
-ramstage-y +=
* Stefan Reinauer stefan.reina...@coreboot.org [110119 07:37]:
* Peter Stuge pe...@stuge.se [110117 03:25]:
repository service wrote:
+++ trunk/src/pc80/mc146818rtc_early.cFri Jan 14 08:40:24 2011
(r6253)
..
static inline int do_normal_boot(void)
{
+ char
uncompression without caching. I had to wade
through the effects of this patch. This patch is a regression - it
makes the code harder to understand.
-Kevin
I agree. And I would like to back it out. Will do so if I get 2 acks.
Signed-off-by: Stefan Reinauer ste...@coreboot.org
-by: Kevin O'Connor ke...@koconnor.net
Acked-by: Stefan Reinauer ste...@coreboot.org
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* Marc Bertens mbert...@xs4all.nl [110116 21:57]:
Hi all,
Acked-by: Marc Bertens mbertens.xs4all.nl
Tested-by: Marc Bertens mbertens.xs4all.nl
Guess it needs a Signed-off-by from you...
http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
Acked-by: Stefan Reinauer ste
* Kevin O'Connor ke...@koconnor.net [110116 18:59]:
The cn700.c code references mainboard_interrupt_handlers() which isn't
defined if VGA_ROM_RUN is off. Define a dummy implementation of that
function for this case.
Signed-off-by: Kevin O'Connor ke...@koconnor.net
Acked-by: Stefan Reinauer
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