Re: [coreboot] coreboot is going to make kcma-d8 obsolete

On Sat, Apr 07, 2018 at 02:25:19PM +0100, Leah Rowe wrote: > If you've got a D16 to submit reports on, that'd also be great. I just pushed one on the D16. Thanks, Ward. -- Ward Vandewege GPG Key: 25F774AB Do you use free software? Donate to join the FSF and support freedom at

[coreboot] OpenBMC/iKVM4 on KGPE-D16: bmc doesn't power up automatically on cold boot

known issue? Thanks, Ward. -- Ward Vandewege GPG Key: 25F774AB Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] kexec of Xen hypervisor from a Linux payload

; My 4.6.3 Xen tree is hacked up right now with stuff copied from old > versions of the tree, so I'll clean it up and see if they are interested > in accepting patches. Oh, wow, thank you! Sorry that I didn't spend time tracking that down properly back in 2008. I'd be intereste

Re: [coreboot] coreboot ported to the ASUS KGPE-D16 (Libreboot: blobless, fully functional!)

On Wed, Apr 29, 2015 at 10:46:29PM +0100, The Gluglug wrote: > You should crowd-fund the $35,000 figure, there are lots of people who > will be interested in this. I personally will chip in, and I'd ask > others to as well. I would chip in too. Thanks, Ward. -- Ward Vandewege GPG

Re: [coreboot] Are any Chromebooks able to run fully libre?

I tested those on the Asus F2A85-M/CSM board. You can also omit the optional xhci blob (no usb3 support) as well as the VGA BIOS. Thanks, Ward. -- Ward Vandewege GPG Key: 25F774AB Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_f

Re: [coreboot] Issues getting ASUS F2A85-M to boot

oard entirely (and let it sit a few seconds to allow the caps to drain) when switching between proprietary bios and coreboot. For me this port works out of the box with the default settings. If you like I can send you a link to a known-good image that we use here, so that you can verify your hard

Re: [coreboot] DDR fails on F2A85-M

On Wed, May 22, 2013 at 11:18:46AM -0400, Ward Vandewege wrote: > However, hd/strings suggest that the AGESA version is v1.1.0.7: > > 206209:007acd40 00 00 00 00 30 30 30 30 41 47 45 53 41 00 00 00 > |AGESA...| > 206210-007acd50 56 31 2e 31 2e 30 2e 37 20 20 20

Re: [coreboot] DDR fails on F2A85-M

00 30 30 30 30 41 47 45 53 41 00 00 00 |AGESA...| 206210-007acd50 56 31 2e 31 2e 30 2e 37 20 20 20 20 00 00 00 00 |V1.1.0.7 | Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://status.fsf.org/ward http://fsf.org/blogs/RSS

[coreboot] server board support - Supermicro H8DGi-F ?

speed issue with AGESA 1.0.3. Anyone else interested in working on a port of H8DGi-F or a similar board? Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate to join the FSF and su

Re: [coreboot] Gerrit problem: Not able to sign in

; Thanks, > > > > Paul > > I have the same problem This is now fixed. Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate to join the FSF and support freedom a

Re: [coreboot] [SPAM] Re: Feedback On Coreboot: the Solution to the SecureBoot Fiasco

On Mon, Jan 07, 2013 at 03:29:01PM +0100, Xavi Drudis Ferran wrote: > For now secure boot only restricts what we boot (and the booted OS restricts > the rest > of what we run). But in the end the purpuse is to stablish a DRM scheme so > that > if a server can't prove that we're running software

Re: [coreboot] tyan s2882-d not booting

visions from the old SVN tree; you can grep the git log for the svn revision number (it is listed); you'll see these are revisions from 2006. I do have an s2881 that I booted succesfully about 5 or 6 weeks ago, with coreboot head. It's a very similar board. Have you tried with less ram?

Re: [coreboot] Moving gerrit to an separate mailing list

ate lists. I hope you all agree. I very much agree. Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_

Re: [coreboot] New Motherboards?

t; Two; I have two identical M-Audio Delta 1010s. Finding a modern board with two 'old' PCI slots may be difficult, regardless of coreboot... Have you seen any at all? Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fs

Re: [coreboot] separate mailling list for gerrit mails?

On Sun, Mar 11, 2012 at 10:19:41PM -0400, Kevin O'Connor wrote: > I'd prefer if they were on a separate email list. Me, too. Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free sof

Re: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13

ou bring too much hardware, but we've never had any (real) > trouble with that approach when trying this in Brussels, Denver or > Hamburg. :-) Well, in Hamburg they were a bit upset about this after about three consecutive evenings of hacking in the hotel lobby. Ah, well. Thanks, War

Re: [coreboot] Microcode CPU writeup

On Mon, Feb 28, 2011 at 08:16:10AM +0100, Rudolf Marek wrote: > Would someone be interrested if I write something about microcoded > CPUs controllers? Like the classic uCode ROM + ALU + Regs + IO unit? Please go for it! Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: co

Re: [coreboot] [PATCH] disabling microcode update

if around the call. Those > files are > src/cpu/amd/model_10xxx/init-cpus.c > src/mainboard/*/*/romstage.c > (and by */* I mean all or some of the fam 10 boards, not all boards). This is the option that Stepan and Peter prefer, so this seems like the best way forward? I'd test a

Re: [coreboot] Fam10 FIDVID in SVI : disabling microcode update

Hi Xavi, On Wed, Feb 16, 2011 at 02:45:02PM +0100, Xavi Drudis Ferran wrote: > Should I send a patch making a Kconfig option to not upgrade microcode for > fam10? Is there any interest in that ? Yes, please. I would test and ack that. Thanks, Ward. -- Ward Vandewege Free So

[coreboot] enabling expert mode -> build fails (warnings treated as errors) on fam10 boards

appear to be used anywhere but in the checks in h3finit.c. What's the best way to fix this? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] don't print too early on mcp55-based boards

On Mon, Nov 01, 2010 at 11:01:41PM +0100, Peter Stuge wrote: > Ward Vandewege wrote: > > See attached. Perhaps we should also print a post code if the SMBus > > controller can't be found - suggestions for a value? > > 0x5B ? Let's do that as part of the die modific

Re: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig

lable: http://www.newegg.com/Product/ProductList.aspx?Submit=ENE&DEPA=0&Order=BESTMATCH&Description=ddr3+quad+rank&x=0&y=0 Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] don't print too early on mcp55-based boards

hat is that it would clobber any previous post codes, which might be a better indicator for what's going wrong. Perhaps a good way to deal with fatal runtime error conditions would be a) set a unique post code b) call die in the assumption that die does not clobber the post code. What

[coreboot] [PATCH] don't print too early on mcp55-based boards

See attached. Perhaps we should also print a post code if the SMBus controller can't be found - suggestions for a value? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator We can't print this early. This patch fixes a hang on superm

Re: [coreboot] [PATCH] Gigabyte MA785GMT support

ng the short. See http://www.coreboot.org/GIGABYTE_GA-MA785GMT-UD2H Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Gigabyte MA785GMT support

ain bios). > signed-off-by Wang Qing Pei Thank you! I have a few of these boards arriving next week and will be testing this. Thanks! Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Simplify device enabling and initialization

gt; > http://ward.vandewege.net/coreboot/s2881/20100621-myles/ > > Thanks for testing Ward! As far as I can see, both worked, but 1+2+3+4 is > cleaner. It doesn't look like there is an ADM1027 on your board. > > Is there something missing before an Ack & commit

Re: [coreboot] [PATCH] Simplify device enabling and initialization

On Mon, Jun 21, 2010 at 07:36:39AM -0600, Myles Watson wrote: > On Mon, Jun 21, 2010 at 5:59 AM, Myles Watson wrote: > > On Sun, Jun 20, 2010 at 8:11 PM, Ward Vandewege wrote: > >> Hi Myles, > >> > >> Everything seems fine with either patch - but there a

Re: [coreboot] [PATCH] Simplify device enabling and initialization

r why the temperature values look right in all cases. Does it > need to be cold booted in order for the initialization to be needed? All boots were cold. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Simplify device enabling and initialization

changeset), r5635 + patch 1 and r5635 + patch 2. Let me know if you need anything else... Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Simplify device enabling and initialization

Ward? Yep, I've got (the guts) of an s2881 lying on my desk here, and can test any patches you throw at me :) Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [h8dme-fam10] acquiring coreboot skills from scratch somewhat daunting

gt; > Another data point: It _does_ continue after the hang, but it takes about > an hour. Oh! That's interesting. I never tried to leave the board alone for that long. > I image each memory write is timing out so a bunch of writes via > memset drags the total timeout to an hour

Re: [coreboot] Indtast Bcc Indtast Bcc Wyse S10 and coreboot

i-dev since Intrepid, and they dropped the virtual pciutils-dev package that refers to libpci-dev in Lucid. I've put a note to that effect on the wiki, too. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] gPXE not found?!

     0x13d00    stage        43730 > > fallback/payload                        0x1e840    payload      34069 > > pci1002,515e.rom                     0x26dc0    optionrom    45056 > > > pci8086,1076.rom                     0x31e00    unknown      72704 > Doesn't this need to be of type opti

Re: [coreboot] [commit] r5560 - in trunk/src: . drivers drivers/sil drivers/sil/3114 mainboard/tyan/s2881 mainboard/tyan/s2882

rom image, or loaded via gpxe or some other means. I can't imagine the use case where you would *not* want to have the mode set to make the drive bootable. Unless there is some downside to doing so that I'm totally missing? Thanks, Ward. -- Ward Vandewege Free Software Founda

Re: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114)

Acked-by: Ward Vandewege Thanks! Ward. On Sun, May 09, 2010 at 12:33:50AM +0200, Rudolf Marek wrote: > The sil3114 chip has a class code set to something else then IDE by strap > resistor. It took me long time to figure out that this chip is otherwise IDE > compatible ;) > > Tr

Re: [coreboot] Query, known-good CPUs to use in a H8DME-2 mb?

h are of the fam10 line, with a pair of model # > CPUs, which are of the K8 line. The port for that board was done on a pair of 2216 HE CPUs. You may be hard pressed to find those for sale these days... Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administr

Re: [coreboot] H8DME-2 woes, hints?

m10. I think it would be more fruitful for you to look at one of the > boards that has both fam10 and k8 support, and try to put together an > h8dme_fam10 port. For the record, I've been trying to get that going for a while, but have not had much success - very early hangs in the fam10

Re: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard

nux kernel anymore. There appear to be public datasheets for Sil3114, referenced here https://ata.wiki.kernel.org/index.php/Sata_sil And the kernel driver also knows how to bring it up, since using a linux kernel as a payload has worked for me in the past. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] H8QME-2+ boot problems on different machines.

s? And the hardware is identical? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] warning days - m57sli/mcp55

t; > > since this is a C file that is included in exactly one file, > "raminit_f.c" you could as well just mark the function "static". Done. > btw, for function prototypes the extern in not really needed. I keep > removing them from the tree, but if people thi

[coreboot] [PATCH] warning days - m57sli/mcp55

If there are better ways to kill the warnings, please let me know! Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator This fixes a number of warnings when building m57sli (and other boards with mcp55). This patch is boot tested on m57sli. What appears to

Re: [coreboot] [PATCH]: AMD RS780/SB700 support

and > not rv610. I just added the ID and it does work it seems. But that Gigabyte board is DDR3 - didn't Zheng say that was not supported with fam10 CPUs yet? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator Join us in Cambridge for LibrePlane

Re: [coreboot] Un-brick a GAM57SLIS4

oggle between your 2 chips. If the second one has a good image, this should work. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator Join us in Cambridge for LibrePlanet, March 19th-21st! http://groups.fsf.org/wiki/LibrePlanet2010 -- coreboot mailing

Re: [coreboot] Supermicro H8QME-2+ mct_d fatal exit.

ones :) Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator Join us in Cambridge for LibrePlanet, March 19th-21st! http://groups.fsf.org/wiki/LibrePlanet2010 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] server hardware without IPMI / with coreboot

ase docs (and code?) for the SR56x0/SP5100 chipset. With that, supporting any of the boards listed above might be possible. This chipset is likely to be around for a while (5 years?). Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Hi...all

arious brands, so far I like Raritan's Dominion series the best). That works, 100% of the time. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Tester hardware

On Wed, Feb 24, 2010 at 12:14:30AM +0100, Carl-Daniel Hailfinger wrote: > On 23.02.2010 21:14, Peter Stuge wrote: > > Ward Vandewege wrote: > > > >> The automatic testing framework Stepan built a few years ago - I'd > >> love to get a few boards set

Re: [coreboot] More lists

On Tue, Feb 23, 2010 at 10:47:21AM -0700, Myles Watson wrote: > > Could we have some tag to svn commit like: > > > And then add: > > > > current->works > And also the "haha this is broken" tag and maybe the "will fry your > mainboard" tag. :) > > One problem is that commits that are board-specif

Re: [coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)

On Wed, Feb 03, 2010 at 07:00:25PM +0100, Patrick Georgi wrote: > Am 03.02.2010 18:50, schrieb Ward Vandewege: > > This fixes breakage introduced in r5051. > Sorry for that. I assumed newconfig would be fine: > > (Options.lb) > #make the SB HT chain on bus 0, default

Re: [coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)

On Wed, Feb 03, 2010 at 06:52:57PM +0100, Stefan Reinauer wrote: > On 2/3/10 6:50 PM, Ward Vandewege wrote: > > This fixes breakage introduced in r5051. > > > > Thanks, > > Ward. > > > > > Sorry for the inconvenience. > > Acked-by: Stefan

[coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)

This fixes breakage introduced in r5051. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator Revision 5051 broke Kconfig booting for the Tyan s2881 board. Up to 5050, there were two SB_HT_CHAIN_ON_BUS0 sections in the mainboard Kconfig file - one setting

[coreboot] dell server BIOS setting insanity

Hi all, I thought I'd point out this little gem from the linux-poweredge list http://lists.us.dell.com/pipermail/linux-poweredge/2010-January/041170.html Apparently several lines of Dell servers have a BIOS setting called "Cores-per-processor". It seems they ship these machines with the set

Re: [coreboot] Memtest86+ failing on coreboot system.

to the list? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] fam10/newconfig on supermicro h8dme - early hang

y good: 0xf870 which is 1111 So the default link is 0, and the Routing Table Disable bit is set to zero. You mentioned bit 11 - that seems to be marked as 'reserved' in the BKDG for fam10? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Admi

Re: [coreboot] fam10/newconfig on supermicro h8dme - early hang

FN(CONFIG_CDB, 0)); //0x00 OK - with that patch it builds and boots, and the output looks similar (but not identical. See http://ward.vandewege.net/coreboot/h8dme/fam10/minicom-20091222af-ram-on-both-cpus.cap The only difference is this -MMIO(b8)00-31a4f2, ->(0,1), , , CPU disab

Re: [coreboot] fam10/newconfig on supermicro h8dme - early hang

gt; If inl and outl are hanging, I would dump the routing registers and read the > device's IDs to see what's going wrong. I'm not very familiar with how the > fam10 code works, but dumping the routing registers should be mostly cut and > paste from the k8/util.c code. Right

Re: [coreboot] fam10/newconfig on supermicro h8dme - early hang

/mcp55/mcp55_early_setup_car.c Log attached. Anything else I should try? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator minicom-20091222aa-all-ram-on-cpu1.cap Description: application/cap -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/m

Re: [coreboot] Problems porting H8dmr_fam10 to H8qme-2+

ment out that if/endif lines and have CONFIG_LOGICAL_CPUS set to zero. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] fam10/newconfig on supermicro h8dme - early hang

se you're interested: http://ward.vandewege.net/coreboot/h8dme/fam10/src-mainboard-supermicro-h8dme_fam10.tgz http://ward.vandewege.net/coreboot/h8dme/fam10/targets-supermicro-h8dme_fam10.tgz Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot maili

Re: [coreboot] coreboot hangs on my AMD fam10 board(updatedebugmessage).

solve this. Does that help? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [v2] r4886 - in trunk/coreboot-v2/util: . amdtools amdtools/example_input

place. What's our current thinking on that? I'd be happy to svn move them... Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]

lar box is in production. What toolchain are you using? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Resend: [PATCH] add h8dmr fam10 target

do some more testing on this hardware, but it's in production so that's a little hard right now. I'm going to work on a supermicro h8dme fam10 port now, which is a very similar board, so hopefully I'll be able to try the suggestions in this thread on that. Thanks! Ward. --

Re: [coreboot] Resend: [PATCH] add h8dmr fam10 target

On Tue, Sep 22, 2009 at 03:29:05PM +0200, Peter Stuge wrote: > Ward Vandewege wrote: > > Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan > > s2912 > > fam10 and h8dmr k8 targets. > > > > Many, many thanks to Marc, Myles, Patrick and Stepan

Re: [coreboot] Tyan s2881 Kconfig

gt; $39 for those boards is pretty attractive, do you have a link? > > > http://www.pacificgeek.com/product.asp?id=847374 Argh, can not resist. Ordered :) Good for spare parts, too - I've still got a couple of those out in the field... Thanks, Ward. -- Ward Vandewege Free Software Found

Re: [coreboot] GPIOs on CS5536 based boards

sy to fix. If it is > > below 0x1000 it is almost trivial. > > It's at 6000 something, and I don't like to. I would much prefer the > driver not make assumptions for no da^Wreason. I think the driver assumes CS5536_BASE = 0x06100 Thanks, Ward. -- Ward Va

Re: [coreboot] GPIOs on CS5536 based boards

up the msr and then do the right thing, but it does not. I think Peter Stuge may have a patch for the LED driver... Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/li

Re: [coreboot] unstable AMD Fam10h boot

g this week, so I should be able to test this in a couple days. Will do as soon as we get the hardware. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] unstable AMD Fam10h boot

on multiple cores, from my > understanding. Not to complicate matters even further, but since we are talking about locking - will any of this improve the 'many cores talking to serial at once' problem? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior

Re: [coreboot] K8 machine with (a lot of) ram from 2 vendors keeps resetting

m-20090902-with-64G-samsung-on-cpu1-kingston-on-cpu2-after-533MHz-limit.cap This is with all samsung ram on CPU1 and all kingston ram on CPU2, as you suggested on irc. Anything else I should try? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- c

Re: [coreboot] PATCH: do not rely on "tempfile" being available

On Wed, Sep 02, 2009 at 04:12:21PM -0400, Bernie Innocenti wrote: > Signed-off-by: Bernie Innocenti > > Build fix: add a fallback for systems where tempfile is missing Acked-by: Ward Vandewege Committed in r271. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senio

Re: [coreboot] unstable AMD Fam10h boot

he patch changes is > 0x10efff. This value appears if the result of the cpuid call (or NB > probe) is 0xff (the highest 8 bits aren't counted in, it might be > 0x, too)' I've seen this occasionally, too. I suspected compiler issues again... Thanks, Ward. -- Ward V

Re: [coreboot] HP dl145 g3

> Do you want me to file a bug for this? Or is adding a cmdline option > considered a good solution? I think that should be considered a bug. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Memtest86

nths or so ago iirc, but it highly depended on the version I tried. I think, maybe, that 3.4 was working for me but I'm not sure. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.o

Re: [coreboot] Tyan S2912[Fam10] HTX problem

4. Also, are you sure your CONFIG_HT_* settings are correct? I found that CONFIG_HT_CHAIN_UNITID_BASE really has to be 1 to get a bootable system with mcp55 on fam10. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: core

Re: [coreboot] AMD RS780 docs released, coreboot support coming

On Sat, Aug 08, 2009 at 09:46:22AM +, Zheng Bao wrote: > Oh, by the way, please add a 780 entry in the > http://www.coreboot.org/Datasheets. Done. Many thanks! Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

On Thu, Aug 06, 2009 at 10:26:38AM +0800, Bao, Zheng wrote: > I am trying to port the ddr3 feature. I will submit a full patch to > replace this one. Sounds good, thanks. I won't be able to test until the end of August though, but perhaps someone else can ack before then. Thanks, Ward

Re: [coreboot] seabios head breaking irqs?

On Tue, Jul 28, 2009 at 08:49:22PM -0400, Kevin O'Connor wrote: > On Mon, Jul 27, 2009 at 11:32:16PM -0400, Ward Vandewege wrote: > > Hi Kevin et al, > > > > I just tried seabios head on my h8dmr fam10 system, and got rather odd > > results - suddenly I am se

[coreboot] seabios head breaking irqs?

-gf.cap OK: http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-gg.cap I'm not sure if this could be caused by seabios, or if perhaps it's yet another toolchain problem. When reverting to the older seabios, the irq problems went away again. Thanks, Ward. -- Ward Vandewege -- corebo

[coreboot] solved - Re: fam10/h8dmr: extreme slowness in CBFS memset /memcpy

witched back to gcc-3.4 (GCC) 3.4.6 (Ubuntu 3.4.6-8ubuntu2) on 32 bit, and it's gone altogether, every time. Is anyone else using gcc 4.3 (32 bit) to compile coreboot? Thanks! Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot cbfs > incorrect bootblock size

s what I am not doing or not doing correctly? See http://www.coreboot.org/pipermail/coreboot/2009-June/049363.html where Patrick explained how to convert a board to CBFS. I've used those instructions with success before. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior

Re: [coreboot] fam10/h8dmr: extreme slowness in CBFS memset / memcpy

d go even slower. > > Sorry that's not much help, but I don't have a fam10 box to try things on. Thanks - will see if I can try some of these things. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] fam10/h8dmr: extreme slowness in CBFS memset / memcpy

size= 512MB: uncachable, count=1 Any thoughts on something else I should look at to debug this? Thanks, Ward. On Sun, Jul 19, 2009 at 09:23:21PM -0400, Ward Vandewege wrote: > Hi all, > > I'm working on a fam10 tree for supermicro h8dmr. I'm using CBFS. > > It boots

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

md.com/documentation/guides/Pages/default.aspx to the Fam10 revision guide is wrong, the correct link is http://support.amd.com/us/Processor_TechDocs/41322.pdf > The actual socket type > should be read from CPUID_8001_EBX. Right? I think so, according to the revision guide... Thanks, War

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

s public. > 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is > just half tested. >I am not confident it is 100% correct. > > Zheng > > > Signed-off-by: Zheng Bao With this patch, I can still boot my system with 00100F42h (RB-C2) CPUs - Opteron

[coreboot] fam10/h8dmr: extreme slowness in CBFS memset / memcpy

Rs - looking at the logs it seems MTRRs are not set up until well after CBFS has dealt with coreboot_ram. This box has 32GB of ram, in case that makes a difference. Any suggestions? Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/m

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

e most certainly talking about Socket F. I have a few Opteron 2372 HE CPUs that are 0x100F42. > You can contact tim.per...@amd.com about the patch releasing. Thank you, I have done so. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] [PATCH] update S1g1 CPU names as per AMD revision guide

s/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf > > > > This patch takes its data from Table 9. > > > > Build tested. > > > > Signed-off-by: Ward Vandewege > > Acked-by: Stefan Reinauer r4434. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] update Socket F CPU names as per AMD revision guide

d.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf > > > > This patch takes its data from Table 7. > > > > Build tested. > > > > Signed-off-by: Ward Vandewege > > > Acked-by: Stefan Reinauer r4433. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] update AM2 CPU names as per AMD revision guide

On Fri, Jul 17, 2009 at 05:07:31PM +0200, Stefan Reinauer wrote: > Ward Vandewege wrote: > > See attached... > > > > Thanks, > > Ward. > > > > > Acked-by: Stefan Reinauer r4432. Thanks, Ward. -- Ward Vandewege -- coreboot mailing list: cor

[coreboot] [PATCH] update S1g1 CPU names as per AMD revision guide

See attached... Thanks, Ward. -- Ward Vandewege Bring S1g1 cpu names up to date with the official Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes its data from

[coreboot] [PATCH] update Socket F CPU names as per AMD revision guide

See attached... Thanks, Ward. -- Ward Vandewege Bring Socket F cpu names up to date with the official Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes its data

[coreboot] [PATCH] update AM2 CPU names as per AMD revision guide

See attached... Thanks, Ward. -- Ward Vandewege Bring AM2 cpu names up to date with the official Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes its data from

[coreboot] add pretty cpu name for Athlon X2 5050e

See attached. I'm not sure if I could predict the IDs for the 4050e/4450e/4850e - anyone know? I only have a 5050e. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator Add pretty name for AMD Athlon(tm) 64 X2 Dual Core Processor 5050e. Boot tested. S

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

ng up. I hope to get that ready soon so I can submit the patch to the list. >I am not confident it is 100% correct. I'll test tonight or tomorrow and let you know how it goes. Thanks! Ward. -- Ward Vandewege -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] SPI emulator

On Wed, Jul 15, 2009 at 05:07:23PM -0700, ron minnich wrote: > any comments on this one? > http://microcontrollershop.com/product_info.php?cPath=180&products_id=3406 Meh, requires Windows... Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator --

Re: [coreboot] What is the way to add a VGA ROM space in target\xx\xx\Config.lb

IG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). Leave 36k for VSA. option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024) So, CONFIG_ROM_SIZE is the place to do that. Thanks, Ward. -- Ward Vandewege Free Software Foundation -

Re: [coreboot] m57sli, seabios and gpxe - kernel booting issues (BUG: INT 14 etc)

On Tue, Jul 07, 2009 at 10:51:56PM -0400, Ward Vandewege wrote: > On Wed, Jul 08, 2009 at 12:53:02AM +0200, Peter Stuge wrote: > > Ward Vandewege wrote: > > > I'm trying to do a GPXE boot from seabios with coreboot on m57sli, > > .. > > > With 2.6.30, I g

Re: [coreboot] m57sli, seabios and gpxe - kernel booting issues (BUG: INT 14 etc)

On Wed, Jul 08, 2009 at 12:53:02AM +0200, Peter Stuge wrote: > Ward Vandewege wrote: > > I'm trying to do a GPXE boot from seabios with coreboot on m57sli, > .. > > With 2.6.30, I get absolutely nothing, the kernel just hangs > > without output. That's with the m

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