[coreboot] win10: Interrupt number is minus?

Maybe it is not a 100% suitable quesion. I assume big boys in coreboot know this. [cid:1fe4e7e2-ae0a-4631-8340-d284b41a2f9d] When I check the interrupt of network device in Windows 10, it says the IRQ is 0xFFDC(-36). I am confused about this minus. What does it mean? Is it MSI? Thanks.

[coreboot] How to delete another me?

Hi, admin of gerrit, I tried to add my working mail address zheng@amd.com to my gerrit account. But it says it is used by another account. I am pretty sure that is because I tried to use this mail address to create an account, but can not login by authorization.

[coreboot] Re: Linux kernel says "do_IRQ: 1.55 No irq handler for vector​"

PUT_POLARITY |​ + LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |​ + LAPIC_DELIVERY_MODE_MASK))​ + | (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING)​ + );​ +​ lapic_write_around(LAPIC_LVT1,​ (lapic_read_around(LAPIC_LVT1) &​ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |​ ________

[coreboot] Re: Linux kernel says "do_IRQ: 1.55 No irq handler for vector​"

From: Nico Huber Sent: Sunday, May 3, 2020 4:28 PM To: Zheng Bao ; coreboot Subject: Re: [coreboot] Linux kernel says "do_IRQ: 1.55 No irq handler for vector​" Hi Zheng, On 03.05.20 17:27, Zheng Bao wrote: > I am debugging the AMD Picasso board. When Linux kernel boots,

[coreboot] Linux kernel says "do_IRQ: 1.55 No irq handler for vector​"

Hi, All, I am debugging the AMD Picasso board. When Linux kernel boots, there is some error message in dmesg. do_IRQ: 1.55 No irq handler for vector​ The kernel can still boot. What does this message mean? Can I just ignore this message? Completed dmesg is attached. Zheng [0.032000] ...

Re: [coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode

Solved. Not know why. set IoapicSbFeatureEn=1. Zheng From: Rudolf Marek Sent: Friday, October 26, 2018 8:06 PM To: Zheng Bao; coreboot@coreboot.org Subject: Re: [coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode Hi

Re: [coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode

I tried AMI and it works. It seems that VxWorks does not use ACPI. Mptable and PCI interrupt Line instead. I copy all the mptable and PCI configuration space from AMI. Now SATA can work. But PCIe Networks Card can not work. Any more ideas? Thanks. Zheng From:

[coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode

Hi, all, I need to support VxWorks in Virtual Wire mode. The code is stable in coreboot.org for a long time which supports Windows and Linux. I add code to set the Interrupt Line in PciConfiguration space. What else needs to be done? Zheng -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] [skylake] Can not turn monitor on

rom github and extracted from original AMI BIOS. My board uses IT6515FN to transfer the display to VGA. Zheng From: Nico Huber Sent: Friday, October 5, 2018 8:27 PM To: Zheng Bao Cc: coreboot@coreboot.org; youness.ala...@puri.sm; Matt DeVillier Subject: Re:

Re: [coreboot] [skylake] Can not turn monitor on

To: Zheng Bao; coreboot@coreboot.org; youness.ala...@puri.sm Subject: Re: [coreboot] [skylake] Can not turn monitor on Hi Zheng, On 10/3/18 4:06 PM, Zheng Bao wrote: > I tried both the vgabios extracted in linux /sys/ and seavgabios. don't know why GOP+SeaVGABIOS fails but an Intel VBIOS extracted f

[coreboot] [skylake] Can not turn monitor on

Hi, All, I tried both the vgabios extracted in linux /sys/ and seavgabios. The coreboot and seabios are both latest. Neither way works. The debug message seems to be good, which is attached. Is there anything wrong? Zheng skl_cb1 Description: skl_cb1 -- coreboot mailing list:

Re: [coreboot] SATA init on FSP 2.0 for Skylake

I met the same problem. I use the FSP1.1 and the 0:17h:0 disappears after raminit. It seems that the FSP disable the SATA. The SATA device can be disabled if SCFD is set. But it can not re-enable. SATA Controller Function Disable (SCFD): BIOS program this bit to 1 to disable the SATA Controller

[coreboot] [Broadwell] Why does refcode disable EHCI

On my board with broadwell, the EHCI controller is disable after refcode runs. RCBA(FD) is 1. After refcode, RCBA(FD) is 0x8001. So I doubt the PEI data is not filled correctly. I change all ports like this. pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, //1,

[coreboot] how does FSP play its role in Haswell/Broadwell/Skylake

Hi, how does FSP play its role in Haswell/Broadwell/Skylake? Take the Broadwell as the example, which I ported coreboot successfully. I use the mrc.bin and vboot.bin from Chromebook BIOS image. I use the ME tool, fitc, to add the IFD to the BIOS image. The final image works well and boots

Re: [coreboot] [ haswell i7-4600] Why does accessing data in MCHBAR hang the boar?

I keep debugging and find out the MCHBAR+0x5400 - MCHBAR+0x7FFC can be accessed. The address below 0x5400 can cause hang. Zheng From: coreboot <coreboot-boun...@coreboot.org> on behalf of Zheng Bao <fishb...@hotmail.com> Sent: Monday, January 29

[coreboot] [ haswell i7-4600] Why does accessing data in MCHBAR hang the boar?

After the MRC.bin is loaded and run, the board hang at accessing data in MCHBAR32. If I move MCHBAR32 backward before the MRC.bin runs, it still hangs. It seems has nothing to do with MRC.bin, does it? /* For reference print the System Agent version * after executing the UEFI PEI

Re: [coreboot] [Haswell i7-4600U]: How can I decide which MRC.bin match my board

Plus, my board uses SODIMM, from which I assume System Agent should get SPD data. Is the grabbing data from SPD in blob? I can not dump the SPD out, can I? Zheng From: coreboot <coreboot-boun...@coreboot.org> on behalf of Zheng Bao <fishb...@ho

Re: [coreboot] [Haswell i7-4600U]: How can I decide which MRC.bin match my board

From: Nico Huber <nic...@gmx.de> Sent: Friday, January 26, 2018 2:15 PM To: Zheng Bao; Robert Reeves Cc: coreboot@coreboot.org Subject: Re: [coreboot] [Haswell i7-4600U]: How can I decide which MRC.bin match my board Hi Zheng, On 24.01.2018 16:12, Zhe

Re: [coreboot] [Haswell i7-4600U]: How can I decide which MRC.bin match my board

I just bought this board on internet. the cpu is Haswell i7-4600. That is all I know. Zheng From: Robert Reeves <xiin...@gmail.com> Sent: Wednesday, January 24, 2018 3:33 PM To: Zheng Bao Cc: coreboot@coreboot.org Subject: Re: [coreboot] [Haswell i7

Re: [coreboot] [Haswell i7-4600U]: How can I decide which MRC.bin match my board

Or, I can ask my quesion in another way. After extract the shellball of chromebook, how can I know what the processor exactly is? Zheng From: coreboot <coreboot-boun...@coreboot.org> on behalf of Zheng Bao <fishb...@hotmail.com> Sent: Wednesday

Re: [coreboot] [Haswell i7-4600U]: How can I decide which MRC.bin match my board

But it seems that ifdtool can only get ME, not MRC. Zheng From: Robert Reeves <xiin...@gmail.com> Sent: Wednesday, January 24, 2018 1:35 PM To: Zheng Bao Cc: coreboot@coreboot.org Subject: Re: [coreboot] [Haswell i7-4600U]: How can I decide which M

[coreboot] [Haswell i7-4600U]: How can I decide which MRC.bin match my board

Hi, All, The output of my board is attached below. The MRC.bin is extracted from panther, which I assume matches my board. But the meminit fails. Do all the haswell use the same MRC, or how can I decide which mrc.bin is the one I should extract? Thanks. Zheng coreboot-4.6-894-ga26344d-dirty

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

2017 6:51 PM To: Zheng Bao; coreboot@coreboot.org Subject: Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled? On 10.08.2017 16:36, Zheng Bao wrote: > Thanks. Your advice is quite helpful. > > > I got the BMP and BSF, created a vBIOS which enables the DDI2 as DP. The

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

<nic...@gmx.de> Sent: Wednesday, August 9, 2017 6:29 PM To: Zheng Bao; coreboot@coreboot.org Subject: Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled? On 08.08.2017 05:39, Zheng Bao wrote: > In text mode, > only one display can be enabled. > > > Can this

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

nable DDI1? Thanks. Zheng From: Nico Huber <nic...@gmx.de> Sent: Monday, August 7, 2017 9:32 AM To: Zheng Bao; coreboot@coreboot.org Subject: Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled? On 06.08.2017 05:18, Zheng Bao wrote: &g

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

turday, August 5, 2017 12:17 PM To: Zheng Bao; coreboot@coreboot.org Subject: Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled? Hi Zheng, On 04.08.2017 04:35, Zheng Bao wrote: > I need to clarify my question. > > For Broadwell-U, are there internal 3 display ports? Is th

Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

<coreboot-boun...@coreboot.org> on behalf of Zheng Bao <fishb...@hotmail.com> Sent: Wednesday, August 2, 2017 6:35 AM To: coreboot@coreboot.org Subject: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled? - # Enable eDP Hotplug with 6ms pulse

Re: [coreboot] Broadwell-U hangs at VGA init (update)

i just replace the bios region with my coreboot and other parts of ibv image untouched. is it a right way?what kinds of issue do you mean? 2017年8月2日 18:58于 Nico Huber <nico.hu...@secunet.com>写道： On 02.08.2017 04:23, Zheng Bao wrote: > src/soc/intel/broadwell/lpc.c > /* Init

[coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?

- # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" # Set

Re: [coreboot] Broadwell-U hangs at VGA init (update)

cpi_mode(); I need to skip all these 4 functions to run through, otherwise it hangs. What causes this? or what setting is not right? Zheng From: coreboot <coreboot-boun...@coreboot.org> on behalf of Zheng Bao <fishb...@hotmail.com> Sent: Tuesday,

Re: [coreboot] Broadwell-U hangs at VGA init (update)

lear requested zeroing cmos IOAPIC: Initializing IOAPIC at 0xfec0 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: Dumping registers reg 0x: 0x0200 reg 0x0001: 0x00170020 reg 0x0002: 0x Set power off after power failure.

Re: [coreboot] Broadwell-U hangs at VGA init

From: Nico Huber <nico.hu...@secunet.com> Sent: Monday, July 31, 2017 10:52 AM To: Zheng Bao; coreboot@coreboot.org; Matt DeVillier; stefan.reina...@coreboot.org Subject: Re: [coreboot] Broadwell-U hangs at VGA init Hi Zheng, On 30.07.2017 16:13, Zheng Bao wrote: > I

Re: [coreboot] Broadwell-U hangs at VGA init

Fix a typo. Accessing upper area (like 0xc4030) of VGA bar0 causes hanging. Accessing lower area (like 0xa00a) is OK. Zheng From: coreboot <coreboot-boun...@coreboot.org> on behalf of Zheng Bao <fishb...@hotmail.com> Sent: Sunday, July 30,

[coreboot] Broadwell-U hangs at VGA init

I have got the mrc.bin and mem init has got passed. Now the new problem is that it hangs at VGA init. static void igd_setup_panel(struct device *dev) { config_t *conf = dev->chip_info; u32 reg32; /* Setup Digital Port Hotplug */ reg32 = gtt_read(PCH_PORT_HOTPLUG); <--- It hangs here. if

[coreboot] How can we get MRC.bin for Intel platform.

Hi, All, I am debugging a i7-5650 board. I use IBV's BIOS to wrap the coreboot, i.e, replace the BIOS Region with coreboot.rom. So I assume the ME blob can work. I wonder if it is the right way. Is it fully supported by Coreboot? How can we get MRC.bin and other blobs? Thanks. Zheng

[coreboot] Is Xeon E5 supported?

Hi, All, We are evaluating a resolution, which requires more than four x8 PCIE lane. We assume Intel Xeon E5 can meet this requirement. I am not quite familar with Intel platform. I am wondering if coreboot supports Xeon E5. Thanks. Zheng -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Question about PCIe separate reference clock

Does it mean the "on mainboard" side it does not support "Asynchronous clock mode"? Zheng From: Predrag Vidic <pvi...@gmail.com> Sent: Friday, January 13, 2017 10:29 AM To: Zheng Bao Cc: Zoran Stojsavljevic; coreboot@coreboot.org Su

Re: [coreboot] Question about PCIe separate reference clock

Here is the ref clk part. Please review. No refclk routes to VPX connector. Thanks. Zheng From: Predrag Vidic <pvi...@gmail.com> Sent: Thursday, January 12, 2017 6:53 PM To: Zheng Bao Cc: Zoran Stojsavljevic; coreboot@coreboot.org Subject: Re: [co

Re: [coreboot] Question about PCIe separate reference clock

believe our board meet this requirement. So we doubt the problem lies in PCI configration space. Zheng From: Zoran Stojsavljevic <zoran.stojsavlje...@gmail.com> Sent: Thursday, January 12, 2017 9:22 AM To: Zheng Bao; Predrag Vidic Cc: coreboot@corebo

[coreboot] Question about PCIe separate reference clock

Our VPX design uses separate reference clock source, which is Si52111-B5 (No spread), instead of common ref clock from CPU. Now The system is unstable. Reading PCIE configuration space is unstable too. (If we add some fly wire to make it work with common ref clock, the system becomes stable.)

Re: [coreboot] Can boards wake up from S3/4/5 by specific keystroke

ping. Any idea? Zheng From: coreboot <coreboot-boun...@coreboot.org> on behalf of Zheng Bao <fishb...@hotmail.com> Sent: Thursday, August 25, 2016 11:05 AM To: coreboot@coreboot.org Subject: [coreboot] Can boards wake up from S3/4/5 by specif

[coreboot] Why my ACPI device conflicts with "PCI Bus"

Hi, All, I am debugging the UART device on Bettong(AMD Carrizo). The device " Device(FUR0) { Name(_HID,"AMD0020") Name(_UID,0x0) Name(_CRS, ResourceTemplate() { IRQ(Edge, ActiveHigh, Exclusive) {10} Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000) }) Method

[coreboot] MMIO UART driver on OS

Hi, All, I want to add support MMIO UART support on OS. I checked the file pnp_uart.asl. For IO UART, a device with EisaId("PNP0501") is added into DSDT, the windows can detect the COM port in device manager. I am wondering if MMIO UART also have that convinient feature. Or I need to build a

Re: [coreboot] How to protect binary in flash chip? OTP?

iques? > > On Fri May 6 08:45:51 2016 Zheng Bao > <fishb...@hotmail.com<mailto:fishb...@hotmail.com>> wrote: > > Hi, All, > > Is there any way to protect the binary image in flash chip from being > > copied? Once the customers gets the image, they can

[coreboot] How to protect binary in flash chip? OTP?

Hi, All, Is there any way to protect the binary image in flash chip from being copied? Once the customers gets the image, they can produce millions of board and do not tell me. I just want to know the amount of the mass production. OTP seems to be a way, but it is not 100%. The data in OTP is

[coreboot] Does ChromeOS-EC have to boot ChromeOS?

https://chromium.googlesource.com/chromiumos/platform/ec Hi, Stafan & All, I am trying to build a platform which uses AMD APU + EC. My goal is let EC 1. give the power sequencing logic to APU 2. play as a generic EC which has features like keyboard, UART. Currently, I don't have plan to boot

Re: [coreboot] Is windows driver for EHCI DEBUG available.

for Ajays - I may contribute back patches to read those from the descriptor at some point but it’s an easy modification to make manually. Regards,Chris. On 4 Apr 2016, at 13:00, Kyösti Mälkki <kyosti.mal...@gmail.com> wrote: -- Forwarded message -- From: Zheng Bao

[coreboot] building SPD: How to decide Trfc by spec

DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 unit 7-7-7 9-9-911-11-11 13-13-13 nRFC-1 Gb 59 74 88 103 nCK nRFC- 2 Gb 86

[coreboot] nvramcui: VGA console flashes if no serial console

Hi, all, I am trying to use the nvramcui. If the serial cable is plugged in, both the serial console and VGA console are stable. but if the serial cable is unplugged, the VGA console are flashing. The flashing part is the text inside the frame "Press F1 when done", i.e., the CMOS entries.

Re: [coreboot] Multiple payloads support?

innich <rminn...@gmail.com> wrote: it's a bit of work but I got it to build two years ago. ron On Sun, Mar 20, 2016 at 6:56 PM Zheng Bao <fishb...@hotmail.com> wrote: But Bayou seems to be dead. It can not be built. The definition like "struct LAR" goes nowhere. Zheng From:

Re: [coreboot] Multiple payloads support?

ds support? It was done about 10 years ago and it was called bayou. Take a look in the libpayload side. On Sat, Mar 19, 2016 at 11:30 PM Zheng Bao <fishb...@hotmail.com> wrote: Hi, all, I am trying to integrate SeaBIOS and another payload(coreinfo, nvramcui) into final image. After a qui

[coreboot] Multiple payloads support?

Hi, all, I am trying to integrate SeaBIOS and another payload(coreinfo, nvramcui) into final image. After a quick code checking, current code in repo does not support multiple payload, does it? I want to let Coreboot load and run nvramcui first. The user can decide to change the CMOS

[coreboot] Is windows driver for EHCI DEBUG available.

Hi, all, http://www.coreboot.org/DIY_EHCI_debug_dongle http://www.coreboot.org/EHCI_debug_dongle I want to build a EHCI debug dongle based on above links. I am wondering if the windows driver of the dongle is available. I google it but can not find it. I assume it is a generic driver. Who knows

Re: [coreboot] Incorrect time stamps on Olive Hill (was: Board status upload of AGESA board like ASUS F2A85-M)

of AGESA board like ASUS F2A85-M) CC: coreboot@coreboot.org Dear Zheng, Thank you very much! Am Sonntag, den 24.01.2016, 07:28 + schrieb Zheng Bao: > Hi, Paul, > I made a timestamp log by the following steps. > 1. Build coreboot with check "Create a table of timest

Re: [coreboot] Incorrect time stamps on Olive Hill (was: Board status upload of AGESA board like ASUS F2A85-M)

F2A85-M) CC: coreboot@coreboot.org Dear Zheng, Thank you very much! Am Sonntag, den 24.01.2016, 07:28 + schrieb Zheng Bao: > Hi, Paul, > I made a timestamp log by the following steps. > 1. Build coreboot with check "Create a table of timestamps collected > during boot &qu

Re: [coreboot] [RFH] Board status upload of AGESA board like ASUS F2A85-M (other than ASRock E350M1) (was: [regression] Increased romstage boot time on ASRock E350M1 (AMD Family 14h))

Hi, Paul, I made a timestamp log by the following steps. 1. Build coreboot with check "Create a table of timestamps collected during boot ". Run coreboot. 2. build cbmem on target machine. 3. run "cbmem -t" The log seems to be not enough. Is that what you want? If yes, I will do it with gcc 4.9

Re: [coreboot] [patch] AMD MCT DDR3 for register DIMMs

the testing report. Note: The pDCTstat-PresetmaxFreq in mctGet_MaxLoadFreq() should be set to a higher limit, otherwise the frequnce will be set as 400MHz. Signed-off-by: Zheng Bao zheng@amd.com Index: src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c

[coreboot] What is the rule of the SPD address assignment if there are more that 8 dimm slots?

The board tht I am working on has 2 process. Each of them has 6 DIMM slots. If you plug 1 dimm into each slot, the SPD address will be, Channel PCB P0: DIMMA0 50h DIMMA1 51h DIMMA2 52h DIMMB0 53h DIMMB1 54h DIMMB2 55h P1: DIMMA0 50h DIMMA1

[coreboot] [patch]remove sb600 legacy code

The device number of SATA SB700 is 0x11, while the one of SB600 is 0x12. We changed almost associated code when we ported but overlooked some. Some legacy of SB600 are also fixed. Signed-off-by: Zheng Bao zheng@amd.com Index: src/mainboard/amd/mahogany/dsdt.asl

Re: [coreboot] [patch] RE: Fam10 breakage

) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE); Removing the .stack construct makes no difference. I like the idea of minimizing the change. Sounds good, and should be stable (unless that's part of the bug Zheng Bao is experiencing). I'd say, commit this (as it fixes things for you). If it's

Re: [coreboot] Data in memory changes unexpectedly ininitialize_cpus

Date: Sat, 13 Feb 2010 11:23:49 -0700 Subject: Re: [coreboot] Data in memory changes unexpectedly ininitialize_cpus From: marcj...@gmail.com To: fishb...@hotmail.com CC: coreboot@coreboot.org 2010/2/12 Zheng Bao fishb...@hotmail.com: Date: Fri, 12 Feb 2010 16:54:43 -0700 From

Re: [coreboot] Data in memory changes unexpectedly ininitialize_cpus

Date: Fri, 12 Feb 2010 16:54:43 -0700 From: marcj...@gmail.com To: zheng@amd.com CC: coreboot@coreboot.org Subject: Re: [coreboot] Data in memory changes unexpectedly ininitialize_cpus On Fri, Feb 12, 2010 at 4:48 PM, Marc Jones marcj...@gmail.com wrote: On Thu, Feb 11, 2010 at

[coreboot] building error of family 10 code (in Kconfig)

It is just me, or anyone has the building error like this. I don't that error when I buildtarget. It only happens when I make menuconfig. /home/baozheng/x86/coreboot-org/src/cpu/amd/model_10xxx/fidvid.c:42: warning: 'print_debug_fv_64' defined but not used CC lib/cbfs.o

[coreboot] [PATCH] Kconfig of socket_AM2r2

Complete the Kconfig of socket_AM2r2. Signed-off-by: Zheng Bao zheng@amd.com Index: src/cpu/amd/socket_AM2r2/Kconfig === --- src/cpu/amd/socket_AM2r2/Kconfig (revision 4914) +++ src/cpu/amd/socket_AM2r2/Kconfig (working copy

[coreboot] The filo crashes if the filo and coreboot overlap.

The filo crashes if the filo and coreboot overlap. Since the CBFS is the must-have feature, my family 10 board crashes when it jumps to filo. I am trying to find out why. I need help. Based on current code, the AMD Family 10 will cause the filo and coreboot overlap in RAM. The

Re: [coreboot] CBFS failed to load vga rom

Have you added the vga rom into image by running ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci,.rom optionrom : vendor id : device id And Please provide the output of sh cbfstool coreboot.rom print Zheng Date: Thu, 22 Oct 2009 23:42:19 -0400 From:

[coreboot] Coreboot or UEFI, who will be the winner.

I got a brief UEFI introduction. It seems that it is pretty close to coreboot. They have same goal and face same problem. Any idea? Zheng _ Windows Live™: Keep your life in sync. Check

Re: [coreboot] AMD RS780 docs released, coreboot support coming

of this documentation release is flashrom support for all AMD chipsets which enables users to reflash their BIOS/firmware/coreboot from within Linux and *BSD without rebooting. Coreboot code for the SB700 and 780 chipset family is already being worked on by Zheng Bao at AMD in his spare time and the coreboot

Re: [coreboot] AMD RS780 docWs released, coreboot support coming

being worked on by Zheng Bao at AMD in his spare time and the coreboot community is happy to work with him on finishing and integrating the code into the official coreboot codebase. We'd like to thank Sharon Troia at AMD for making these documentation releases possible. The developer guides

Re: [coreboot] [PATCH] Fix AMD 690 HIGH_TABLES

I will have a vocation. I am gonna test next Thursday. Zheng Date: Fri, 5 Jun 2009 12:51:46 +0200 From: c-d.hailfinger.devel.2...@gmx.net To: coreboot@coreboot.org; zheng@amd.com Subject: [coreboot] [PATCH] Fix AMD 690 HIGH_TABLES Zheng, can you please test this with HIGH_TABLES

Re: [coreboot] [PATCH] Asus M2A-VM

Hi, Why the Socket S1G1 is changed to AM2? Joe Date: Mon, 6 Apr 2009 01:05:27 +0200 From: c-d.hailfinger.devel.2...@gmx.net To: coreboot@coreboot.org Subject: [coreboot] [PATCH] Asus M2A-VM This is the state of my v2 tree with Asus M2A-VM support. The patch is against the AMD

Re: [coreboot] 690/600 Just starting out.

When we did our dbm690t, we set up a SVN server in our own server, which everyday work was submit to. When we think the work is good enough, we send a patch to the community. That is a little complicated, but I believe it is a good way. Currently the SuperIO is not only configured in