[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Thank you so much Javier Galindo! Sorry for not finding this case myself ... I checked it on the motherboard with lapic #4 - everything works as it should. Tomorrow I'll check it on the motherboard with lapic #0. I wish I could understand how this magic works :)! lapic 0xbeef . Thanks

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Thank you so much Javier Galindo! Sorry for not finding this case myself ... I checked it on the motherboard with lapic #4 - everything works as it should. Tomorrow I'll check it on the motherboard with lapic #0. I wish I could understand how this magic works :)! lapic 0xbeef . Thanks

[coreboot] A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Hi! We developed our CRB motherboard on Intel Atom C3538 (4 core) Denverton_NS processor. Faced with the following problem. For part of processors with the same SKU and steping (Atom C3538), lapic #4 in devicetree.cb needed (95%), and for the other part lapic #0 (5%). Intel confirmed that it

[coreboot] Updating the BIOS from the OS on a custom motherboard (Intel Atom С3538 Denverton_ns).

Hi! I can’t update the BIOS on our custom motherboard (Intel Atom С3538 Denverton_ns SOC) when using a bunch of coreboot + siabios. (When processing BIOS, the Intel Hurcuvar motherboard is taken as a source). The BIOS chip is located on the SPI bus. The BIOS chip size is 16 megabytes. I need to

[coreboot] Re: Decryption of post codes that appear during Intel FSP operation?

Thank you all, I found the necessary information in the document: Aspen Cove Customer Reference Board (CRB) User Guide March 2016 Document Number: 566111, Revision: 1.0 ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to

[coreboot] Re: Decryption of post codes that appear during Intel FSP operation?

Hi Wim Vervoorn I use FSP 2.0 for denverton_ns. Unfortunately in the directory for this processor the documentation does not contain information on post codes Regards, Dmitry ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an

[coreboot] Re: Decryption of post codes that appear during Intel FSP operation?

I use FSP version 2.0 for Intel Denverton_ns. Unfortunately in the directory for this processor the documentation does not contain information on post codes... ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to

[coreboot] Decryption of post codes that appear during Intel FSP operation?

Hi! Please tell me where I can get the decryption of post codes that appear during Intel FSP operation? Codes such as 0x57, 0x59, 0x58, 0x62 ... I see that they appear during testing and memory tuning, but I would like to have more detailed information. Maybe someone knows the number of the

[coreboot] Re: How to access the PCIE device registers at an early stage of coreboot booting?

Wow, thanks! At first glance, it looks like what I need ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] How to access the PCIE device registers at an early stage of coreboot booting?

Hello to all! Need quick help! I am poorly versed in the question so detailed answers are welcome :) ! As a result of the motherboard developers laziness the hard straps for ASPEED AST2510 chip were not properly prescribed. Now I need to write register 0x1e6e2070 with necessary bits [5][15]

[coreboot] Atom C2000 processor FSP 1.0 initialization process fail if read SMBus0 before.

Motherboard based on the Intel Rangeley Atom C2000 (C2758) processor. On the board installed Nuvoton NCT6776F/D superIO. For its correct operation, a frequency of 48 MHz is necessary, which must be enabled by write some bits in IDT clock synthesizer (9VRS4420DKLFT). The configuration of the

[coreboot] Re: How to enable the SMBus0 in coreboot for Intel Atom C2000?

Yes, most likely you are right! I could not completely fix the problem but was able to get around it. The problem arose when connecting an external video card to an PCI-E slot through riser. Without connecting the video card the SMBus0 (i2c-1 bus) works fine. I was able to experiments with IDT

[coreboot] How to enable the SMBus0 in coreboot for Intel Atom C2000?

There is motherboard based on the Intel Rangeley Atom C2000 (C2758) series processor. How to enable the SMBus0 in coreboot? If I use OEM BIOS or BIOS from Intel (EDVLCRB1.86B.0048.R00.1508181657_MPK) for mohon peak crb, then I see on the SMBus0 (i2c-1 in Fedora 28) memory DIMM spd (0x50 &

[coreboot] How to add NUVOTON NCT6776F support with serial port logic enabled ???

There is a Lanner FW-7573 platform based on the Intel Rangeley Atom C2000 series processor. To work with the Serial port in this platform, the NUVOTON NCT6776F chip is connected via the LPC bus to the processor. I just can’t get Serial port working for debuging. I take as a basis intel

[coreboot] Coreboot hangs with post code 0x75. How to describe the PCIe Switch (Asmedia ASM1182e) and devices connected after it for devicetree.cb?

I'm trying to develop a coreboot+seabios for motherboard MB-7573 by LANNER, CPU Intel(R) Atom(TM) CPU C2758. PCI root port 4 configured as x4. PCIe Switch (Asmedia ASM1182e) connected to root port 4. Two more devices are connected to ASM1182e - Xillinx network device and RDC C6139(PCI bridge &

[coreboot] Re: Intel sVID controller and SVID bus.

The reason for the poor performance was not working SVID bus. Understand exactly what settings affect the enabling/disabling SVID bus failed to find out. The problem was solved by choosing another platform in spsFITs (Aspen Cove instead of Harcuvar). After that, the SVID bus started to work, we

[coreboot] Re: Atom Denverton processor and memory are very slow.

The reason for the poor performance was not working SVID bus. Understand exactly what settings affect the enabling/disabling SVID bus failed to find out. The problem was solved by choosing another platform in spsFITs (Aspen Cove instead of Harcuvar). After that, the SVID bus started to work, we

[coreboot] Intel sVID controller and SVID bus.

On the motherboard developed by our company (intel atom denverton 3538), there is a low performance of the processor and memory. When trying to monitor the exchange of the SVID bus lines with the oscilloscope (SVID_CLK, SVID_DATA and SVID_ALERT), no activity was noticed. Circuit design is

[coreboot] Coreboot hangs with post code 0x26 - Infinit loop in cache_as_ram.S (Intel Atom denverton_ns)

Motherboard with Intel Atom Denverton C3538 Stepping B1 processor. I configured Intel FSP (FSP_M and FSP_S, FSP_T did not use - is it needed at all?). Integrate FSP_M & FSP_S to coreboot 4.9 (intel/harcuvar or Scaleway/tagada same behavior). I copied the header files from the FSP package to the