If people are trying native graphics init I still think it's worth trying
the SPARK stuff from nico at least once.
It seems more complete to me than teh stuff I started.
On Thu, Dec 1, 2016 at 2:54 PM Klemens Nanni wrote:
> On Thu, Dec 01, 2016 at 11:35:36AM -0700, Trammell Hudson wrote:
> >The
what's the latest best one? What's the battery life like (can't be worse
than this mac pro that's always hot and now seems to have a life of 90
minutes, always). How much dram/ssd can I jam in it?
thanks
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/co
Apologies in advance: this is not a coreboot question but I'm counting on
coreboot expertise.
I need to find a way to force the value of the segment alignment variable.
The problem is that on the riscv gld, they want to align segments on 4k
boundaries. I need them aligned on 2M boundaries. Note t
OK, then someone just asked me: how long does it take to rewrite that 128
MiB vs. the 512 byte sector on the floppy. :-)
On Wed, Nov 30, 2016 at 1:18 PM ron minnich wrote:
> amusement value:
>
> The 512 bytes used for MBR is about .04% of the 8" floppy disk that
> shipped with
amusement value:
The 512 bytes used for MBR is about .04% of the 8" floppy disk that shipped
with the original IBM PC. For 128 MB to be that fraction of a new disk, the
disk would have to be 256 GiB. That's about $40 worth of disk.
Geez.
On Wed, Nov 30, 2016 at 11:00 AM Zoran Stojsavljevic <
zo
hey, peter, code wins :-) go for it
On Wed, Nov 30, 2016 at 10:08 AM Peter Stuge wrote:
> Julius Werner wrote:
> > If you really can't stand the idea of BIOS interrupts and real mode,
>
> I for one can't.
>
>
> > I think your next best option would be to try to cram an
> > as-small-as-possible b
"Oflags": [
"-static"
],
"Post": [
"rm -f *.o"
],
"Pre": [
"rm -f *.o *.tag.*"
]
}
}
On Mon, Nov 28, 2016 at 1:15 PM David Hendricks via coreboot <
coreboot@coreboot.org> wrote:
> On Mon, Nov 28, 2016 at 12:40 PM, Peter Stuge wrote:
On Sun, Nov 27, 2016 at 5:58 PM Charlotte Plusplus <
pluspluscharlo...@gmail.com> wrote:
> I don't know about you, but once I have a minimal working kernel or a
> coreboot fallback, I never really update them. So having no way to recover
> them without hardware intervention is fine. The kernel I m
configure/what to download/how to
validate (we have a gpgv command written in Go by
Eric Grosse) and then how to kexec it.
I think what we're doing might be useful?
ron
On Sun, Nov 27, 2016 at 6:04 PM David Hendricks
wrote:
> On Sat, Nov 26, 2016 at 2:46 PM, ron minnich wrote:
>
On Sun, Nov 27, 2016 at 4:22 PM Charlotte Plusplus <
pluspluscharlo...@gmail.com> wrote:
>
>
> In my ideal scenario, coreboot would have the 2 images (normal, fallback)
> both starting the same payload (a minimal linux kernel) to save space.
>
at Los Alamos we found we wanted a fallback kernel an
Seems reasonable, but on Harvey recently we went with c11. Any reason not
to do that instead?
On Sun, Nov 27, 2016 at 2:09 PM Paul Menzel via coreboot <
coreboot@coreboot.org> wrote:
> Dear coreboot folks,
>
>
> Using GCC 4.9.2 coreboot fails to build for certain boards, whose code
> uses ‘for’ l
On Sun, Nov 27, 2016 at 1:03 AM Zoran Stojsavljevic <
zoran.stojsavlje...@gmail.com> wrote:
>
> I'll again repeat what I always believe in, and always advertise(d) here,
> and anywhere else: Coreboot is one excellent absolute minimum required for
> booting HW platform to the next step: OS boot loa
:
>
> * HEADS - https://github.com/osresearch/heads
>
> * Petitboot - https://secure.raptorengineering.com/content/kb/1.html
>
> I am currently working on the UI of Heads. So feel free to contribute ;)
>
>
> Best Regards
>
> Zaolin
>
> On 11/26/2016 11:47 PM, ron minnic
coreboot today is linuxbios minus the linux. The original intent was always
that linux be our lifeboat. The current set of (as you point out) not
terrific options is a result of linux growing too big for flash, and flash
growing too big for linux, ca. 2002, when we adopted the payload model. The
or
Oh, my fingers type too much for me now.
The current set of (as you point out) not terrific options is a result of
linux growing too big for flash, and flash growing too SMALL for linux, ca.
2002, when we adopted the payload model.
On Sat, Nov 26, 2016 at 3:46 PM ron minnich wrote:
> coreb
we've seen.
Keep me posted on anything you need.
Thanks
ron
On Thu, Nov 24, 2016 at 12:01 PM Nico Huber wrote:
> Hi,
>
> On 20.11.2016 21:29, ron minnich wrote:
> > I also wonder if you could use the code Nico put in for the graphics
> init.
> > I have no idea if
On Mon, Nov 21, 2016 at 10:54 AM Rudolf Marek wrote:
>
>
> BME is ignored by Intel integrated graphics - the DMA runs even if the BME
> is
> clear (this happens on core i7 chipsets for example) Thus thatswhy it
> needs RMRR
> IOMMU range for VGA...
>
>
wow. It's amazing how many of the PCI viola
On Mon, Nov 21, 2016 at 9:21 AM Timothy Pearson <
tpear...@raptorengineering.com> wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 11/21/2016 10:43 AM, ron minnich wrote:
> > Talidan, just be aware, you can spend the money on enabling IOMMU in
> > cor
Talidan, just be aware, you can spend the money on enabling IOMMU in
coreboot, but you should not just assumed that it gets upstreamed.
Enabling IOMMU on one implementation of one CPU from one vendor for one
generation is not a really compelling idea, at least for me.
You don't want to confuse yo
On Mon, Nov 21, 2016 at 7:53 AM Timothy Pearson <
tpear...@raptorengineering.com> wrote:
>
>
> A quick check through the source seems to indicate that the generic
> pci_set_resource function will enable bus mastering on any PCI bridges.
> From that point on, if I'm not mistaken, any malicious dev
On Sun, Nov 20, 2016 at 3:49 PM Kyösti Mälkki
wrote:
> On Mon, Nov 21, 2016 at 1:36 AM, ron minnich wrote:
>
> The way coreboot has always enforced DMA protections is to not set bus
> master enabling on IO devices. I trust that particular setting a lot more
> than I trust trying
print a warning for each one found?
On Sun, Nov 20, 2016 at 3:52 PM ron minnich wrote:
> On Sun, Nov 20, 2016 at 3:49 PM Kyösti Mälkki
> wrote:
>
> On Mon, Nov 21, 2016 at 1:36 AM, ron minnich wrote:
>
> The way coreboot has always enforced DMA protections is to not set bus
The way coreboot has always enforced DMA protections is to not set bus
master enabling on IO devices. I trust that particular setting a lot more
than I trust trying to configure an IOMMU, given that such configuration
seems to require trying to parse ACPI DMAR tables. If you will now tell me
that s
On Sun, Nov 20, 2016 at 4:36 PM, ron minnich wrote:
>
>
>
> On Sun, Nov 20, 2016 at 1:00 PM Matt DeVillier
> wrote:
>
> On Sun, Nov 20, 2016 at 2:51 PM, ron minnich wrote:
>
> I had the same thought even while writing that note. So option 2 for the
> config file is to c
On Sun, Nov 20, 2016 at 1:00 PM Matt DeVillier
wrote:
> On Sun, Nov 20, 2016 at 2:51 PM, ron minnich wrote:
>
> I had the same thought even while writing that note. So option 2 for the
> config file is to create it at the top level: config.${MAINBOARD) or
> somewhere else.
On Sun, Nov 20, 2016 at 12:45 PM Trammell Hudson wrote:
> On Sun, Nov 20, 2016 at 08:20:51PM +0000, ron minnich wrote:
> > [...]
> > There's also no fundamental reason for using the name .config other than
> > tradition. We could, for example, create
> > build
I'm working from memory here, I wrote this code over 4 years ago, but I did
find out there's lots of ways to get a dark panel or other issues you
mention. And it's very hard sometimes to get it all right. It's also easy
to have it almost working with parameters that are so wrong that getting
back t
A little word of caution: seeing a problem with coreboot and a given
distro has proven, in the past, to not always be a coreboot problem. I'd
say it more frequently uncovers a kernel problem than a coreboot problem,
but I have only my limited memory and no statistics.
On Sun, Nov 20, 2016 at 11:
I think the build system could stand some cleanup so that external build
would not be needed and building many mainboards in one tree would be easy.
LinuxBIOS V1 allowed you to build any number of mainboards in one source
tree -- it was initially modeled on the BSD
build system. objects were place
Neat! This was the original linuxbios model from 1999: kernel + minimal
initramfs in flash, so it's nice to see it coming back.
I've got something similar too, save the userland is not petitboot (I no
longer want to use C for user mode code) but Go. It's also bigger than I'd
like (about the size o
On Wed, Oct 19, 2016 at 5:53 PM ron minnich wrote:
> On Wed, Oct 19, 2016 at 4:50 PM Riko Ho wrote:
>
> Ok, it means, I need to use microcode for LGA775 otherwise it will not
> work, please correct me ?
>
>
> I can't honestly say. I talked to an expert about this yeste
On Wed, Oct 19, 2016 at 4:50 PM Riko Ho wrote:
> Ok, it means, I need to use microcode for LGA775 otherwise it will not
> work, please correct me ?
>
>
I can't honestly say. I talked to an expert about this yesterday and
pointed out that early sandybridge required the microcode update to work at
On Wed, Oct 19, 2016 at 9:36 AM Vasilief wrote:
> On 10/18/2016 10:31 AM, Stefan Reinauer wrote:
> > * Riko Ho [161017 02:18]:
> >> Is it ok if I'm not including microcode updates ?
> >
> > It might, or might not. On the i945/946 it probably is ok. A lot of
> > modern CPUs can't boot successfull
See you there! I just registered and am really looking forward to seeing
everyone! Thanks Peter!
ron
On Fri, Sep 30, 2016 at 9:41 AM Peter Stuge wrote:
> Hello all,
>
> I'm happy to *finally* have the information and registration page online:
>
> https://coreboot.berlin/
>
>
> Yes, it's very la
I'd lke to track some things I'm learning about linux paylaod on kgpe-d16
I'm thinking of keep track of
working linux ref and a working .config
working coreboot ref and a working .config
I'm not quite sure where in the wiki this belongs; ideas anyone?
reon
--
coreboot mailing list: coreboot@cor
things got better with the CL I submitted yesterday, but further on in 4.x
more things break on the KGPE-D16
I'll keep you posted. 4.x has been very painful so far.
ron
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
p stage as needed.
You only need the cpp hack once as you want to switch to the transformed
output.
Not pretty, but maybe ACPI is so simple that it would work.
ron
On Tue, Sep 20, 2016 at 12:11 PM ron minnich wrote:
> It would be nice if there were a source to source transformation tool ou
It would be nice if there were a source to source transformation tool out
there but failing that RPN to infix is pretty simple to automate.
ron
On Tue, Sep 20, 2016 at 12:03 PM Duncan Laurie wrote:
> So far I've been asking people in ACPI patches to not introduce ASL 2.0
> syntax into existing
This is fantastic!
I hope you can write this up for the coreboot wiki ...
ron
On Thu, Sep 15, 2016 at 12:24 PM Trammell Hudson wrote:
> On Mon, Sep 12, 2016 at 09:27:18PM +, Peter Stuge wrote:
> > Trammell Hudson wrote:
> > > I've experimented with clearing additional bits, from 0x3000 to
oline code from the bzimage. I'll try that.
ron
On Tue, Sep 13, 2016 at 4:43 PM ron minnich wrote:
> I've been trying to find a problem in linux that makes it not boot when
> used as the payload in the KGPE-D16. The symptom is that I get no output at
> all on serial when linux
I've been trying to find a problem in linux that makes it not boot when
used as the payload in the KGPE-D16. The symptom is that I get no output at
all on serial when linux starts.
I finally got it down to 1 commit today in linux.
commit 974f221c84b05b1dc2f5ea50dc16d2a9d1e95eda
Author: Yinghai Lu
I was thinking that the x230 was so old it would just keep running, is that
possible? I know that on newer platforms you only get the 30 minutes.
ron
On Mon, Sep 12, 2016 at 10:28 AM Peter Stuge wrote:
> ron minnich wrote:
> > That's pretty interesting. I had no idea that would w
That's pretty interesting. I had no idea that would work.
I wonder if erasing it all erases that little boot of the ME you need to
get the hardware going, whereas the 4KB erase lets the little bootstrap run
but disables the ME otherwise. If so, that's great news.
ron
On Mon, Sep 12, 2016 at 8:43
>
>
>
>
>
>
> On Thu, Sep 8, 2016 at 8:12 AM, Zoran Stojsavljevic <
> zoran.stojsavlje...@gmail.com> wrote:
>
>> There is always "better" per say, whatever does it mean!? ;-)
>>
>> Am I right (I am too old to play it on first, second... N-
It's wonderful.
For fun, I found this, which is *not* the first one, but close.
https://web.archive.org/web/2819124055/http://www.acl.lanl.gov/linuxbios/index.html
On Wed, Sep 7, 2016 at 5:51 PM Stefan Reinauer
wrote:
> Hi!
>
> As some of you might already have noticed, our new web presen
I wonder if it's the bad problem I'm see with BAR allocation in linux? I
can't get my in-flash linux to boot and function if it's 4.x.
ron
On Wed, Aug 24, 2016 at 12:44 PM Timothy Pearson <
tpear...@raptorengineering.com> wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 08/24/2016
gt;
>
> On Wed, Aug 10, 2016 at 5:01 PM, ron minnich wrote:
> > oh, thanks, Marshall, for some reason I confused FS2 and HDT.
> >
> > darn. Well, if nobody wants this thing ... into the black hole with it.
> >
> > ron
> >
> > --
> > coreboot
oh, thanks, Marshall, for some reason I confused FS2 and HDT.
darn. Well, if nobody wants this thing ... into the black hole with it.
ron
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coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
Thanks Nico that's it. It's a nice debugger for opterons.
If somebody wants it let me know and I'll bring it to berlin.
ron
On Wed, Aug 10, 2016 at 3:08 AM Nico Huber wrote:
> On 10.08.2016 10:35, ron minnich wrote:
> > ah, no, those are not it. Sorry. I'll get
On Wed, Aug 10, 2016 at 3:34 AM Zoran Stojsavljevic <
zoran.stojsavlje...@gmail.com> wrote:
>
> > Basically, in the classic car we got in 2005, the steps on x86 are:
> > enable cache
> *> do references to set tags*
> > disable cache (really!)
> > then cache as ram works.
>
> I am interested how th
tel-Pentium-Dual-Core-Processor.14045.0.html
>
> Zoran
>
> On Tue, Aug 9, 2016 at 3:30 PM, Jonathan Neuschäfer > wrote:
>
>> On Sat, Aug 06, 2016 at 10:39:48PM +, ron minnich wrote:
>> > I have an FS2 if someone can use it. I may have mentioned this before. I
&
I have an FS2 if someone can use it. I may have mentioned this before. I
can bring it to berlin with me if you will be at the meeting.
ron
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https://www.coreboot.org/mailman/listinfo/coreboot
That's quite neat ...
ron
On Thu, Aug 4, 2016 at 5:12 AM Łukasz Dobrowolski
wrote:
> I discovered that ITE often uses 8032 in their EC's. Those start from
> address 0.
> After some changing cbfs size in menuconfig and playing a bit with dd
> i was able to get the board to turn on and display po
"ASUS AM1I-A is an AM1 Socket-based Mini-ITX motherboard. It has an
intuitive UEFI BIOS "
er, what? What's the word intuitive mean again?
ron
--
coreboot mailing list: coreboot@coreboot.org
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Ah well, Werner, I've had the error of my ways pointed out to me, turns out
this packed stuff is a standard practice in coreboot now. I must have
missed the memo. So, I'm not a fan but if that's how we do it, it's how we
do it.
thanks and apologies
ron
On Wed, Jul 27,
On Tue, Jul 26, 2016 at 9:25 PM Zeh, Werner wrote:
>
>
>
> In the case of ACPI we need to provide a table which has constrains on the
> used data types and alignment
> as the contents of the table will be interpreted by the ACPI interpreter
> of the OS.
> So if we omit the usage of packed it may
> from memory into an unpacked struct? That's how ACPICA seems to do it.
>
> Because in most cases, it is not data, but register space we are
> accessing.
>
> Are you suggesting to learn our coding style from ACPI? Who are you and
> what did you do to Ron Minnich? ;)
>
A couple of questions preceded by the usual curmudgeonly comment :-)
I'm not a big fan of checkpatch.pl. It's 5965 lines of dense perl spaghetti
code, continues to grow, and is attempting to achieve that which I
understand may be impossible: parsing C with REs and random blobs of PERL.
Given that
This is just weird. I can easily load a 3.18 kernel and boot it from flash.
4.6.4 with your config won't work at all.
Could you put your kernel somewhere I can try it out? I'm starting to worry
about my toolchain.
Also, do you use the bzimage or vmlinux? I would prefer to use the vmlinux
but hav
On Sun, Jul 24, 2016 at 11:32 AM Trammell Hudson wrote:
>
> The Qubes kernel is the Xen hypervisor and is only about 800 KB.
> I'm attempting to add it as the payload, although I think that a minimal
> Linux in ROM that kexec's Xen from an encrypted and measured disk image
> will be better suited
I"m assuming this is native graphics? That's sometimes a sign that the
graphics hardware can't get to memory for an image, either due to the page
remapping on the graphics hardware being wrong or maybe BME is not set on
the device.
Or, it could be something as simple as the memory it's pointing to
I have a kgpe-d16 with coreboot and it *was* working with linux. I now have
a linux kernel that won't boot on fuctory bios or coreboot. I can't recall
changing anything ...
If somebody's got a known good .config for linux I could sure use it. I'm
booting stock tinycore and it seems to hang a lot.
I'm bringing an x230 to the conference next week in hopes that someone can
help me flash it ... I've failed every time so far.
And, I'll have a bunch of gear at the swap table, so if you flash the x230,
you can take your pick of it :-)
ron
--
coreboot mailing list: coreboot@coreboot.org
https://
On Tue, Jun 7, 2016 at 7:40 AM Patrick Rudolph wrote:
>
>
> I've read this serveral times and wonder how a stored variable could get
> damaged ?
> There is a checksum to verify the mrc cache. How should anything go
> wrong ?
>
>
oh boy. "how should anything go wrong" ... :-)
What I wonder, every
On Mon, Jun 6, 2016 at 12:52 PM Patrick Rudolph wrote:
> To summarize:
> The easy way is to use 2G.
> The preferred way would be to mimic mrc behaviour and reboot after
> finding the correct size.
>
>
>
I'm not sure it's "easy vs. preferred" so much as
- simple that has no known failure cases (ye
I'm getting the sense here that reasonably modern CPUs can easily handle
the 2G hole. From what I've seen, it would not cause trouble for older CPUs
because they're most likely to be in small systems that are not likely to
have more than 2G memory anyway (I'm thinking of the vortex).
The 2G hole s
Another Kconfig option? How many people will really understand what it
means and whether to use it?
Has just reserving 2 GiB as a hard and fast rule hurt anyone yet?
thanks
ron
On Fri, Jun 3, 2016 at 11:25 PM Patrick Rudolph wrote:
> On 2016-06-03 05:41 PM, Aaron Durbin via coreboot wrote:
>
oh. wait.
is that me?
ron
On Mon, May 16, 2016 at 4:39 PM ron minnich wrote:
> There's no way this can work.
>
>
>
> On Mon, May 16, 2016 at 4:32 PM Stefan Reinauer <
> stefan.reina...@coreboot.org> wrote:
>
>> Hello coreboot folks,
>>
>> I&
There's no way this can work.
On Mon, May 16, 2016 at 4:32 PM Stefan Reinauer <
stefan.reina...@coreboot.org> wrote:
> Hello coreboot folks,
>
> I've played around with gerrit's avatar feature this weekend and as
> a little gimmick, I have turned on avatars for our gerrit instance at
> https://
H means hex, they do that instead of 0x.
2 is footnote 2.
The whole H thing goes back 45 years or so and was a failure of vision, AH
is a register name and a constant. As are bc, ch, and dh. oops.
ron
On Mon, May 9, 2016 at 8:19 AM Rafael Machado <
rafaelrodrigues.mach...@gmail.com> wrote:
> Hi
On Thu, May 5, 2016 at 7:54 PM Persmule wrote:
> Don't you feel ashamed to ask coreboot, a free firmware project, for copy
> protection techiques?
>
>
>
>
Zheng Bao has nothing to be ashamed of, he made at least 187 commits to
coreboot from 2008 to 2015 -- and they were not simple ones by any mea
FWIW RISCV is looking at this issue and I've talked to them about just
using text-based tables. Since the kernel always has to interpret the table
anyway there's no real advantage to binary formats.
We've even discussed using text protobufs.
ron
--
coreboot mailing list: coreboot@coreboot.org
ht
I tend to vote for CORE, I think it is really going to be clear to people
what it's for
I like CRBT but fear it gets lost in the plethora of ACPI alphabet soup.
ron
On Fri, Apr 22, 2016 at 2:40 PM Aaron Durbin wrote:
> On Fri, Apr 22, 2016 at 2:38 PM, ron minnich wrote:
>
Wait, I thought it had to be 4 characters.
ron
On Fri, Apr 22, 2016 at 2:36 PM Aaron Durbin via coreboot <
coreboot@coreboot.org> wrote:
> On Fri, Apr 22, 2016 at 2:00 PM, Duncan Laurie
> wrote:
> > On Tue, Apr 19, 2016 at 6:49 AM, Aaron Durbin
> wrote:
> >>
> >> On Mon, Apr 18, 2016 at 10:17
On Wed, Apr 20, 2016 at 10:21 AM Jonathan Neuschäfer
wrote:
>
> I can get coreboot to boot in QEMU up to the "payload not loaded"
> message with a few patches:
> - I patched QEMU to not trap unaligned memory accesses
>
we're supposed to handle these traps, so something is broken. I would only
t
Yes, it does.
On Tue, Apr 19, 2016, 11:59 AM Yang, York wrote:
> Just want to confirm, will whole event happen in Google SF office?
>
>
>
> Thanks,
>
> York
>
>
>
> *From:* coreboot [mailto:coreboot-boun...@coreboot.org] *On Behalf Of *ron
> minnich
> *
The coreboot convention is coming along very well. Just today we've been
able to schedule a talk which I think you are going to enjoy: Ms. Joanna
Rutkowska of the Invisible Things Lab, and one of the inventors of Qubes,
will be presenting her ideas on the Stateless Laptop on Monday, June 13.
Put si
yeah, I know ... :-)
I just wanted to get the full word in there
ron
On Mon, Apr 18, 2016 at 6:22 PM Aaron Durbin wrote:
> On Mon, Apr 18, 2016 at 8:18 PM, ron minnich wrote:
> > So we would submit new ACPI table types to the standards guys? Could we
> get
> > n
So we would submit new ACPI table types to the standards guys? Could we get
names like
CORE
BOOT
CBFS
?
ron
On Mon, Apr 18, 2016 at 10:15 AM Patrick Georgi via coreboot <
coreboot@coreboot.org> wrote:
> 2016-04-18 19:09 GMT+02:00 Vadim Bendebury :
> > It's been a while since I looked at it, but
This is a reminder about some details of the upcoming coreboot convention.
Early registration ends May 15, and registration costs will be higher past
that date.
We've been working hard to find a block of hotel rooms but at the moment
the best bet is to find and book your own; I've found about 50
On Sat, Apr 9, 2016 at 11:49 AM Vadim Bendebury
wrote:
> Wow, looks like it was an excellent talk, thank you for sharing the slides!
>
> Should we expect an influx of contributions from China now? :)
>
>
>
but seriously :-)
from the very beginning, we've had great contributions from China. Th
I use initramfs and it works wondefully well. Figures, Patrick Georgi did
that code :-)
ron
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On Fri, Mar 25, 2016 at 9:34 AM Jonathan Neuschäfer
wrote:
>
>
> I've discussed this some more with Ron, and it will be an untethered
> lowRISC[1] ("untethered" meaning that it doesn't use the Host-Target
> Interface which is a bridge and abstraction layer for I/O) on a Nexys 4
> board by Diligen
Actually, this seems a pretty good proposal in its current state, but not
my one comment.
thanks
ron
On Wed, Mar 23, 2016 at 12:14 PM ron minnich wrote:
> Thanks, now I understand, and I will try to get to this tonight. Sorry to
> be causing your worries.
>
> ron
>
> On We
forget. I'll be patient
>
> 2016-03-23 20:55 GMT+02:00 ron minnich :
>
>> you need to be patient. All the reviewers have day jobs and there is a
>> lot of work in all this.
>>
>> There's no advantage to you or your proposal in complaining about the
&
me time, please :-)
>>>> Thanks in advance
>>>>
>>>> 2016-03-14 23:11 GMT+02:00 Yurii Shevtsov :
>>>>
>>>>> I know we haven't discussed project properly yet, and I understand my
>>>>> vision of project may vary from
it's a bit of work but I got it to build two years ago.
ron
On Sun, Mar 20, 2016 at 6:56 PM Zheng Bao wrote:
> But Bayou seems to be dead. It can not be built. The definition like
> "struct LAR" goes nowhere.
>
>
> Zheng
> --
> From: rminn...@gmail.com
> Date: Sun, 2
It was done about 10 years ago and it was called bayou. Take a look in the
libpayload side.
On Sat, Mar 19, 2016 at 11:30 PM Zheng Bao wrote:
> Hi, all,
> I am trying to integrate SeaBIOS and another payload(coreinfo, nvramcui)
> into final image.
>
> After a quick code checking, current code in
On Thu, Mar 17, 2016 at 2:33 PM Yurii Shevtsov wrote:
>
> I can't see any other way, it's all about running the commands. Browsers
> can't do this. Certain actions are still required from user. Some shell
> script, which will run commands and then send stdout to the server, can be
> developed tho
On Thu, Mar 17, 2016 at 1:08 PM Denis 'GNUtoo' Carikli
wrote:
>
> Once we get reproducible builds, we could:
> 1) Store an (SHA) hash of images in board-status.
> 2) Make the rom-o-matic build (with the board-status configs) and
>verify(checksums) the image of a known good state.
>
>
>
I rea
way :-)
>> Here is the link:
>>
>> https://docs.google.com/document/d/1OWOYfKMUSZTi4tTHmGIIY27KAbM5MJVV0DdirjpB2As/edit?usp=sharing
>>
>> I made my proposal draft private. As for now I shared it with Ron Minnich
>> and Martin Roth. If you part of a GSoC commission, I&#
On Thu, Mar 17, 2016 at 1:30 PM Yurii Shevtsov wrote:
>
>
>>
> I like it too. Maybe we can ask users on rom-o-matic to provide neccesary
> info for further project improvement
>
no, it has to be automated or it won't work.
ron
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboo
On Fri, Mar 11, 2016 at 5:28 PM Yurii Shevtsov wrote:
> But personally I think it's fun. Also, now I understand, that rom-o-matic
> should be web-version of nconfig/menuconfig
>
>
I'm not sure that's quite right. But we can talk. You definitely know what
you are doing at this point :-)
ron
--
record as to how uniform, e.g., the x220 experience has
been? I know the chromebook uniformity is pretty good.
ron
On Wed, Mar 9, 2016 at 2:07 PM Alexander Couzens wrote:
> On Wed, 09 Mar 2016 20:57:23 +
> ron minnich wrote:
>
> > I suspect you know far more about writing such a
On Wed, Mar 9, 2016 at 4:16 AM Yurii Shevtsov wrote:
> I looked at sites you mentioned. I haven't any configuration feature on
> johnlewis.ie Instead it provides an instruction for running special shell
> script. But I much more liked original Rom-o-matic. I want do develop same
> thing, but with
yeah, we had something like this in the linuxbios days. I think you don't
want to build it on demand, but rather have a bunch of pre-built images
that are known good.
Really, look at johnlewis.ie, that's the best thing I've seen. Have you
also seen the original Rom-o-matic from the etherboot (now
These are actually reasonable questions. I am wondering if, as you get each
answer, you can document it for others who
have the same questions.
ron
On Sun, Mar 6, 2016 at 10:47 AM daoud yessine
wrote:
> Hi
>
> how we can get the timestamp from coreboot ?
>
> what's the name of table in the sour
On Mon, Feb 29, 2016 at 2:53 PM persmule wrote:
> , and siphon out the whole BIOS image,
> which will be sent to you soon, too.
>
>
>
I am not sure what you mean by "sent to you soon", but if it means you are
going to read a copyrighted image out of firmware and mail it to us, please
do NOT do th
Do you want to build Chrome from source to?
I have google doc that explains how building chromeos from source used to
work. Chromeos is quite a monster to build, and my google doc is out of
date (something changed), but it's possible to build a lot from source.
Just have a reasonably powerful CPU
We tried to do Doxygen starting in 2000, but the experiment never seemed to
work out. I still like the idea. One result was that you could
make documentation
and get a manual for the board you were working on at the time. That
actually did work for a few years but it all kind of decayed.
ron
On T
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