Hi Patrick,
understood and thanks anyway.
Regards,
Hook Guo
On Fri, Mar 27, 2015 at 6:33 PM, Patrick Georgi wrote:
> Hi Hook Guo,
>
> 2015-03-27 11:11 GMT+01:00 郭佳 :
>> At the time this main function has been called, the Cache as RAM has been
>> setup
>> by FSP, and the MTRR_PHYSBASE0 is FEF0_
Hi Hook Guo,
2015-03-27 11:11 GMT+01:00 郭佳 :
> At the time this main function has been called, the Cache as RAM has been
> setup
> by FSP, and the MTRR_PHYSBASE0 is FEF0_0006.
> BTW: (1) Using the debugger's memory window, I can see Cache as RAM region of
> temporary stack are full of A5 5A, is
Hi,
I'm debugging with Arium XDP3e debugger on ADI target board(MohonPeak based).
The coreboot.rom can bring target board up successfully in case of XDP
not plugged.
However, when stepping with debugger, the C code main function of romstage can't
be stepped, it always failed and the cpu goes into
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