Re: [coreboot] Bayley Bay FSP-based CRB

2018-06-26 Thread Zvi Vered
Dear Jose & Nico, Thank you very much for your help ! Best regards, Zvika On Thu, Jun 21, 2018 at 11:28 AM Jose Trujillo wrote: > Hello Zvika, > Look for the list of Linux commands to dump many of the information from > your original BIOS running, maybe there you will find this information. >

Re: [coreboot] Bayley Bay FSP-based CRB

2018-06-21 Thread Nico Huber
On 21.06.2018 02:34, Zvi Vered wrote: > In case of PCIe enumeration, the generation of PCIe (1,2,3) can be set> > Should vendor supply code for this ? or any other information ? PCIe configuration is SoC specific and should be done by FSP. However, I can't find any PCIe specific settings for the

Re: [coreboot] Bayley Bay FSP-based CRB

2018-06-21 Thread Jose Trujillo via coreboot
Hello Zvika, Look for the list of Linux commands to dump many of the information from your original BIOS running, maybe there you will find this information. Also, some configuration can be seen from your original BIOS running Intel FIT for Baytrail in Windows. About configuring those settings

Re: [coreboot] Bayley Bay FSP-based CRB

2018-06-21 Thread Nico Huber
Hello Zvika, On 18.06.2018 05:24, Zvi Vered wrote: > 1. The size of CBFS is: 0x20. Is it a fix size or should I change it > according to my board (which is also bay trail) ? on Intel platforms, the SPI flash is shared with other chipset compo- nents. The CBFS_SIZE should be at most the size

Re: [coreboot] Bayley Bay FSP-based CRB

2018-06-20 Thread Zvi Vered
Hello, Thank you very much for the detailed reply. Vendor's BIOS contains few peripherals initialization. For example: PCIe enumeration, SATA controller, USB etc. In case of PCIe enumeration, the generation of PCIe (1,2,3) can be set. Should vendor supply code for this ? or any other information

Re: [coreboot] Bayley Bay FSP-based CRB

2018-06-18 Thread Jose Trujillo via coreboot
Hello Zvika: 1.- Usually it is not necessary to change the CBFS size unless the compiler complain of lack of space. 2.- You should not worry about this setting to make your system to work. 3.- You should not use FSP_PACKAGE_DEFAULT if your plan is to use SIO because it will enable SOC internal

[coreboot] Bayley Bay FSP-based CRB

2018-06-17 Thread Zvi Vered
Hello, I inspected the "Bayley Baay FSP-based CRB" sample in coreboot. after make distclean I chose: Mainboard vendor: Intel Mainboard model: Bayley Bay FSP-based CRB 1. The size of CBFS is: 0x20. Is it a fix size or should I change it according to my board (which is also bay trail) ? 2.