On Sat, May 5, 2018 at 4:26 PM, Kyösti Mälkki wrote:
> On Sun, May 6, 2018 at 12:17 AM, Aaron Durbin wrote:
>>> I find it particularly hard to be civil on your first question, so
>>> trying with sarcasm instead. After 5000 or so development hours and
On Sun, May 6, 2018 at 12:17 AM, Aaron Durbin wrote:
>> I find it particularly hard to be civil on your first question, so
>> trying with sarcasm instead. After 5000 or so development hours and
>> direct support from AMD, is the boot sequence for soc/stoneyridge
>> prototypes
On Sat, May 5, 2018 at 6:27 PM, Marshall Dawson
wrote:
>> So did you hit problems with CAR_GLOBAL in agesa_get_dispatcher(),
>> when experimeting CZ vs ST? I don't see why this code works even for
>> dual-core ST but I did not evaluate CAR layout. Documentation part
On Fri, May 4, 2018 at 8:49 PM, Kyösti Mälkki wrote:
> On Fri, May 4, 2018 at 8:22 PM, Aaron Durbin wrote:
>> On Fri, May 4, 2018 at 11:16 AM, Kyösti Mälkki
>> wrote:
>>> On Fri, May 4, 2018 at 7:19 PM, Kyösti Mälkki
>
> So did you hit problems with CAR_GLOBAL in agesa_get_dispatcher(),
> when experimeting CZ vs ST? I don't see why this code works even for
> dual-core ST but I did not evaluate CAR layout. Documentation part for
> fixed MTRRs in gcccar.inc appears to be same.
>
I don't remember specifically
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On 05/05/2018 11:53 AM, Kyösti Mälkki wrote:
> On Sat, May 5, 2018 at 3:06 AM, Marshall Dawson
> wrote:
>>> My current guess is AP CPUs do not see initialised memory for
>>> _car_region_start .. _end. That region is
On Sat, May 5, 2018 at 3:06 AM, Marshall Dawson
wrote:
>> My current guess is AP CPUs do not see initialised memory for
>> _car_region_start .. _end. That region is set up using fixed MTRRs in
>> low memory and probably not synced between cores so early in romstage.
>
On Fri, May 4, 2018 at 8:22 PM, Aaron Durbin wrote:
> On Fri, May 4, 2018 at 11:16 AM, Kyösti Mälkki
> wrote:
>> On Fri, May 4, 2018 at 7:19 PM, Kyösti Mälkki
>> wrote:
>>> On Fri, May 4, 2018 at 6:37 PM, Aaron Durbin
>
> My current guess is AP CPUs do not see initialised memory for
> _car_region_start .. _end. That region is set up using fixed MTRRs in
> low memory and probably not synced between cores so early in romstage.
>
Kyosti, I haven't kept a close watch on CAR changes in the other AMD
systems,
On Fri, May 4, 2018 at 11:16 AM, Kyösti Mälkki wrote:
> On Fri, May 4, 2018 at 7:19 PM, Kyösti Mälkki wrote:
>> On Fri, May 4, 2018 at 6:37 PM, Aaron Durbin wrote:
Any idea what can be result of such weird behavior?
On Fri, May 4, 2018 at 7:19 PM, Kyösti Mälkki wrote:
> On Fri, May 4, 2018 at 6:37 PM, Aaron Durbin wrote:
>>>
>>> Any idea what can be result of such weird behavior?
>>
My current guess is AP CPUs do not see initialised memory for
_car_region_start
On Fri, May 4, 2018 at 6:37 PM, Aaron Durbin wrote:
> On Fri, May 4, 2018 at 9:23 AM, Piotr Król wrote:
>> Hi Aaron,
>> I tried to boot PC Engines apu2 on recent master branch and discovered
>> that it not boot. Bisection points to:
>>
>> 60320182d011
On Fri, May 4, 2018 at 9:23 AM, Piotr Król wrote:
> Hi Aaron,
> I tried to boot PC Engines apu2 on recent master branch and discovered
> that it not boot. Bisection points to:
>
> 60320182d011 console: only allow console messages after initialization
>
> It is hard to
Hi Aaron,
I tried to boot PC Engines apu2 on recent master branch and discovered
that it not boot. Bisection points to:
60320182d011 console: only allow console messages after initialization
It is hard to believe that this change cause AGESA reset loop, but I
checked 3 times. After applying
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