Felix, thank you very much - this is exactly what I needed! Also now
found a "51192_Bolton_FCH_RRG.pdf" with slightly newer (but similar)
info.
Dear friends, thank you so much for your kind help! Now this important
work is completed for G505S
and you're welcome to take a look at
https://review.cor
Hi Mike!
The PIRQ_MISC registers in the indirect I/O address space with 0xc00
being the index register aren't IRQ numbers; those configuration bits.
To get an idea, have a look at the interrupt routing register chapter of
for example AMD publication number 45482 [1]. Not sure if that's the
ex
Hi Nico, thank you very much for your kind help, it really helped to
advance! Please could you answer a small question:
While cleaning up some code I noticed there are Misc,Misc0,Misc1,Misc2
interrupts - with the following "magic" values respectively:
mainboard_picr_data:
[0x08] = 0x5A,0xF1,0x00,
Hi Mike,
On 10.11.20 19:22, Mike Banon wrote:
> Thank you very much for your advice, dear Naresh, I will try matching
> the UEFI routing.
I wouldn't expect too much. If things are configurable in the chipset
(they usually are these days) it's possible that coreboot configures
them differently and
Thank you very much for your advice, dear Naresh, I will try matching
the UEFI routing.
Dear Elyes, huge thanks to you for telling me about "getpir" utility -
never heard about it before!
> this old "getpir" utility may help you ;)
> You may have to run:
> coreboot/util$ git revert 6c90f3334e65ff4
Hi Mike,
I see that IRQ routing that you set in Coreboot is different then that in
UEFI bios.
I recommend you first try to match them.
Required data is already available in the dump you took.
Also this link can be of help:
https://gist.github.com/mcastelino/4acda7c2407f1c51e68f3f994d8ffc98
IRQ r
Dear Naresh, please check the attached archive for these files (and
tell if there's anything else I need to show)
On Thu, Nov 5, 2020 at 8:08 PM Naresh G. Solanki
wrote:
>
> Can you give following output with coreboot and OEM bios.
> lspci -vvvk
> dmesg
> cat /proc/interrupt
>
>
> On Thu, 5 Nov,
Can you give following output with coreboot and OEM bios.
lspci -vvvk
dmesg
cat /proc/interrupt
On Thu, 5 Nov, 2020, 6:29 pm Mike Banon, wrote:
> Still need your help, friend
>
> On Sat, Oct 24, 2020 at 11:15 AM Mike Banon wrote:
> >
> > Although I found this article
> > https://www.coreboot.o
Still need your help, friend
On Sat, Oct 24, 2020 at 11:15 AM Mike Banon wrote:
>
> Although I found this article
> https://www.coreboot.org/Creating_Valid_IRQ_Tables , I'm not sure if
> it applies to mainboard_picr_data/_intr_data : considering a problem
> from my previous msg - where a copy-pas
Although I found this article
https://www.coreboot.org/Creating_Valid_IRQ_Tables , I'm not sure if
it applies to mainboard_picr_data/_intr_data : considering a problem
from my previous msg - where a copy-paste of old picr/intr data
structures gave the bad results. Could you please clarify if this
a
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