[coreboot] Re: Boot loop on Thinkpad X200/GM45 with master.

Hi Denis, > I've a reboot loop on master on the Thinkpad X200. did you try it yet without the EHCI debug? if the reset happens after 4~5s, it might be the watchdog (which seems to be enabled for ICH9). Nico ___ coreboot mailing list --

[coreboot] Coreboot not scanning all PCI devices

Hi, I have an intel Xeon-D board with vendor BIOS and I trying to get it to work with the Coreboot. I am successful in booting OS through grub payload from coreboot-4.9-1259-gc4f3972-dirty. The problem is some of the PCI devices are missing while scanning PCI in coreboot but detecting all

[coreboot] Re: RAM init failing with some DIMMs on GM45 with "Timing overflow during read training."

Hi Denis, >> Raw card type:D last time we encountered problems with type D DIMMs, we concluded that it's not supposed to work [1]. Can you confirm if your DIMMs are stable with the vendor BIOS? We should probably issue a warning when type D is installed. Nico [1]

[coreboot] KGPE-D16 maintainership

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 Hi all, we see a lot of attention around KGPE-D16 maintainership problems. After discussion with Thierry Laurion (Insurgo) at OSFC2019 3mdeb decided to help in maintaining that platform by organizing crowd founding campaign or getting founds in

[coreboot] Re: KGPE-D16 maintainership

Hello, On Tue, 17 Sep 2019 11:19:42 +0200 Piotr Król wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA512 > > Hi all, > we see a lot of attention around KGPE-D16 maintainership problems. > After discussion with Thierry Laurion (Insurgo) at OSFC2019 3mdeb > decided to help in maintaining

[coreboot] Re: Coreboot not scanning all PCI devices

Hi there, open a devicetree.cb file for your board, located at somewhere like ./coreboot/src/mainboard/[board_vendor]/[board_model]/devicetree.cb There will be the lines like device pci 0.0 on end device pci 0.2 on end device pci 1.0 on end device pci 1.1 on end device pci 2.0 off end You need

[coreboot] Re: Coreboot not scanning all PCI devices

If I am not mistaken at least 00:03.2 and 00:03.3 are the integrated PCIe-Ports of the IOU (PEG-port) and their availability depends on the PCIe bifurcation of the associated PEG-port. You can configure the bifurcation over the FSP-parameters "ConfigIOU2_PciPort1" and "ConfigIOU1_PciPort3". If

[coreboot] Re: KGPE-D16 maintainership

I'd be happy to assist as well with hardware. I have a spare fully functional KGPE-D16 with dual CPUs that can be donated to a US-side developer interested in keeping the native init alive, working, and in-tree. If enough functionality can be restored in coreboot master I can also reactivate

[coreboot] Re: KGPE-D16 maintainership

On Tue, 17 Sep 2019 11:19:42 +0200 Piotr Król wrote: > If anyone is willing to help in founding, sponsoring hardware or by > code development and testing we would be very grateful. Cool! Thank you for your effort. I don't have much funds available, but I could contribute a few spare 16 MiB

[coreboot] Re: RAM init failing with some DIMMs on GM45 with "Timing overflow during read training."

On Tue, 17 Sep 2019 10:21:38 +0200 Nico Huber wrote: > Hi Denis, Hi, > >> Raw card type:D Is there more information on such "card type" somewhere? Is there a way to avoid buying such "card type"? > last time we encountered problems with type D DIMMs, we concluded that > it's not supposed

[coreboot] Re: KGPE-D16 maintainership

Hello, I'd be happy to kick more than a few bucks towards hardware or other costs. Just need to know where to send it. I'll also drop a post over on r/Libreboot. Sincerely, -Matt On Tue, Sep 17, 2019 at 1:33 PM Timothy Pearson < tpear...@raptorengineering.com> wrote: > I'd be happy to

[coreboot] Re: KGPE-D16 maintainership

On 17/09/2019 10:50, Vikings GmbH via coreboot wrote: On Tue, 17 Sep 2019 11:19:42 +0200 Piotr Król wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA512 [...] Unfortunately we don't have hardware. During OSFC 2019 Stefan left one board, but it was too late (and probably too expensive)