Hello All,
Firstly this is sort of building off of the suggestions from the "i2c_writeb vs
i2c_raw_write output" thread; I have looked into the smbus_xxx() functions and
they might do the trick. So basically what I am trying to do is send the
POSTcodes to somewhere I can read them and at the
Hi again,
> It would be interesting to test 0x00...300 and 0xff...400 just for
> completeness.
The 0x00...300 does the same (NMI delivered on all CPUs) and the other one does
nothing.
> That would be great. I am really curious about the official clarification on
> the issue. Maybe there is a
On 10/10/2016 21:59, Rudolf Marek wrote:
> Hi Andriy,
>
>> An example:
>> $ ioapic_wr 3 0xff000300
>
> I tried with minicom and IRQ 4, and I can confirm that NMI is delivered only
> when using the redirection entry above. The one 0x0400 does
> nothing
> in my case. I tested
On Mon, Oct 10, 2016 at 09:40:49AM -0600, Trammell Hudson wrote:
> [...]
> I filed an issue on the tracker related to the ramstage problem
> and am trying to debug it with Aaron:
>
> https://ticket.coreboot.org/issues/78
And it appears to be a bug of my own creation...
Earlier I ran into a probl
Hi Andriy,
> An example:
> $ ioapic_wr 3 0xff000300
I tried with minicom and IRQ 4, and I can confirm that NMI is delivered only
when using the redirection entry above. The one 0x0400 does nothing
in my case. I tested on AMD Hudson chipset, I had to add #include to
have the
?Thank you Julius for the explanation, I really appreciate it especially since
in my googling I didn't manage to gather the information you provided in your
last paragraph. Also thank you both Duncan and Kyösti for the
suggestions/direction for my continuation of this project, I will defiantly
Hi Arthur,
On 09.10.2016 18:50, Arthur Heymans wrote:
> Hi
>
> I'm trying to port coreboot to the gigabyte ga-945gcm-s2l, which has a
> 945gc northbridge, a ich7 southbridge and a ite it8718f sio. I'm trying
> all this with a 1067fsb cpu, so in that last aspect there is no
> precedent in coreboot
When my Skylake system comes out of S3 it fails to resume and ends up
going back through the normal boot path. Console output durng resume:
coreboot-4.4-1781-g2fcabb8-heads Wed Oct 5 01:45:23 UTC 2016 ramstage
starting...
FSP_INFO_HEADER not set!
Enumerating buses...
Enabling Common Clock Confi
>> What is INTEL IOTG support?
Never mind, I wanted to say that INTEL will not support Penryn, either
Merom, or Nehalem (over 9 years in production).
>> No idea, but I can certainly try it.
Yes, you can. Ether using source code, but other that that (if you have
some sort of problems), you just nee
On 09/10/2016 23:41, Rudolf Marek wrote:
> Great, so there is a bug! Do you have some USB image I can try on more recent
> AMD system (with Hudson chipset). Or we can try to report this to AMD, but I
> have read somewhere that the new chipsets are done by Asmedia.
I did most of the testing using t
On 08/10/2016 23:57, Rudolf Marek wrote:
> I did the HPET NMI generator on Intel PCH, it works fine. I just fill the MSI
> addr/data in a way that it was delivering NMI to certain CPU - physical
> delivery
> to a CPU with a certain ID.
>
> If this does not work on AMD, perhaps there is some probl
Zoran Stojsavljevic writes:
> Hello Arthur,
>
> CPUID 1067x? Penryn?
> https://en.wikipedia.org/wiki/Penryn_(microprocessor) ?!
This is indeed the cpu which I used to run tests with. This board should
also work with older LGA775 cpu I think. (even though coreboot has
problems with CAR on this P4
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