Hi,
There is slight update from AMD [1], relevant part for you:
*AMD Microcode Updates for GPZ Variant 2/Spectre*
In addition, microcode updates with our recommended mitigations addressing
Variant 2 (Spectre) have been released to our customers and ecosystem partners
for AMD processors
On 04/11/2018 09:54 PM, Raymond Yeung wrote:
> Thanks David for the detailed response.
>
>
> My main motivation to go down Coreboot/UBOOT route is to attempt to simplify
> the remaining boot-up to Linux. Instead of using PXE-BOOT, we could use tftp
> only. Am I correct to say that?
If you
Thanks David for the detailed response.
My main motivation to go down Coreboot/UBOOT route is to attempt to simplify
the remaining boot-up to Linux. Instead of using PXE-BOOT, we could use tftp
only. Am I correct to say that?
If we're to use whatever that is available today, instead of
On 04/11/2018 06:39 PM, Raymond Yeung wrote:
> I currently have a board that uses Intel Xeon D (previously codenamed
> Broadwell DE). It boots up with BIOS/UEFI. I 'm exploring other oot-up
> options here.
Let us know what you are attempting to accomplish.
> I'm not familiar with this early
On Wed, Apr 11, 2018 at 3:39 PM, Raymond Yeung wrote:
> I currently have a board that uses Intel Xeon D (previously codenamed
> Broadwell DE). It boots up with BIOS/UEFI. I 'm exploring other oot-up
> options here.
>
>
> I'm not familiar with this early stage of system
I currently have a board that uses Intel Xeon D (previously codenamed Broadwell
DE). It boots up with BIOS/UEFI. I 'm exploring other oot-up options here.
I'm not familiar with this early stage of system initialization. It seems
BIOS/UEFI to Linux needs to use PXE, with the need to configure
Hi
We have runtime configuration arguments implemented for our platform in out
fork.
This is very simple, we just add few lines in SeaBIOS configuration file on CBFS
(https://bit.ly/2qmX9nT — config example, https://bit.ly/2v5Era6 — handling
code).
There are only boolean values, no syntax,
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That should work, yes. It's the very early init code that is getting
confused with the differing core counts, likely related to APIC setup or
similar.
On 04/11/2018 03:26 PM, taii...@gmx.com wrote:
> But it would be possible to have two CPU's with
But it would be possible to have two CPU's with the same core count but
differing frequencies?
Thanks
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This may be a general coreboot limitation at the moment. The
compatibility sections for mixed CPUs in the BKDG are more concerned
with total power delivery and proper P-state setup than anything else.
If I recall correctly, coreboot assumes both
Thank you for your reply Timothy.
Vendor Bios doesn't print any special message regarding this.
In fact it shows a total of 28 cores (16+12).
I thought mixing CPUs from same families was supported.
Regards,
- Eli
On 11/04/18 20:44, Timothy Pearson wrote:
> I don't know if coreboot has
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I don't know if coreboot has support for differing CPUs in the same
mainboard; it's not something I can recall testing at any point.
The failure is occurring far before memory initialization, in CAR, in
core setup. I'd guess it has something to do
Hello,
After testing the board for some weeks I bought another CPU (6276). I
installed this into CPU1 slot and a 6238 in CPU2.
I checked that both CPUs are shining and also the memory (Micron
MT18JSF25672PDZ-1G4F1DD, populated in A2/C2/E2/G2 slots).
The problem is that Coreboot seems to hang at
Mike Banon writes:
> Line 869 - "const int amd_erratum_319[] =" --- is this code really
> against the Spectre, or its more like against the erratas in general?
> Also, What if someone would like to use either a Linux distro which
> hasnt been upgraded to the latest kernels,
Line 869 - "const int amd_erratum_319[] =" --- is this code really
against the Spectre, or its more like against the erratas in general?
Also, What if someone would like to use either a Linux distro which
hasnt been upgraded to the latest kernels, or maybe some alternative
OS like FreeDOS or
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