On 25.06.2018 01:55, Timothy Pearson wrote:
> On 06/24/2018 06:41 PM, Timothy Pearson wrote:
>> On 06/24/2018 06:35 PM, Nico Huber wrote:
>>> On 24.06.2018 23:52, Timothy Pearson wrote:
On 06/24/2018 03:43 PM, Nico Huber wrote:
> On 24.06.2018 21:37, taii...@gmx.com wrote:
>> On
On 06/24/2018 06:41 PM, Timothy Pearson wrote:
> On 06/24/2018 06:35 PM, Nico Huber wrote:
>> On 24.06.2018 23:52, Timothy Pearson wrote:
>>> On 06/24/2018 03:43 PM, Nico Huber wrote:
On 24.06.2018 21:37, taii...@gmx.com wrote:
> On 06/24/2018 02:59 PM, ron minnich wrote:
>> On Sun,
On 06/24/2018 06:35 PM, Nico Huber wrote:
> On 24.06.2018 23:52, Timothy Pearson wrote:
>> On 06/24/2018 03:43 PM, Nico Huber wrote:
>>> On 24.06.2018 21:37, taii...@gmx.com wrote:
On 06/24/2018 02:59 PM, ron minnich wrote:
> On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
>
On 24.06.2018 23:52, Timothy Pearson wrote:
> On 06/24/2018 03:43 PM, Nico Huber wrote:
>> On 24.06.2018 21:37, taii...@gmx.com wrote:
>>> On 06/24/2018 02:59 PM, ron minnich wrote:
On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
wrote:
>
>
> "While we’d love
On 06/24/2018 03:43 PM, Nico Huber wrote:
> On 24.06.2018 21:37, taii...@gmx.com wrote:
>> On 06/24/2018 02:59 PM, ron minnich wrote:
>>> On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
>>> wrote:
>>>
"While we’d love to provide you with this information, we believe we
Hi,
Lets do some speculation that some off the shelf DDR memory controller is used.
Maybe it could be same as the RockChip aka Denali High-Speed DDR PHY IP from
Cadence?
It has also some "interrupt status" bits and such and "bstlen" which sounds
same as the few
regs named as the
I'm still interested in risc-v, just not hifive.
In saying I've lost interest, I'm definitely not saying anyone is a bad
person. The sifive people are wonderful, personally and professionally, and
I wish them the best success.
But sifive had to make some decisions to get to what they thought
On 24.06.2018 21:37, taii...@gmx.com wrote:
> On 06/24/2018 02:59 PM, ron minnich wrote:
>> On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
>> wrote:
>>
>>>
>>>
>>> "While we’d love to provide you with this information, we believe we
>>> cannot. However, we can’t prevent anyone from
Hi Ron,
Dne 24.6.2018 v 20:59 ron minnich napsal(a):
> and ... there ends my interest in the hifive. A shame.
Well perhaps because the DDR controller is third party IP, see [1] FAQ or here:
> The Freedom U540 SoC is based on the Freedom Unleashed Platform, which has
> been open sourced. The
On 06/24/2018 02:59 PM, ron minnich wrote:
> On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
> wrote:
>
>>
>>
>> "While we’d love to provide you with this information, we believe we
>> cannot. However, we can’t prevent anyone from disassembling the fsbl and
>> copying the values sent to the
On 06/23/2018 01:58 AM, Jorge Fernandez Monteagudo wrote:
> Hi Nico, thanks for the feedback!
>
>
>> I guess it's used, but you need an acpi name for all devices along the
>> path. "LIBR" is the name for the LPC device, there should also be one
>> for the PCI bus/domain. I would try
On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
wrote:
>
>
> "While we’d love to provide you with this information, we believe we
> cannot. However, we can’t prevent anyone from disassembling the fsbl and
> copying the values sent to the blackbox DDR register map."
>
>
and ... there ends
On Fri, Jun 22, 2018 at 01:01:04PM +0200, Jonathan Neuschäfer wrote:
[...]
> Section 20.3 describes the initialization sequence for the DRAM
> controller, but leaves out the values for the register for "memory
> timing settings, PAD mode configuration, initialization, and training."
> It says:
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