On Tue, 2019-02-26 at 11:16 -0800, ron minnich wrote:
> On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
> wrote:
> >
> > Hi coreboot folks,
> > in order to support TEE like Intel TXT it is necessary to be able
> > to
> > clear all DRAM at boot on request.
> >
> > As all of the x86 coreboot code
Hi all
A change [1] has been approved that applys a minimum loglevel of BIOS_DEBUG
for CBMEM console. There should be miminal performance impact as it is
nothing but writes to cacheable memory.
For some platform this could cause that pre-ram console buffer runs out of
space. My opinion is that
I looked for my CL from years back in which I showed a way to 64-bit
amd64 ramstage, but I don't see it any more.
But it was easy.
On Tue, Feb 26, 2019 at 2:11 PM Rudolf Marek wrote:
>
> Hi,
>
> Dne 26. 02. 19 v 22:58 Nico Huber napsal(a):
> > On 26.02.19 20:16, ron minnich wrote:
> >> On Tue,
Hi,
Dne 26. 02. 19 v 22:58 Nico Huber napsal(a):
> On 26.02.19 20:16, ron minnich wrote:
>> On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
>> wrote:
>>>
>>> Hi coreboot folks,
>>> in order to support TEE like Intel TXT it is necessary to be able to
>>> clear all DRAM at boot on request.
>>>
>>>
Hello Neelix,
On 26.02.19 22:54, Neelix via coreboot wrote:
> I just compiled coreboot for a x220 and I got a error saying that
> data.vbt wasn't located in src/mainboard/lenovo/x220. It's indeed not
> in directory it should be in. Its located in
> src/mainboard/lenovo/x220/variants/x220/.
I
On 26.02.19 20:16, ron minnich wrote:
> On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
> wrote:
>>
>> Hi coreboot folks,
>> in order to support TEE like Intel TXT it is necessary to be able to
>> clear all DRAM at boot on request.
>>
>> As all of the x86 coreboot code is x86_32, it is necessary
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Hash: SHA256
Hello,
I just compiled coreboot for a x220 and I got a error saying that
data.vbt wasn't located in src/mainboard/lenovo/x220. It's indeed not
in directory it should be in. Its located in
src/mainboard/lenovo/x220/variants/x220/. Can you guys
On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
wrote:
>
> Hi coreboot folks,
> in order to support TEE like Intel TXT it is necessary to be able to
> clear all DRAM at boot on request.
>
> As all of the x86 coreboot code is x86_32, it is necessary to make use
> of PAE to clear memory.
I would
Hi coreboot folks,
in order to support TEE like Intel TXT it is necessary to be able to
clear all DRAM at boot on request.
As all of the x86 coreboot code is x86_32, it is necessary to make use
of PAE to clear memory.
Please find the attached patch series which proposes an architecure
independed
Hello Masanori,
sorry for the late reply, I guess I could have saved you from some
confusion.
Am 26.02.19 um 05:35 schrieb Masanori Ogino:
> On Mon, Feb 25, 2019 at 4:27 AM Lance Zhao wrote:
>> Current coreboot should have same level of microcode compare to
>> intel-microcode for Linux.
>
>
On Mon, Feb 25, 2019 at 03:42:41PM -0500, taii...@gmx.com wrote:
I'm reasonably sure that this is not true and security-conscious users
can disable internal flashing, but I haven't been able to find any
mention of such a setting in the documentation.
Isn't it possible to set the flash chip
Dear Lance,
Thank you for your reply.
On Mon, Feb 25, 2019 at 4:27 AM Lance Zhao wrote:
> Current coreboot should have same level of microcode compare to
> intel-microcode for Linux.
Indeed. I saw a commit updating Intel microcode in last December, so I
am sure the microcode is not so ancient
Dear Ivan,
On Tue, Feb 26, 2019 at 12:26 AM Ivan Ivanov wrote:
> Please tell, do you observe the same results with more fresh Linux
> distributions?
> It is known that Debian usually contains the outdated packages and
> some of the problems there - may have already been fixed.
> Try running
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