[coreboot] Re: IS_ENABLED() vs CONFIG()

[Julius Werner]

> Now, when we run "coreboot$ ./util/lint/kconfig_lint " , we can see :
> #! Warning: CONFIG() used on unknown value (option) at 
> src/include/kconfig.h:21.
> #! Warning: CONFIG() used on unknown value (%02x) at 
> src/northbridge/amd/amdfam10/util.c:138.

Yes... that's why it's a warning and not an error. ;) It's hard to
completely avoid false positives with the limited parsing capabilities
of a Perl script.

I still think this is valuable enough as a warning because for new CLs
it should point out a real problem most of the time and will help
people avoid errors. We have plenty of other spurious warnings when
you run the linter across the whole tree right now (e.g. a page full
of "Unused symbol" that someone should probably clean up at some
point), so I hope adding two more isn't going to be a huge problem?
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[coreboot] Re: IS_ENABLED() vs CONFIG()

[ehaouas]

Hi Julius,



Yes, you are right.

I've send a new patch #31848 & 31810, would you have a look on it when you have 
time please?



BTW: I did  some cleaning : 
https://review.coreboot.org/#/q/status:merged+project:coreboot+branch:master+topic:Clean_Kconfig
 :p 



Thank you


 Message d'origine 
De : "Julius Werner" 
À : ehao...@noos.fr
Objet : Re: [coreboot] IS_ENABLED() vs CONFIG()
Date : 11/03/2019 19:54:23 CET
Copie à : "Coreboot" 

> Now, when we run "coreboot$ ./util/lint/kconfig_lint " , we can see :
> #! Warning: CONFIG() used on unknown value (option) at 
> src/include/kconfig.h:21.
> #! Warning: CONFIG() used on unknown value (%02x) at 
> src/northbridge/amd/amdfam10/util.c:138.

Yes... that's why it's a warning and not an error. ;) It's hard to
completely avoid false positives with the limited parsing capabilities
of a Perl script.

I still think this is valuable enough as a warning because for new CLs
it should point out a real problem most of the time and will help
people avoid errors. We have plenty of other spurious warnings when
you run the linter across the whole tree right now (e.g. a page full
of "Unused symbol" that someone should probably clean up at some
point), so I hope adding two more isn't going to be a huge problem?

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[coreboot] New Defects reported by Coverity Scan for coreboot

[scan-admin]

Hi,

Please find the latest report on new defect(s) introduced to coreboot found 
with Coverity Scan.

2 new defect(s) introduced to coreboot found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent 
build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)


** CID 1399411:  Null pointer dereferences  (NULL_RETURNS)
/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 90 in 
ConfigureDefaultUpdData()



*** CID 1399411:  Null pointer dereferences  (NULL_RETURNS)
/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 90 in 
ConfigureDefaultUpdData()
84 {
85  DEVTREE_CONST struct device *dev;
86  DEVTREE_CONST config_t *config;
87  printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n");
88 
89  dev = pcidev_path_on_root(SOC_DEV_FUNC);
>>> CID 1399411:  Null pointer dereferences  (NULL_RETURNS)
>>> Dereferencing a null pointer "dev".
90  config = dev->chip_info;
91 
92  /* Set up default verb tables - Just HDMI audio */
93  UpdData->AzaliaConfigPtr = (UINT32)
94 
95  /* Set SPD addresses */

** CID 1255946:  Memory - corruptions  (ARRAY_VS_SINGLETON)
/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 177 in 
ConfigureDefaultUpdData()



*** CID 1255946:  Memory - corruptions  (ARRAY_VS_SINGLETON)
/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 177 in 
ConfigureDefaultUpdData()
171 case MIPI_DEV_FUNC: /* Camera / Image 
Signal Processing */
172 if (FspInfo->ImageRevision >= 
FSP_GOLD3_REV_ID) {
173 UpdData->ISPEnable = 
dev->enabled;
174 } else {
175 /* Gold2 and earlier FSP: 
ISPEnable is the field*/
176 /* next to PcdGttSize in 
UPD_DATA_REGION struct */
>>> CID 1255946:  Memory - corruptions  (ARRAY_VS_SINGLETON)
>>> Using ">PcdGttSize" as an array.  This might corrupt or 
>>> misinterpret adjacent memory locations.
177 
*(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled;
178 printk (FSP_INFO_LEVEL,
179 "Baytrail Gold2 or 
earlier FSP, adjust ISPEnable offset.\n");
180 }
181 printk(FSP_INFO_LEVEL, 
"MIPI/ISP:\t\t%s\n",
182 
dev->enabled?"Enabled":"Disabled");



To view the defects in Coverity Scan visit, 
https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V05UPxvVjWch-2Bd2MGckcRbLuoVetFLSjdonCi1EjfHRqWGQvojmmkYaBE-2BPJiTQvaU4HClancRgJSp1vcdHRWU-3D_q4bX76XMySz3BXBlWr5fXXJ4cvAsgEXEqC7dBPM7O5YrlKxmu5dmMqAhFEcChrzUG0OUHvvbNPU45h3XG4HkTXzLmk9YMIjer8Du8RJsrvgTqBHVDDiwMQCp6tFVj524W5Kaz22paG5aw-2FKvOuGxh6-2BDsg0EjfHVSh0m-2BRM3tdjmTTcf6w9qFXszHEawgknl8BxUADGrNTb8j67rzdTH3vuL-2FYozKgL-2BEX8otojPesk-3D
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[coreboot] Shubhendra - GSoC proposal Inquiry about "Port payloads to RISC-V"

[Shubhendra Singhal]

Dear Sir/Ma'am,

I am Shubhendra Pal Singhal, currently third year in Computer Science at
NIT Trichy, India. I wish to apply for Google Summer of Code. I looked into
the profile of coreboot 4.9 and found out the project idea "*Port payloads
to ARM, AArch64, MIPS or RISC-V*" to be very interesting.

I have worked in the similar field on *RISCV architecture at IIT Madras
where I helped in porting real time OS eChronos*, on RISCV architecture. I
will be undergoing a *project in Embedded systems offered by USC Los
Angeles in solving the SAT Solvers using OS and Digital Logic*.
Furthermore, I am currently  working on a *long term project with under
Prof. N.Ramasubramanium on the AI chip* where we are trying to solve the
processing speeds by efficiently reducing the number of writes in the cache
for faster access. I am also *undergoing Microcontrollers and
Microprocessors* as my core subject in my current semester and have
already* undergone
OS, Real time Systems* in my B.Tech IV semester.
I have included my further details in my Linkedin  : *
https://www.linkedin.com/in/
shubhendra-singhal-7378a9131/*

I want to contribute to the open source community in the field of Operating
Systems and this can prove to be an excellent platform for gaining
experience in field of systems. This opportunity can pave my career,
towards applied research in the field of Systems.

*While browsing through the link, I saw the mailing list assigned for the
project. It would be very useful if you could guide me as to what is
expected in the project proposal and how can I serve the open source
community in the best possible way. *Any guidance would be very useful and
I hope to receive a reply soon. Thanking you for your time and
consideration.

Regards
Shubhendra Pal Singhal
National Institute Of Technology, Trichy, India
Phone number : +91 9787888015
Email-id : shubhendrapalsing...@gmail.com
Linkedin :  
https://www.linkedin.com/in/shubhendra-singhal-7378a9131/
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