Re: [coreboot] Adapting Linux kernel documentation setup with Sphinx and reStructuredText

Zaolin has been working for a while on updating our documentation, and his plan is to switch coreboot to using Hugo for our documentation manager.[1] Hugo supports various different markup languages, including markdown, html, RestructuredText, and AsciiDoc. [2] I meant to send the list an email

[coreboot] Upcoming coreboot release v4.5 - Targeting mid-October.

Hi Everyone, We're coming up on our next coreboot release. We'd like to get the release done around the middle of October, but if there are issues in flight, we can delay it a bit. The release will absolutely happen before end of the month. If anyone is working on major changes that will

Re: [coreboot] AM1ML IOMMU Support / Where has the wiki page gone?

The AM1ML page was created as just a single dot. I have no clue why. https://www.coreboot.org/index.php?title=Board:biostar/am1ml=history Martin. On Sunday, September 18, 2016, taii...@gmx.com wrote: > I recently purchased one of these boards after seeing articles about

Re: [coreboot] Welcome to the new coreboot.org!

efan.reina...@coreboot.org> > > wrote: > > > >> Hi! > >> > >> As some of you might already have noticed, our new web presence > >> has gone live on https://www.coreboot.org/ today! > >> > >> I want to use this chance to send a big s

Re: [coreboot] [RFC] Deciding on style for multi-line comments

> --vb > > On Fri, Aug 26, 2016 at 8:48 AM, Martin Roth <gauml...@gmail.com> wrote: > >> Can we please just decide on some tool and setting that we can run all >> the changes through that will "correctly" format it so we can stop arguing >> about th

Re: [coreboot] [RFC] Deciding on style for multi-line comments

Can we please just decide on some tool and setting that we can run all the changes through that will "correctly" format it so we can stop arguing about the format? Martin On Thu, Aug 25, 2016 at 12:59 PM, Julius Werner wrote: > First of all, let's dispel the notion that

Re: [coreboot] ASUS KFSN4-DRE (K8) Automated Test Failure [master]

Thanks Timothy. If anyone does have some time and would like to look at this, I can send you a KFSN4-DRE (K8) board. Martin On Mon, Aug 22, 2016 at 10:09 AM, Timothy Pearson < tpear...@raptorengineering.com> wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > On 08/21/2016 03:48 PM,

Re: [coreboot] Coreboot is failing to build

Hi Ali, The build script seems to be working for me, so it might be your network connection or your environment. Currently we don't run the checksum routine again after downloading the file. We probably need to do that. My first thought is that it didn't download correctly for some reason. If

Re: [coreboot] ARM Trusted Firmware build issue

Hey Paul, I'll get that patch tested and replace the current patch with it if it works. Thanks, Martin On Tue, Aug 2, 2016 at 9:51 AM, Paul Kocialkowski wrote: > Le mercredi 20 juillet 2016 à 19:33 -0700, Stefan Reinauer a écrit : >> Martin produced a binutils fix for the

Re: [coreboot] WG: What is the best way to treat warnings reported by checkpatch.pl

Hey Werner, Thanks for bringing up this topic. It's something we've discussed a bunch of times, but hadn't done anything about until now. Here's what I've done: I've pushed the .checkpatch.conf from the Chrome OS coreboot tree https://review.coreboot.org/#/c/15919/ I had initially pushed a

Re: [coreboot] how to debug without com port

Hi Cheng, Without knowing your platform, what you actually have available. and what your budget is, and where you're stuck, it's hard to say, but here are some directions you could look: - If you're making it to an OS but something's wrong, use the CBMEM console. - EHCI debug could be the best

Re: [coreboot] Query to release the code for new board

Hi Mayuri, coreboot does not share the TXE or descriptor.bin files for the boards. In the instructions from Intel for the BayleyBay CRB, it tells you to build coreboot as a 3MB rom file and to flash that to the top of the ROM chip, so as to not overwrite the TXE & Descriptor on the board. That

Re: [coreboot] TXE and Descriptor bin management in Coreboot

Hi Mayuri, The descriptor.bin file is relatively specific to each board. This sets the soft-straps, gives information about the ROM chip being used on that particular board, and sets the sizes of the areas on the SPI ROM. As for the TXE/ME/SPS/xxx binary, this would be specific to the CPU/SOC

Re: [coreboot] ARM Trusted Firmware build issue

13, 2016 at 9:14 AM, Paul Kocialkowski <cont...@paulk.fr> wrote: > Hi, > > Le mercredi 13 juillet 2016 à 08:57 -0600, Martin Roth a écrit : >> Thanks for posting about this. I've spent some time looking into >> this as well, but in my usual fashion, I didn't

Re: [coreboot] ARM Trusted Firmware build issue

Hi Paul, Thanks for posting about this. I've spent some time looking into this as well, but in my usual fashion, I didn't communicate what I found in a responsible fashion. Here's what I posted in a code review: > The current binutils (2.26) is failing to build the current >

Re: [coreboot] setting ipxe rom path deslects ipxe option

Hi Andrew, I was able to reproduce this issue. It looks like the 'optional' keyword is creating some odd behavior. Thanks for letting us know. Here's the patch to fix the problem. https://review.coreboot.org/1 Because of the way the Kconfig was rewritten, you'll have to re-enable it

Re: [coreboot] [SeaBIOS] UEFI project ideas

Here's a patch to build the UEFI coreboot payload package directly as a coreboot payload. https://review.coreboot.org/#/c/15057/ Martin On Tue, Jun 7, 2016 at 1:13 PM, Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > > I fail to see what you are trying to tell me. > > I'm not sure

Re: [coreboot] Add bootorder file for Seabios

Hi Naveed, Currently, the bootorder file would need to be manually added after the build. https://www.coreboot.org/SeaBIOS#Configuring_boot_order I just pushed a patch to allow the bootorder to be added during the build process. https://review.coreboot.org/15076 Martin On Tue, May 31, 2016 at

[coreboot] autoport

Hi phcoder, I'm trying to resolve a question that came up with inteltool & autoport regarding how the probing of graphics should behave. Stefanct kept having his board reboot when he was running autoport, so he added this change to separate out the graphics call as "unsafe" when probing all.

Re: [coreboot] What purpose the "mrc.cache"?

1) The MRC cache is a location for saving the state of the memory registers. These values are typically used to restore the memory controller state on resume from S3 suspend, or to help the system boot faster. On systems using the Rangeley FSP it is not optional as it is on some other platforms.

Re: [coreboot] SeaBios serial(RX) is not running.

Kyösti, thanks for doing that. On Mon, May 23, 2016 at 12:47 AM, 김유석 책임연구원 <kay@hansol.com> wrote: > Dear Sir. > > Thank's your work. > > > Enable the bi-direction serial console is done. > > > 2016-05-20 오후 8:36에 Kyösti Mälkki 이(가) 쓴 글: > > > >

Re: [coreboot] permissions error building external payload

PENBIOS_STABLE) \ CONFIG_OPENBIOS_REVISION=$(CONFIG_OPENBIOS_REVISION) \ CONFIG_OPENBIOS_REVISION_ID=$(CONFIG_OPENBIOS_REVISION_ID) \ MFLAGS= MAKEFLAGS= Martin On Wed, May 18, 2016 at 6:08 PM, David Griffith <d...@661.org> wrote: > On Wed, 1

Re: [coreboot] permissions error building external payload

Hi David, You need to add a rule to payloads/external/Makefile.inc as well. Here's a start: payloads/external/OpenBIOS/openbios/obj-x86/openbios-builtin.elf openbios: $(top)/$(DOTCONFIG) $(MAKE) -C payloads/external/OpenBIOS all \ CONFIG_OPENBIOS_MASTER=$(CONFIG_OPENBIOS_MASTER) \

Re: [coreboot] openbios in config?

I agree that downloading at build time shouldn't be a requirement, and that there should be the ability for building on a machine that isn't connected to the internet. So I'd say that it's important for the number of *REQUIRED* downloads at build time to be zero. Adding another payload option

Re: [coreboot] SeaBios serial(RX) is not running.

Hi, If you want bi-directional serial port in SeaBIOS, I think you need to stick with the version from Sage. As far as I know, it's never been supported in the upstream SeaBIOS version. You might want to bring this up on the SeaBIOS mailing list. http://www.seabios.org/Mailinglist Martin On

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Hi Mayuri, As of right now, the coreboot build doesn't have a way to build tianocore/CorebootPayloadPkg into coreboot automatically, but I'm working on integrating it. I had hoped to have my initial push ready last week, but didn't get it finished. That said, it's not difficult to build it

Re: [coreboot] Community Meeting

Hi Rafael, It's added. Please let us know if there's anything we can do to help you get more people involved. Martin On Sat, May 7, 2016 at 12:56 PM, Rafael Machado wrote: > Hi Zaolin > > Would it be possible to add at this calendar the Brazilian timezone ?

Re: [coreboot] sign fsfe radio lock down statement

Hey Lynxis, In general, the feeling is that the coreboot project should stay out of politics if it's not explicitly about coreboot. This issue is probably close enough that we'd at least be interested in hearing more about what the expectations are. I'll send an email to the fsfe campaign

Re: [coreboot] Building with SeaBIOS and serial debugging

Hi Dylan, I'm not sure if you've already figured this problem out, but the CONFIG variables are set by Kconfig and would be in your .config file. Looking at the .config file you posted I have no idea how you're seeing anything coming out on serial from coreboot. The only logging I see is to CBMEM.

[coreboot] coreboot conference in SFO

Hi everyone. I've just sent out an email to everyone who is currently registered for the coreboot conference. If you believe that you are registered and did not get the email, please check with me. Please remember that fees for registration go up $50 after May 1. Additionally, because Apple is

Re: [coreboot] Issue Tracker down?

Hi Daniel, We're seeing the same thing. We'll work to get it back up immediately. Thanks. Martin On Mon, Apr 25, 2016 at 11:24 AM, Daniel Kulesz via coreboot wrote: > Hi, > > I just wanted to report bug regarding memory initialization on the F2A85-M, > but it looks

Re: [coreboot] F2A85-M: Memory issues

Hi Daniel, unless you're using the memtest from the coreboot codebase, the memtest failures are likely false. Try this one - it should work better under SeaBIOS: git clone https://review.coreboot.org/memtest86plus You can also just build it into the coreboot image as a secondary payload in the

[coreboot] coreboot 4.4 release coming soon

Hi Everyone, We're planning on doing the coreboot 4.4 release in the next week or so. We'd like to request some help with testing platforms both ahead of the release and when the release actually happens. If you have a board in the coreboot tree, please try doing a build to help us verify

Re: [coreboot] QEMU with coreboot

Hi Daoud, This page might help: https://www.coreboot.org/Lesson1 Martin On Thu, Apr 14, 2016 at 2:24 AM, Gerd Hoffmann wrote: > On Do, 2016-04-14 at 10:01 +0200, daoud yessine wrote: >> What should I tap to run qemu with coreboot ? > > CONFIG_VENDOR_EMULATION=y >

Re: [coreboot] WG: Alix 2d13 coreboot breaking source

Hi Reto, Sorry, what's the issue that was caused by the toolchain update? It seems like you probably described the issue on IRC, but I missed that and 'broken' doesn't give me much information. Can you file a bug on this with additional information about what the issue is?

Re: [coreboot] coreboot convention, june 13-16, san francisco

Thanks for the reminder Aaron. You can register by filling out this form: http://goo.gl/forms/f8uqHHFL2S Additional information about the conference is on the wiki: https://www.coreboot.org/coreboot_conference_San_Francisco_2016 If anyone has any additional questions about the conference, feel

Re: [coreboot] Cleaning up old commits in gerrit

All of the patches that have not been touched in at least 18 months have been abandoned. Here is the list of patches that were abandoned: https://review.coreboot.org/#/q/status:abandoned+comment:%22touched+in+18+months%22 If you see a patch in that list that you feel should be picked back up,

Re: [coreboot] Linux as payload

You'll want both. The file system is what goes in the initrd config option Add a payload (A Linux payload) ---> (bzImage) Linux path and filename () Linux command line () Linux initrd Martin On Thu, Apr 7, 2016 at 10:31 AM, daoud yessine wrote: > Hi > > how to

Re: [coreboot] Regarding offset adjustment for building coreboot.

Not knowing which platform this is makes it a little harder to determine what's locked in place. We'd also need to know if this is getting built from the top of the coreboot.org tree, an old coreboot.org commit or an private repo with many changes from coreboot.org. Microcode should be able to

Re: [coreboot] Libpayload dies with NMI exception on qemu-q35

Hi Jonathan, What command line are you using to start QEMU? I just tested it and it's working for me, but I'm not getting the USB devices showing up, which may be why it's working. Here's what I used: qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M q35 -smp 2 -m 2G This is from

[coreboot] coreboot consulting

coreboot related issues arise. We currently have five agreements in place, and are in communication with other companies about joining the program. For more information on how to become a coreboot licensed consultant and get your company listed, please contact mar...@coreboot.org Martin Roth

[coreboot] Cleaning up old commits in gerrit

Hi all, We're looking at cleaning up gerrit, so we're planning on abandoning some older commits. To keep from overwhelming people, we're going to do it in stages. Right now we're looking at abandoning all commits that haven't been updated in 18 Months. This is around 90 commits. Please look

Re: [coreboot] IOMMU for AMD APU2 - consulting needed

Hi Jürgen, For AMD work, I'd try Raptor Engineering: https://raptorengineeringinc.com/content/base/main.htm Martin On Thu, Mar 24, 2016 at 5:30 AM, Jürgen Walter wrote: > Hello coreboot people, > > we are looking for a hired hand in helping us getting IOMMU (Xen >

Re: [coreboot] Porting coreboot to the Asus P5G41T-M LX motherboard

boot-for-asus-p5g41t-m-lx/blob/maste > r/superiodump > > https://github.com/rnplus/test-coreboot-for-asus-p5g41t-m-lx/blob/maste > r/superioextradump > > This is the output of superiotool using the OEM BIOS. > > The SIO is configured for 0x2E. > > Greetings, > Renze &

Re: [coreboot] [GSoC 2016] ROM-O-Matic project

Sorry it's taken a while to get back to you on this. The build needs to happen with the correct toolchain to generate a rom that is similar (or identical) to the original rom that was tested in the board status. That would be done with with 'make crossgcc'. If I try to build a rom that was

Re: [coreboot] Logs storage? Was: Target candidate: Dell Latitude E4300

I think that having OEM BIOS logs from supported boards does make a lot of sense, but when I talked to Stefan about it before, he didn't want to add unsupported boards. His thinking was that we didn't want to be the world's largest lspci database, which seems reasonable to me. I'd even support

Re: [coreboot] Missing Coverity reports

Hey Paul, Thanks for bringing this up. We'd definitely like to fix the issues that are identified by coverity. To start looking at issues, sign up for a coverity account: https://scan.coverity.com/users/sign_up After you log in, search for the coreboot project and click the 'Add me to

Re: [coreboot] Memtest86 SPD/DMI popups broken

Do you think we should revert those patches until we can get them fixed? On Wed, Mar 9, 2016 at 11:56 AM, Ben Gardner wrote: > FYI - > > I just tried memtest86 with the popup patches that were added to coreboot. > I'm seeing issues with clearing the background before

Re: [coreboot] On Memtest86+ change sets up for review

. > > I've been sitting on Baytrail support patches. > If you are OK with this being an active branch, I can send those patches > along. > > Ben > > On Mon, Feb 29, 2016 at 3:51 PM, Martin Roth <gauml...@gmail.com> wrote: >> Hi Paul, >> I'm not really i

[coreboot] coreboot convention

Greetings: We are going to hold a 4 day coreboot convention in San Francisco, CA, Monday June 13 - Thursday June 16. Google has agreed to host two very nice conference rooms for those 4 days and we are also working to get a block of rooms in a nearby hotel for a reasonable rate. We plan for two

Re: [coreboot] On Memtest86+ change sets up for review

Hi Paul, I'm not really interested in taking over memtest86+, I'm just creating a repository that we can build from and run as a payload. I originally looked at having the build process download the tarball and apply patches, but once I got up to 10 patches, I opted for starting a repo instead.

Re: [coreboot] [RFC] board-status.git growth

It's definitely an issue, and it's actually something that is currently being looked into. As always, we just need someone to do the work. :) There's a project listed on the project ideas wiki page about this, so maybe we'll get an enterprising person to work on it. If not, we'll probably

Re: [coreboot] RFC: coding style: "standard" defines

I don't think we need redefinitions of TRUE/FALSE Ron's argument against using BIT(16) makes sense to me. I don't have a problem with BIT16, 0x1, or (1 << 16) but #define VENDOR_BIT_16 0x1 seems like overkill. I'd really generally prefer some good definitions though instead of

Re: [coreboot] bootfail on my Mohon Peak CRB.

You might try a different video card. There's an issue in the video bios of the aspeed card that came with the mohon peak. martin On Tue, Feb 2, 2016 at 00:41 김유석 wrote: > Dear sir. > > My ENV is see below. > > *EVB : Intel rangeley Mohon Peak CRB* > > > This time, I was

Re: [coreboot] [RFC] Proposal for policy for changing the development guidelines

discussion, nor > community oversight. This was not a "minor typo fix" or > "clarification". I count three different changes which were made this > way. And I think Paul nailed it with his proposal. > > I fully support Paul's proposal. > > On Sat, Jan 30, 2016 at 6:

Re: [coreboot] [regression] Increased romstage boot time on ASRock E350M1 (AMD Family 14h)

I've been bisecting this today. I see an increase of about 1 second somewhere between commit 35261c0d476ef and commit 730a043fb6c. That's a range of 15 commits On the good commits, I get the boot messages: > APIC: 00 missing read_resources > APIC: 01 missing read_resources > I2C: 00:50 missing

Re: [coreboot] [RFC] Proposal for policy for changing the development guidelines

Alex, Please stop already. We know you don't agree with the decision. Stefan has agreed privately that he shouldn't have submitted those, and that it set a bad precedent. As you say in your email, *YOU* even questioned it when he did it, and he agreed that he would change them from Intel

Re: [coreboot] Building on 64 Bit Linux

Hi Gregg, I'm not sure what tools come installed by default on Slackware, so I can't really say. I'd be happy to try to work out any issues you see and get any special requirements documented. Is there some issue that you're seeing that makes you ask? Martin On Tue, Jan 19, 2016 at 7:19 AM,

[coreboot] Building the toolchain automatically

coreboot already detects whether the toolchain is built, and already has targets to build the toolchain for each individual architecture. It would be trivial to connect these together and simply build the toolchain for the current architecture if it doesn't exist. Is this something that is

Re: [coreboot] [regression] Increased romstage boot time on ASRock E350M1 (AMD Family 14h)

Hey Paul, I can take a look. Martin On Sun, Jan 10, 2016 at 5:40 AM, Paul Menzel wrote: > Dear coreboot folks, > > > on the ASRock E350M1, I lately noticed that the SeaBIOS banner takes > longer to appear. And looking at the logs board status [1], the time >

Re: [coreboot] baytrail + fsp_baytrail

I think we can cut down on some of the code redundancy, but as Alex says, they are different chipsets, and we need to be careful about trying to combine too much. Here are my suggested steps: 1) Look for commonalities between baytrail and other chipsets and move pieces things into

[coreboot] Saved SeaBIOS configuration options for mainboards.

I recently posted a patch that would allow the coreboot build to use a saved SeaBIOS .config file stored in the mainboard directory. The initial reason for this was to replace one existing SeaBIOS configuration option that was in coreboot's Kconfig, and to remove the need for a second option that

Re: [coreboot] CBMEM Console corruption with fsp_baytrail in coreboot 4.2

Hi Ben, I'm still trying to get to this. I don't know if you saw how different the fsp cbmem route is from other platforms. The fsp copies the contents of the car stack to the top of memory when it tears down the cache as ram. The pointer to that gets saved and passed to the cbmem transfer code.

Re: [coreboot] CBMEM Console corruption with fsp_baytrail in coreboot 4.2

Aaron, yeah, I was talking about CBMEM_FSP_HOB_PTR. Obviously if that gets corrupted, things are going to be ugly. Since Ben was talking about the stack getting corrupted during CAR migration, That's what I was thinking might be happening. Maybe it wasn't getting saved anymore, maybe it was

[coreboot] coreboot leadership meeting notes for November 5, 2015

Attendance: --- Stefan, Martin, Aaron, Patrick Agenda: --- * This meeting was initially set up as a consortium meeting. We need to decide if this is a consortium meeting or a coreboot leadership meeting. - It was decided that the meetings are leadership meetings, and that the

[coreboot] coreboot leadership meeting notes for October 29, 2015

The coreboot leadership is making a number of changes to be more open than they have been in the past. Releasing the minutes of the discussions that are being held regularly is another step towards this goal. The first couple sets of minutes are delayed a bit while figuring out the process, but

Re: [coreboot] Removal of AGESA - to be or NOT to be? A story of G505S

Hi Alex, While your numerous contributions to the community are appreciated, it's not ok to troll on the coreboot mailing list. Please stop now. If you feel like you should be reimbursed for your server, you are welcome to stop running it as a coreboot build server. I added a server two weeks

Re: [coreboot] A case for branching AGESA

to the 4.2 branch. Martin On Wed, Nov 4, 2015 at 3:02 PM, Alex Gagniuc <mr.nuke...@gmail.com> wrote: > On Wed, Nov 4, 2015 at 8:09 AM, Martin Roth <gauml...@gmail.com> wrote: >> Let's table the discussion of agesa (and other) platform removal for >> now. > > I didn't talk

Re: [coreboot] [RFC] Time until patches should be submitted (was: Document for review: coreboot Gerrit Etiquette and Guidelines)

> On Tue, Nov 3, 2015 at 1:36 PM, Paul Menzel > <paulepan...@users.sourceforge.net> wrote: >> >> Dear coreboot folks, >> >> >> Am Donnerstag, den 29.10.2015, 12:55 -0600 schrieb Martin Roth: >> > As the community has grown, so has the need t

Re: [coreboot] A case for branching AGESA

Let's table the discussion of agesa (and other) platform removal for now. As Patrick said in the 4.2 release announcement, a plan for the removal of code is being written and will be posted for discussion shortly. Martin On Tue, Nov 3, 2015 at 12:58 PM, Timothy Pearson

Re: [coreboot] setting up a bug tracker

I'm good with redmine, and if Lynxis is going to be the administrator, I think it's reasonable that he should be able to decide in what he's going to be working on. I had done some looking and thinking about before Lynxis offered to set up redmine, so I'll still present those items. These were

Re: [coreboot] Dell Dimension 8300 reboots when grub2 cbfs module is loaded

Thanks Andrei, Vladimir, what do you think? Martin On Sun, Nov 1, 2015 at 7:53 AM, Andrei Borzenkov wrote: > I was debugging problem reported by user on Dell Dimension 8300 - it > rebooted when doing "ls -l". It turned out, the problem was triggered by > loading cbfs which

Re: [coreboot] Document for review: coreboot Gerrit Etiquette and Guidelines

Hi Alex, Thanks for voicing your concerns. I do think that most of the issues you bring up are handled, or aren't as big issues you make them out to be. As always, I could be wrong, so I'd again invite others to give their opinions. I've tried to address your issues below. > ... the

[coreboot] Document for review: coreboot Gerrit Etiquette and Guidelines

As the community has grown, so has the need to formalize some of the guidelines that the community lives by. When the community was small, it was easy to communicate these things just from one person to another. Now, with more people joining the community every day, it seems that it's time to

Re: [coreboot] Proposal: Removing obsolete & EOL boards and chipsets for 4.2 release

It seems that we've got more issues than we can address before the proposed 4.2 release date within the next few days - we're trying to get this out in October. Maybe it's time for another 'Major' release where we can remove more than just the few mainboards and truly obsolete code that I was

Re: [coreboot] Proposal: Removing obsolete & EOL boards and chipsets for 4.2 release

The current thought is to create a new branch for 4.2, *THEN* remove the decided upon code from the master branch. This removes the maintenance work on master going forward while providing a known point if someone wants to pick up the boards going forward. I don't understand the question about

Re: [coreboot] SPD binaries in coreboot

I don't think it's really very similar at all. The bootblock output can change drastically based on Kconfig settings. Am I missing something? On Fri, Oct 23, 2015 at 10:59 AM, Nico Huber <nic...@gmx.de> wrote: > On 23.10.2015 18:32, Martin Roth wrote: >>> So, is there a thi

Re: [coreboot] SPD binaries in coreboot

> So, is there a third option that I'm missing? Other opinions? >> > The third option would be a plain text format which is easy to parse >> > but still covers the spec well. I'd say that we should store the SPDs as binaries - these are easy to use at build time, and there's no reason to build

Re: [coreboot] SPD binaries in coreboot

I like what I understand Nico's proposal to be: Store the SPD data as a c struct with all of the different JEDEC fields broken out. it would relatively trivial to compile this into an SPD binary, or it can be used in whatever other fashion is desired. A tool to convert from a binary SPD to the

Re: [coreboot] GPL license headers

I haven't seen any disagreement that we get rid of the entire third paragraph. Alex votes that we should get rid of the second paragraph of the header as well, and what Ron posted SEEMS to support that we can, although the wording in that license header might be different enough that it doesn't

Re: [coreboot] intel atom e3815

Hi John, coreboot does support the E3815 (Bay Trail I) with the Intel FSP. The tree is a little broken for it right now, but we're working to get it fixed. The primary example for that chip is the Minnowboard Max. A couple of resources to get you started: - http://intel.com/fsp - There are a

[coreboot] Syntax Highlighting for ACPI ASL, devicetree.cb and Kconfig files

I've just posted syntax highlighting files for ASL, Kconfig and devicetree.cb for a few editors if anyone wants to try them out. vim: ASL - https://github.com/martinlroth/vim-acpi-asl devicetree.cb - https://github.com/martinlroth/vim-devicetree Kconfig is alredy supported in vim. atom: ASL -

Re: [coreboot] memtest86 reading 0k memory

On 04/08/2015 08:45 PM, Kevin O'Connor wrote: On Wed, Apr 08, 2015 at 10:55:18PM +0200, Stefan Tauner wrote: On Thu, 19 Feb 2015 10:43:44 -0500 Kevin O'Connor ke...@koconnor.net wrote: On Wed, Feb 18, 2015 at 10:26:21PM +0100, Stefan Reinauer wrote: * Timothy Pearson

Re: [coreboot] VGA doesn't work on Mohon Peak

My experience is that the aspeed chip based graphics card that comes with Mohon Peak has a bug in the vbios causing it to hang when run. If you need to use this specific card, you'll need to debug it, probably with a jtag debugger, going through the assembly, and see what's causing the issue. My

Re: [coreboot] Mohon Peak, Memtest86+ does not start

Hi Viktor, SeaBIOS serial console is currently output only. Someone would need to add a change to read from the serial port and stuff the value into the keyboard buffer or something similar for it to be bi-directional. I know that Sage has already done this, but I don't believe that it

Re: [coreboot] SeaBIOS wit USB3.0 hub and USB3.0 devide behind the hub

Hi May, I just wanted to expand on your finding. On Rangeley, the USB buffers MUST be pushed low because the USB controller isn't allowed to write into the 0xe - 0xf area. The processor is the only device that can write to that area. The restricted area might be larger - I can't

Re: [coreboot] SeaBIOS, serial output, grub, sgabios does not seem to load

Hi May, you might have already gotten past this, but I thought I'd comment. The codebase you're working from is intel's proof of concept implementation. I don't remember if they have the MRC cache enabled. For Rangeley/Avoton platforms though, saving and restoring the MRC cache required,

Re: [coreboot] SeaBIOS, serial output, grub, sgabios does not seem to load

get building it yourself. Martin On 01/12/2015 01:50 AM, Kuzmichev Viktor wrote: On 11.01.2015 07:45, Martin Roth wrote: On 01/10/2015 07:53 AM, Kevin O'Connor wrote: On Thu, Dec 25, 2014 at 11:45:40AM +0300, Kuzmichev Viktor wrote: Hello, I've been trying to boot grub installed on the hard

Re: [coreboot] SeaBIOS, serial output, grub, sgabios does not seem to load

On 01/10/2015 07:53 AM, Kevin O'Connor wrote: On Thu, Dec 25, 2014 at 11:45:40AM +0300, Kuzmichev Viktor wrote: Hello, I've been trying to boot grub installed on the hard drive using coreboot and SeaBIOS as a payload. The motherboard I'm using is Intel Mohon Peak. Also, I do not use VGA for

Re: [coreboot] PCIe PME vs ACPI Interrupt

Hi Gailu, Sorry, wake on lan wasn't tested during the Bayley Bay development, so something was probably missed. I'm doing some baytrail work right now, so I might get around to looking at it and pushing a change, but I can't make any guarantees about when or if that might happen. Regards,

Re: [coreboot] 答复: questions about Rangerley

for file or introduction. That will be great. Thanks a lot for support. Best Regards, Jack Zhao +86-21-58966996-81122 -邮件原件- 发件人: Martin Roth [mailto:gauml...@gmail.com] 发送时间: 2014年12月5日 12:01 收件人: Jack Zhao; coreboot@coreboot.org 主题: Re: [coreboot] questions about Rangerley Hi Jack

Re: [coreboot] questions about Rangerley

Hi Jack, The Rangeley processor is supported by coreboot. The intel/mohonpeak is the reference board. You will need to download the FSP from http://intel.com/fsp While there isn't a platform guide for rangeley yet, you would follow similar steps to setting up coreboot for the baytrail

Re: [coreboot] Baytrail SD card interface

Wen, I'll push a patch for the muxing - I'd been meaning to do this and just got behind. I don't believe that SeaBIOS yet supports boot from SD (without a USB translator). Sage pushed a preliminary patch supporting SD boot on specific platforms to the SeaBIOS mailing list a while

Re: [coreboot] S3 support in BayleyBay FSP

Hi Mohan, S3 suspend/resume support still needs to be added. This is the first of the FSPs that supported S3 suspend/resume. If you're actually interested in adding S3 support for baytrail-I, I'd be glad to give you a list of what I know that needs to be done and work with you to get it

Re: [coreboot] BayleyBay FSP booting

Tuan, Sorry - I've been on vacation and missed this thread until now. What Wang Fei suggested is exactly right - you need to start with a different BIOS flashed on the board.. The problem is the Descriptor/TXE that is being used. Intel has said that they would update the build instructions

Re: [coreboot] coreboot hackaton/meeting in Prague - september 2014 - date shift?

Hi Rudolph, The new dates sound good. Martin On 07/01/2014 12:04 AM, Rudolf Marek wrote: Hi all, What about 16 17 18 19 of October then? It is already in the university semester so there could be trouble with dormitory accommodation, but I think no trouble with some room @university. I

Re: [coreboot] Current master broken on ASRock E530M1 (AMD Fam14/SB800)

Hi Paul, I'll test it out and work with Mike to get it working again. Martin On 07/04/2014 01:03 AM, Paul Menzel wrote: Dear coreboot folks, I’ll have to check again, but going from commit 2093c4f (AMD/agesa: Add functions for AMD PCI IRQ routing) [1] to commit 6a089e3 (AGESA boards: Use

[coreboot] source of coreboot boot log for board-status database

I've added a routine to grab the boot log for the board-status database from a serial device. I didn't realize at the time that it had already been voted down on the mailing list - I was told that if I wanted this to go in, I should appeal to the mailing list. Please see the patch here:

Re: [coreboot] latest baytrail fsp on CRB

If we figure out why we see the device id of 0x for the SOC transaction router, I'd really like to understand that. I had initially thought it was a B0 vs B3 issue, but I've heard from people that it happens on the B3 silicon as well. Currently if the device id comes up as 0, the

Re: [coreboot] latest baytrail fsp on CRB

Hi, I'm getting ready to push some code that better aligns things between the Kconfig option and the FSP for the MMIO configuration area. It shouldn't be a problem after that. Martin On 06/20/2014 01:17 PM, Karl-Heinz Nirschl wrote: hi, i did some experiments with the baytrail fsp coreboot

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