Re: [coreboot] Debug builds and memory testing

How u resolved memory issue? From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Naveed Ghori Sent: 31 May 2016 06:52 To: coreboot Subject: Re: [coreboot] Debug builds and memory testing To update this: There are option in the menuconfig to enable various

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry= 0x008002c0 lb_start = 0x0010 lb_size = 0x00035650 buffer = 0x7ac34000 Regards Mayuri From: Mayuri Tendulkar Sent: 17 May 2016 14:13 To: 'Zoran Stojsavljevic' <zoran.stojsavlje...@gmail.

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Can anybody help here? Do we have UEFI payload changes for Minnowmax available? From: Mayuri Tendulkar Sent: 18 May 2016 10:27 To: 'Zoran Stojsavljevic' <zoran.stojsavlje...@gmail.com>; 'coreboot@coreboot.org' <coreboot@coreboot.org> Subject: RE: [coreboot] UEFI Payload in corebo

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

8002c0 lb_start = 0x0010 lb_size = 0x00035650 buffer = 0x7ac34000 From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 20 May 2016 10:44 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com>; coreboot <coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Hi Zoran Sorry, but I am not able to understand what you have mentioned. Can you please help me explain little detail? Sorry, but I am new to this coreboot environment. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 20 May 2016 13:39 To: Mayuri Tendulkar

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 21 May 2016 12:47 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com> Cc: coreboot <coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Mayuri, > Zoran writes in last email: &

[coreboot] Query regarding coreboot for new intel customized board

Hi team I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB. As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx

Re: [coreboot] Coreboot image and seabios payload with debug symbols

jsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 10 May 2016 23:15 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com> Cc: coreboot@coreboot.org Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Few questions, may I? [1] When you do refer to "Intel sys

Re: [coreboot] Coreboot image and seabios payload with debug symbols

Hi Zoran Can you please update on this? Can we build using debug FSP and gdb enabling? Regards Mayuri From: Mayuri Tendulkar Sent: 11 May 2016 10:02 To: 'Zoran Stojsavljevic' <zoran.stojsavlje...@gmail.com> Cc: coreboot@coreboot.org Subject: RE: [coreboot] Coreboot image and seabios p

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 16 May 2016 21:04 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com>; coreboot@coreboot.org Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay OK, Mayuri, You brought an interesting

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

...@gmail.com] Sent: 16 May 2016 20:43 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com> Cc: Zoran Stojsavljevic <zoran.stojsavlje...@gmail.com>; coreboot@coreboot.org Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi Mayuri, As of right now,

Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 16 May 2016 17:57 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com> Cc: coreboot@coreboot.org Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, You should check p

[coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and

Re: [coreboot] Coreboot image and seabios payload with debug symbols

Hi Zoran I am having Intel system studio trial version and also XDP3 connector. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 12 May 2016 17:31 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com>; coreboot@coreboot.org Subject: Re: [coreboot] Co

[coreboot] Serial prints not coming on Minnowboard Turbot

Hi I have built coreboot using Minnowmax config file in coreboot with seabios payload. I don't see any serial console prints. Can you please confirm what could be the issue? If I flash Minnowboard Max file given on intel site, everything works fine and I see UEFI shell prompt. Regards

[coreboot] Coreboot image and seabios payload with debug symbols

Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this

[coreboot] Query to release the code for new board

Hi Team I would like to know how process of releasing code for new board works in coreboot community? For example, when BayleyBay CRB or Minnowboard Max was release, is it only code changes released, mainly related to Mainboard. How TXE and Descriptor.bin for these openly available boards are

[coreboot] USB3.0 enumeration in Baytrail E3845 with coreboot

Hi I am facing issue in enumerating USB3.0 device on baytrail processor with coreboot with seabios. Is there any setting in coreboot where we need to enable this separately. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual

Re: [coreboot] USB3.0 enumeration in Baytrail E3845 with coreboot

t At least, you can do lsusb --h to see options which can help you to start debugging this issue. Zoran On Wed, Aug 3, 2016 at 11:23 AM, Mayuri Tendulkar <mayuri.tendul...@aricent.com<mailto:mayuri.tendul...@aricent.com>> wrote: Hi I am facing issue in enumerating USB3.0

Re: [coreboot] Help on setting clock speed in coreboot

comes up and directly shows payload is loaded, so not able to get whats happening before that. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 13 July 2016 10:43 To: Naveed Ghori <naveed.gh...@dti.com.au> Cc: Mayuri Tendulkar <mayuri.tendul...@ar

Re: [coreboot] TXE and Descriptor bin management in Coreboot

is booting based on current, but display doesn't come up. -Original Message- From: Martin Roth [mailto:gauml...@gmail.com] Sent: 13 July 2016 15:36 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com> Cc: coreboot <coreboot@coreboot.org> Subject: Re: [coreboot] TXE and De

[coreboot] TXE and Descriptor bin management in Coreboot

Hi Team I would like to know how we can handle TXE and descriptor bin in Coreboot? Is there any generic file for Intel processors which can be used rather than any proprietary bin files? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of

Re: [coreboot] Help on setting clock speed in coreboot

[mailto:naveed.gh...@dti.com.au] Sent: 11 July 2016 20:03 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com>; coreboot <coreboot@coreboot.org> Subject: Re: Help on setting clock speed in coreboot First thing is to get serial output as there will probably be other hurdles before the display w

[coreboot] Help on setting clock speed in coreboot

Hi Team I have a customized board based on Intel valley island design. Reference design uses Intel Baytrail processor E3825, while my design is using E3845. I am customizing coreboot for this E3845, but getting just garbage on coreboot, so not able to debug where it is stuck. When I add

Re: [coreboot] Help on setting clock speed in coreboot

Thanks. We tried 115200, but it didn't work. We checked TTL levels and tried to match, but no luck. Are you using PCU UART (same as minnowboard) or anything different? From: Naveed Ghori [mailto:naveed.gh...@dti.com.au] Sent: 11 July 2016 18:17 To: Mayuri Tendulkar <mayuri.tendul...@aricent.

[coreboot] SVID interface support on Intel Baytrail

Hi In our design, we are using SVID interface on Intel Baytrail for accessing PMIC. But in coreboot, we don't see any support enabled for this interface for Baytrail. Does anybody have idea how to access this interface? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is

Re: [coreboot] SVID interface support on Intel Baytrail

We want to access this from Linux kernel Ubuntu 14.04.5 From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 01 February 2017 14:33 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com> Cc: coreboot <coreboot@coreboot.org> Subject: Re: [coreboot] SVID interface supp

Re: [coreboot] SMBIOS table enablement in coreboot

Hi David Thanks for response. So are there any other settings which enable Type 17 i.e. DDR data information in SMBIOS? We don’t see this Type 17 information in our table. Regards Mayuri From: David Hendricks [mailto:dhend...@google.com] Sent: 18 January 2017 01:58 To: Mayuri Tendulkar

Re: [coreboot] SMBIOS table enablement in coreboot

We are using coreboot 4.4 only, because when I do dmidecode – t 0, its showing me bios version as 4.4-573. Still type 17 doesn’t come up. How we can access DIMM information from HOB? From: cheng yichen [mailto:blessyic...@gmail.com] Sent: 25 January 2017 15:35 To: Mayuri Tendulkar

[coreboot] USB 2.0 test pattern support on Bayley Bay

Hi Team We are trying to do the eye pattern test on USB2.0 on Bayley Bay board. But we are not able to see the test pattern support from BIOS side. Do we have any settings in coreboot to enable this? This works fine on any Linux laptop/desktop Regards Mayuri "DISCLAIMER: This message is

[coreboot] Any changes to coreboot for low latency kernel

Hi I have below 2 queries: 1)Do we need to do any changes in coreboot to support low latency kernel? 2) Is there a way to communicate from SeaBIOS to GRUB regarding selection of any particular partition for recover? 3)Has anybody tested TPM (Trusted platform module for Intel SOC) with

[coreboot] Intel EMT/RMT tool with Coreboot

Hi Team I am exploring usage of Intel memory related tools with coreboot for Intel BayTrail processors. As per their guide, it works on Valley View BIOS with some MRC settings. Has anybody explored on this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended

[coreboot] SMBIOS table enablement in coreboot

Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode -t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is

Re: [coreboot] SMBIOS table enablement in coreboot

NAME="" Regards Mayuri From: David Hendricks [mailto:dhend...@google.com] Sent: 14 January 2017 08:19 To: Mayuri Tendulkar <mayuri.tendul...@aricent.com> Cc: coreboot <coreboot@coreboot.org> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, Do you hav

[coreboot] Re: Caby lake support

Thanks for quick response. I see below release- this support is added. https://coreboot.org/releases/coreboot-4.8.1-relnotes.txt Is there any reference board used with this chipset , which can be referred as some POC? From: Angel Pons Sent: 20 February 2019 15:55 To: Mayuri Tendulkar Cc

[coreboot] Caby lake support

Hi Team Is there support for Intel Cabylake chipset in latest coreboot? [cid:image001.png@01D4C934.5B4BE590] Regards Mayuri = Please refer to http://www.aricent.com/email-disclaimer for important disclosures regarding this electronic