I experienced problems with a non working ethernet interface on my x230.
The reason was that I accidentally touched the embedded controller
region. The EC participates in setting the ethernet interface up.
So if I were you I would check if I flashed the regions correctly.
The best way is to
I experienced problems with a non working ethernet interface on my x230.
The reason was that I accidentally touched the embedded controller
region. The EC participates in setting the ethernet interface up.
So if I were you I would check if I flashed the regions correctly.
The best way is to
Am Montag, den 16.09.2019, 07:20 -0700 schrieb Stefan Reinauer:
> Yes, this is often done as a cost reduction method. The habit started
> with the arrival of the ME and the firmware descriptor allowing you
> to spread your different firmware regions across one or both chips.
Hm, surprises me.
Hi folks,
Platforms like the x230 have two flash ROMs which are virtually treated
as a single one.
So:
1. What the heck is the meaning of this? Why do vendors buy and solder
two small chips (even worse, on the x230, one with 8M and one with
4M) instead of a single big one? Is this
Am Donnerstag, den 27.06.2019, 11:55 +0200 schrieb Vinzenz Vietzke:
> maybe some of you have already seen it in common Linux online media.
> We are currently looking for Coreboot developers.
> More about this also at:
> https://www.tuxedocomputers.com/en/Infos/Jobs/Software-Developers-
>
Recently I had an interesting discussion with a system administrator
who is responsible for several hundred PCs, Routers etc.
His argument was: Imagine it would take you 15 minutes to install a
patch on a computer (all windows machines of course...). If your
company has 1000 computers and you
Am Sonntag, den 28.10.2018, 15:55 +0100 schrieb Luc Verhaegen:
> Ooh, bait, on a sunday afternoon with nothing better to do. I'll
> bite.
>
> Matrix is not even 4 years old.
>
> IRC has been good around for just over 3 decades. Many here have
> been
> using it for more than 2 already. Yes, 2
Am Sonntag, den 28.10.2018, 16:45 -0500 schrieb Timothy Pearson:
> More importantly, choose your own application. There are so many
> good
> choices for desktop-side IRC clients at this point that almost
> certainly
> any older developers have already settled on one. Forcing us to
> switch
>
Hey,
have you guys already heard of Matrix?
https://matrix.org/blog/home/
It's some sort of modern IRC, using JSON to format messages. It's more
modern than IRC. Features are:
* Source code formatting and highlighting in messages
* multiple devices
* history + history synchronization between
Am Samstag, den 13.10.2018, 10:27 -0700 schrieb ron minnich:
> good summary.
>
> The most security critical code gets the least attention and no
> external security review.
>
> If this sounds crazy, well ... it is.
I honestly don't think that matters at all. Worrying about crappy BIOS
code
Am Mittwoch, den 10.10.2018, 11:01 + schrieb Peter Stuge:
> We do however know what consequences said (firmware) architecture
> have
> for coreboot, both the good and the bad.
What's the good?
--
coreboot mailing list: coreboot@coreboot.org
Hey Nico,
Am Sonntag, den 07.10.2018, 22:56 +0200 schrieb Nico Huber:
> At least since I'm working on the project it was always like this.
> And,
> IMHO, it is a good thing. The only decent x86 coreboot code I know
> was
> written when Intel didn't have their fingers in the pie.
Do the Intel
Am Samstag, den 06.10.2018, 07:50 +0300 schrieb Zvi Vered:
> Currently, in order to replace vendor's BIOS we must take binary
> parts
> of the original bin file and then stitch it to coreboot.rom built
> with
> the coreboot project.
Well, exactly. Why do you think that is? Intel won't give you or
Am Mittwoch, den 29.08.2018, 04:09 -0400 schrieb Youness Alaoui:
> If there are more specific questions that you have, ask them and I
> might be able to answer them!
I might have one: What does stop a motherboard-vendor from just buying
a CPU and implementing it? Which chips, beside the CPU, do
You should include some more details:
* Used Hardware
* Configfile
* Does anything happen when pressing ESC?
* What does "is not installing OS" mean exactly?
Am Montag, den 09.07.2018, 20:06 +0530 schrieb Dhanasekar Jaganathan:
> Hi All,
>
> After including Seabios as a primary bootloader in
Am Montag, den 26.02.2018, 17:14 -0300 schrieb Sumo:
> Hi,
>
> In the coreboot build menu there is no option regarding the Intel ME
> integration.
> The 'coreboot.rom' file is the full SPI flash image or this file is
> suitable to
> replace the BIOS region of the SPI flash
I don't get it, too. ME has nothing to do with what you can do with your
machine and what it can perform.
Even if 90% of users use their machine for multimedia purposes...
Am 24. Dezember 2017 14:02:41 MEZ schrieb eche...@free.fr:
>Yes Peter
>But what has Netflix (or Sony, or the
Am Freitag, den 22.12.2017, 15:31 +0100 schrieb Nico Huber:
> Hi Zoran,
>
> please stop sending HTML emails. Your mails are often very hard to
> view. Especially the quotations are completely messed up by your MUA
> when you play with the font settings.
Afaik it's possible to configure
Thanks.
They didn't seriously include a Java Runtime Environment into the IME??
I can't believe what's going on with this company.
Am Freitag, den 08.12.2017, 16:16 +0100 schrieb Thomas Heijligen:
> For those who are interested in the Intel ME, the slides and white
> papers
> from the Black Hat
> So, where do we stand on support for UEFI (Tianocore?)
Hmm, what does UEFI have to do with it?
> Can I use the same build for both X230 and X230T? What else
> would I miss?
AFAIK the Tablet doesn't need firmware-initialization. At least Vitali
Serbinenko mentioned [1] that the builds for X220
Am Sonntag, den 29.10.2017, 23:28 +0800 schrieb Tom Li via coreboot:
> Do you ever encountered a problem like this? What is your suggestion
> for me
> to try before replacing the motherboard?
>
> Cheers,
> Tom Li
Just to be absolutely sure:
Did you make sure the Intel ME is in place and
Am Montag, den 25.09.2017, 09:17 +0200 schrieb Paul Menzel:
> First, please just sent plain text messages to mailing lists.
Afaik list-servers can be configured to filter HTML. Doesn't the cb-
Server implement this on purpose?
P.
signature.asc
Description: This is a digitally signed message
Am Donnerstag, den 07.09.2017, 04:30 + schrieb ron minnich:
>
> very closed system with RISCV very easily. RISCV doesn't magically
> take
> away ME- and PSP-like problems.
But it will magically take away microcode and maybe compatibility-modes
– what will already be a progress. Both in
Am Montag, den 04.09.2017, 20:15 + schrieb Peter Stuge:
> legacy
> tables such as ACPI
ACPI is a open standard, isn't it?
>
> The payload directly reads the filesystem from disk, no boot sector
> is used.
Indeed. So a payload built for cb won't try to call BIOS. And if
something after it
Thanks so far. Very interesting.
Am Montag, den 04.09.2017, 07:28 + schrieb Peter Stuge:
>
> coreboot itself can only start one payload, but SeaBIOS allows the
> user to choose which of those payloads to start, in which case a
> payload *does* have interrupt services available.
>
> Just to
Am Samstag, den 02.09.2017, 12:36 + schrieb Peter Stuge:
>
> Sure, but a payload can. SeaBIOS aims to provide a complete BIOS with
> all neccessary interrupt services for legacy compatibility.
Once coreboot jumped into SeaBIOS-code the latter is responsible for
providing the right interface
Hi,
Don't worry, x86 is hard to understand IMO. I often feel like an
archaeologist when trying to understand it.
Am Sonntag, den 03.09.2017, 00:32 +0200 schrieb
ingegneriafore...@alice.it:
> is there a way to disable this BIOS function? More precisely,
> coreboot can be set to avoid receiving
Am Donnerstag, den 03.08.2017, 12:48 + schrieb Peter Stuge:
> Philipp Stanner wrote:
> > Why would I want to address memory in RM with 32 Bits? I don't see
> > any difference to using PM without Paging enabled.
>
> In a bootloader (after coreboot) you often want to
On 30.08.2017 14:54, Peter Stuge wrote:
Compatibility is the only actual value of x86.
Hi,
I was often wondering why they don't at least try to get rid of the
*very* old stuff when it's not possible to get rid of the middle-old stuff.
It's understandable that it's necessary to provide a
Am 29.08.2017 um 20:15 schrieb Timothy Pearson:
> On 08/29/2017 06:10 AM, Rene Shuster wrote:
> > Wow.
>
> My favorite part is where the NSA itself basically admits that the ME
> can't be trusted! I wonder if they are looking at other architectures
> or if this HAP bit was enough for their needs?
Am 07.08.2017 um 23:50 schrieb taii...@gmx.com:
How can the end-user documentation be improved?
Hey. Great that you're interested in this special task.
For me as a non-contributing user much trouble occurs when trying to
build anything beside SeaBIOS (Grub and FILO especially). Maybe a
Do we have any idea what exactly they do to update the firmware internally?
The wiki says once coreboot is flashed you can flash it internally. I
suppose this means the blockade protecting the flash can be switched of
somehow, as the vendor's have to do it to install firmware-updates.
Am
Yes, you're probably right.
Though I wonder when and how they programmed the firmware. Before or
after soldering?
Am 05.08.2017 um 19:41 schrieb Igor Skochinsky via coreboot:
> Hello Philipp,
>
> Saturday, August 5, 2017, 6:01:04 PM, you wrote:
> PS> PS: Rantmode: Why the hell don't they just
Dear Patrick, dear Zoran & List,
thank you, this was *very* helpful. I had some misunderstandings
regarding function and features of the CPU-modes.
Let me sum it up again and feel free to correct further mistakes.
* 16-Bit-Real Mode: No virtual memory, no segmentation. 2^20 addresses
of
On 01.08.2017 16:49, Peter Stuge wrote:
Note that PM != paging. Neither coreboot nor proprietary BIOS
products used paging traditionally. Ron pushed for paging, there was
a bit of support. I don't know the current situation though.
Also note that PM != "flat real mode" or "32-bit real mode",
Philipp Stanner <stan...@posteo.de>:
1. cb switches the CPU immediately to Protected Mode, yet Payloads like seaBIOS
work in Real Mode. Does coreboot switch the CPU always back to RM before
jumping to the payload?
No, payloads are started in pmode.
2. When CB switches to PM - who gen
Dear folks and techpriests,
the more I want to contribute and learn about low-level-code the less I
understand, it seems.
1. cb switches the CPU immediately to Protected Mode, yet Payloads like
seaBIOS work in Real Mode. Does coreboot switch the CPU always back
to RM before jumping to
Dear Vincenco,
coreboot is extremely architecture dependent. It's hardcore low-level
code, maybe lower than the Operating System (or Windows) itself.
You can configure the makefile for your platform using menuconfig or
kconfig. De facto Lenovo's thinkpads are the only customer-IT-devices
which
hi,
I can build cb+FILO and cb+seaBIOS, but I can't build it with grub (what
would be my favorite payload as I don't need bios calls and don't want
to flash an entire kernel).
I'll attach the build-protocol. Any ideas what the problem is?
Philipp
CC
, Arthur Heymans wrote:
Philipp Stanner <stan...@posteo.de> writes:
Hi,
where (which code file) does coreboot set the DRAM-refresh-rate and
how easy is it for me to change it?
That would be in raminit, which is platform specific. So it depends on
readability of that code whether it's easy t
Hi,
where (which code file) does coreboot set the DRAM-refresh-rate and how
easy is it for me to change it?
A higher refresh rate will decrease the performance but increase the
protection against Rowhammer.
// Philipp
--
coreboot mailing list: coreboot@coreboot.org
> Coreboot on brand new laptops isn't actually coreboot like it used to
> be, it has been reduced to a pathetic vestige of its former self -
> simply a shim loader layer that does next to nothing besides get the
> purism phonies all excited for a "free" firmware laptop.
Could I get some details
hardware may be honorable, but my personal
believe is that efficiency is more important to people.
Am 30.01.2017 um 23:09 schrieb Timothy Pearson:
> On 01/30/2017 02:12 PM, Philipp Stanner wrote:
> > I'm primary interested in it because of faster booting speed and in
> > general
computer is the X60.
But isn't this whole privacy issue more a topic for libreboot?
Am 30.01.2017 um 19:18 schrieb Timothy Pearson:
> On 01/30/2017 10:53 AM, Philipp Stanner wrote:
> > I'm going to buy a new laptop soon (has to have a touchscreen) and am
> > considering buying one
I'm going to buy a new laptop soon (has to have a touchscreen) and am
considering buying one which supports coreboot.
Which model would that be?
>From what the wiki tells me The X220 is supported best, thanks to
Vladimir, but also the X201 is listed in the green area.
The wiki lists some
Could coreboot (or parts of it) be written in C++?
What would be the advantages and disadvantages?
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
That's a wise decision.
If you'd ask me I would also think about creating a coreboot-forum. It
would make certain diskussions more clear than the mailing list,
especially if they last longer than a few days.
Am 07.01.2017 um 08:42 schrieb Patrick Georgi:
> Hi all,
>
> we've set up a mattermost
By the way:
Is it true that coreboot consumes more power ( = shorter battery life)
than vendor bios?
Am 01.12.2016 um 18:04 schrieb ron minnich:
> what's the latest best one? What's the battery life like (can't be
> worse than this mac pro that's always hot and now seems to have a
> life of 90
:19 schrieb Nico Huber:
> Hi Philipp,
>
> On 09.11.2016 09:46, Philipp Stanner wrote:
>> Hi,
>>
>> I'm currently busy making cb+grub running. While I can boot successfully
>> (qemu) using the grub-shell I of course want to automatize this process.
>>
>> Bu
Hi,
I'm currently busy making cb+grub running. While I can boot successfully
(qemu) using the grub-shell I of course want to automatize this process.
But how and where do I have to put the grub.cfg file? The wiki doesn't
include much informations about this.
I would appreciate if someone could
The wiki-article lists several issues, primary:
* Most times after suspend an EC IRQ hangs in the queue and all
functions keys stopped working until cold boot.
* *Commit 456f495d broke USB and PCI-E* (unable to boot from live ISO
on USB), a hard reset to commit a3e41c08 fixed the boot
Sure: Do the following:
1. qemu-img create test.img 10G
2. qemu-system-x86_64 -enable-kvm -hda test.img -cdrom ubuntu.iso -boot
d -m 512
3. Install ubuntu on test.img
After installing, boot the new virtual machine with your self-build bios:
* qemu-system-x86_64 -enable-kvm -hda
Hi,
according the first problem I've already created a ticket. I (and others
in IRC) failed building rom-images using nconfig+make with other
payloads than seabios. See the txt-files in the ticket system; make
reports something like: "Rule for filo unkown".
The second problem is that a
Is it possible to activate virtualization in the CPU somewhere?
greetings
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
Hi cb-community,
as everyone who owns a computer can subscribe to the list and there is
no coreboot-forum, I presume that I'm allowed to ask a few primitive
questions about the topic :)
1. Coreboot+Payload are only used to initialize the hardware and then
give the complete control over the
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