Hi Sumo,
Thanks for your reply.
As mentioned in my previous mail,.
There are two different fixes which are required for c3558.
a.) The SPEED STEP needs to enabled separately.
b.) APIC id has to be changed under the device tree.
Thanks,
Nitin.
___
Hi Nico,
Nico Huber wrote:
> Hi Nitin,
>
> On 11.06.20 18:44, nitin.ramesh.singh(a)gmail.com wrote:
> > Flash start -> 0xFC00 (with-in 4GB space
> > @4227858432)
> this is misleading. Setting it in the FMAP makes sense to make the
> calculations work, but the flash is not mapped there.
>
Hi,
I am trying to build a Coreboot for a Flash Size as 64 MB, with 32MB reserved
for a BIOS region.
I have modified the descriptor for a bios region:
0200:03ff bios
The fmap used for the given setting is as follows:
FLASH@4227858432 0x400 {
BIOS@33554432 0x200 {
Hi Paul,
As far as cpu init is concerned, I haven't modified the cpu initialization
sequence for the given board. The code is located under following sub-folder
"src/soc/intel/denverton_ns/cpu.c".
The given CPU (CPU C3558) has 4 cores, and I am noticing the following logs
while booting up,
HI Paul,
I have tried different measures to increase the load on CPU, but still the
frequency reflects the same value ie. 800Mz.
My question is why this behavior is different w.r.t the one when system boots
up with BIOS.
When I boot with BIOS, I can see that frequency output stays at 2200Mhz.
Hi Mariusz,
I tried running the stress test to increase the load average, but still the
frequency stays at 800Mhz.
Thanks,
Nitin.
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org
Hi,
I am using coreboot to boot Denverton cpu (CPU C3558) based board.
I can see that the cpu frequency is set to the correct value i.e. "2200 Mhz"
under the coreboot logs.
.
"
CPU #3 initialized
bsp_do_flight_plan done after 146 msecs.
cpu: frequency set to 2200
"
Later when I check the
Hi Mariusz,
Thanks for your reply.
I will try out with the given settings.
Is there is a new release happening for (coreboot denverton_soc) ?
Regards,
Nitin.
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to
Hi All,
Can anyone help me regarding the instructions to build coreboot 4.11 release
for Harcuvar platform.
I am not able to see the microcode, FSP_T and other settings in make menuconfig
(for the Harcuvar platform).
I am already using the settings suggested under the doc
9 matches
Mail list logo