[coreboot] Re: Regarding Intel CPU frequency.
Hi Sumo, Thanks for your reply. As mentioned in my previous mail,. There are two different fixes which are required for c3558. a.) The SPEED STEP needs to enabled separately. b.) APIC id has to be changed under the device tree. Thanks, Nitin. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Change Romsize and CBFS size.
Hi Nico, Nico Huber wrote: > Hi Nitin, > > On 11.06.20 18:44, nitin.ramesh.singh(a)gmail.com wrote: > > Flash start -> 0xFC00 (with-in 4GB space > > @4227858432) > this is misleading. Setting it in the FMAP makes sense to make the > calculations work, but the flash is not mapped there. > > Because of other fixed resources below 0xff00, the architectural > limit of memory-mapped flash space is 16MiB. Some chipsets even limit > the mapping to 8MiB. Without making changes to coreboot code (e.g. > switch from memory mapped flash access to using the SPI controller), > all coreboot regions have to fall into the memory mapped space. > I am aware about the given fact... just wanted to describe the way fmap is being arranged. https://www.coreboot.org/Developer_Manual/Memory_map > > Can any one please let me know what are the other > > changes required to incorporate the Coreboot image as per the given layout? > Generally, such a big CBFS seems odd. I think changes are better made > outside of coreboot, e.g. the payload. What is your exact use case? > > Nico I am using the direct-grub payload (which incorporates cbfs with a limitation of maximum 16MB memory mapped flash space), plus I want to package few other binaries. Thanks, Nitin ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Change Romsize and CBFS size.
Hi,
I am trying to build a Coreboot for a Flash Size as 64 MB, with 32MB reserved
for a BIOS region.
I have modified the descriptor for a bios region:
0200:03ff bios
The fmap used for the given setting is as follows:
FLASH@4227858432 0x400 {
BIOS@33554432 0x200 {
FMAP@0 0x200
RW_MRC_CACHE@65536 0x1
COREBOOT(CBFS)@131072 33423360
}
}
Flash start -> 0xFC00 (with-in 4GB space @4227858432)
Flash Size -> 0x400
BIOS Start offset w.r.t Flash start -> 0x200 (@33554432)
Bios region size -> 0x200
CBFS Size -> 0x1FE
Can any one please let me know what are the other changes required to
incorporate the Coreboot image as per the given layout?
Thanks,
Nitin.
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[coreboot] Re: Regarding Intel CPU frequency (Intel Denverton based)
Hi Paul, As far as cpu init is concerned, I haven't modified the cpu initialization sequence for the given board. The code is located under following sub-folder "src/soc/intel/denverton_ns/cpu.c". The given CPU (CPU C3558) has 4 cores, and I am noticing the following logs while booting up, which I am trying to debug in parallel by inserting some delays. The wakeup fails for cpu (core) 1, but it continues and passes for 2,3,4. So at the end, cores are getting recognized as CPU 0,2,3,4 respectively. There are few records available for the same sort of cases: https://lore.kernel.org/lkml/0bc26e9524533c38fdbdc95eed2b1...@teksavvy.com/T/ " 1.620879] x86: Booting SMP configuration: [1.624592] node #0, CPUs: #1 [ 11.624587] smpboot: do_boot_cpu failed(-1) to wakeup CPU#1 [ 11.632919] #2 #3 #4 [ 11.636707] smp: Brought up 1 node, 4 CPUs [ 11.640585] smpboot: Max logical packages: 2 [ 11.644585] [ 11.644587] | NMI testsuite: [ 11.644588] [ 11.644590] remote IPI: ok | [ 11.644623]local IPI: ok | [ 11.644642] [ 11.644644] Good, all 2 testcases passed! | [ 11.644646] - [ 11.644650] smpboot: Total of 4 processors activated (17600.00 BogoMIPS) " Thanks for you help. Thanks, Nitin. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Regarding Intel CPU frequency.
HI Paul, I have tried different measures to increase the load on CPU, but still the frequency reflects the same value ie. 800Mz. My question is why this behavior is different w.r.t the one when system boots up with BIOS. When I boot with BIOS, I can see that frequency output stays at 2200Mhz. Do I need to enable some settings under the coreboot code related to turbo frequency e.t.c ? Please find the lscpu dump as follows: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian Address sizes:39 bits physical, 48 bits virtual CPU(s): 5 On-line CPU(s) list: 0,2-4 Off-line CPU(s) list: 1 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s):1 Vendor ID:GenuineIntel CPU family: 6 Model:95 Model name: Intel(R) Atom(TM) CPU C3558 @ 2.20GHz Stepping: 1 CPU MHz: 800.000 BogoMIPS: 4400.00 Virtualization: VT-x L1d cache:24K L1i cache:32K L2 cache: 2048K Flags:fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch cpuid_fault cat_l2 ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust smep erms mpx rdt_a rdseed smap clflushopt intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm arat pln pts arch_capabilities Thanks, Nitin. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Regarding Intel CPU frequency.
Hi Mariusz, I tried running the stress test to increase the load average, but still the frequency stays at 800Mhz. Thanks, Nitin. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Regarding Intel CPU frequency.
Hi, I am using coreboot to boot Denverton cpu (CPU C3558) based board. I can see that the cpu frequency is set to the correct value i.e. "2200 Mhz" under the coreboot logs. . " CPU #3 initialized bsp_do_flight_plan done after 146 msecs. cpu: frequency set to 2200 " Later when I check the frequency reading under linux (kernel version 4.19) , It comes out as 800 Mz: model name : Intel(R) Atom(TM) CPU C3558 @ 2.20GHz stepping: 1 microcode : 0x24 cpu MHz : 800.000 When I reprogram the board with BIOS, the cpu frequency gets reflected correctly (i.e. 2200 MHz) with the same kernel image. I have also tried out the different Grub command line options like disabling the pstate, and idle state e.t.c, but the end result remains same. Can anyone please provide me some suggestions. Is there is any cpu specific settings which needs to enabled under coreboot or with Intel-FSP ? Thanks, Nitin. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: REGARDING COREBOOT 4.11 release for "Harcuvar mainboard"
Hi Mariusz, Thanks for your reply. I will try out with the given settings. Is there is a new release happening for (coreboot denverton_soc) ? Regards, Nitin. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] REGARDING COREBOOT 4.11 release for "Harcuvar mainboard"
Hi All, Can anyone help me regarding the instructions to build coreboot 4.11 release for Harcuvar platform. I am not able to see the microcode, FSP_T and other settings in make menuconfig (for the Harcuvar platform). I am already using the settings suggested under the doc "denverton-ns-coreboot-pc-001-release-notes-v1-3 " to build the coreboot version number 4.9. I am facing the given problem when I am trying to migrate to coreboot-4.11 release (while using the same steps). Thanks in advance, Nitin. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
