I can't build serialICE, here's the log :
10:30:14 AM) bianchi: on serialICE Mainboard Intel D946GZIS ...ROM 512K
...make menuconfig
(10:30:35 AM) bianchi: Kconfig:438:warning: defaults for choice values not
supported
(10:30:35 AM) bianchi: #
(10:30:35 AM) bianchi: # configuration written to
It's in SerialICE project, not in coreboot project.
On 2016年10月17日 10:23, Antonius Riko wrote:
I can not see
D946GZIS
on my src/mainboard/intel where is it ?
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I can not see
D946GZIS
on my src/mainboard/intel where is it ?
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coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
I didn't see carefully that coreboot has 946hopefully it will help me a
lot...I need to see it's superio and southbridge then...
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On Sun, Oct 16, 2016 at 5:12 PM, Riko Ho wrote:
> Everyone..
>
> What's the process on diassembling i946GZ ? How can I do that from my
> original motherboard ? so I can see the init process of this northbridge ?
>
> How can I use SerialICE doing it ? I want to know the
Everyone..
What's the process on diassembling i946GZ ? How can I do that from my
original motherboard ? so I can see the init process of this northbridge ?
How can I use SerialICE doing it ? I want to know the process
downloading the code from the original motherboard, and run it on Qemu ?
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