Board: asus/f2a85-m
In AMD Bolton FCH Register Reference Guide (51192), page 2-154, this
register Interrupt Line – RW – 32 bits - [PCI_Reg:3Ch] is 0x12/0x11
while having booted the vendor binary and 0xff/0xff when having booted
coreboot.
Could the erratic value cause SeaBIOS boot issues? See
Subject should read Re: Hudson-D4 (A85X): IRQ routing of XHCI seems
incomplete?
2015-07-08 15:59 GMT+02:00 Idwer Vollering vid...@gmail.com:
Board: asus/f2a85-m
In AMD Bolton FCH Register Reference Guide (51192), page 2-154, this
register Interrupt Line – RW – 32 bits - [PCI_Reg:3Ch] is
Hi
In AMD Bolton FCH Register Reference Guide (51192), page 2-154, this
register Interrupt Line – RW – 32 bits - [PCI_Reg:3Ch] is 0x12/0x11
while having booted the vendor binary and 0xff/0xff when having booted
coreboot.
Well this register is used only by OS when MPTABLE/ACPI PCI routing
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