Hello Nico,
My patch to ./roda/rk9/romstage.c
--- ./rk9_orig/romstage.c 2014-02-14 18:26:39.0 +0400
+++ ./rk9_patch/romstage.c 2014-02-14 18:36:24.859508133 +0400
@@ -47,10 +47,14 @@
/* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT,
WLAN, ~ANTMUX, ~GPIO12,
Hello Nico,My patch to ./roda/rk9/romstage.cThank youBest regards, Dmitry Bagryanskiy
patch
Description: Binary data
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Am 14.02.2014 14:23, schrieb Vladimir 'φ-coder/phcoder' Serbinenko:
> On 14.02.2014 13:38, Dmitry Bagryanskiy wrote:
>> //Enable Com3
>> pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c02e1);
>> //Enable Com4
>> pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x001c03e1);
> GEN*_DEC should not be set
Hello Dmitry,
> I solved the problem with GP1-GP4 registers. It is needen to change
> the mask for decosding the port 0x600 on LPC.
> pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x001f0601);
I'm not sure how changing the mask helps. Please provide a patch, so
I can better understand what you are
On 14.02.2014 13:38, Dmitry Bagryanskiy wrote:
> //Enable Com3
> pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c02e1);
> //Enable Com4
> pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x001c03e1);
GEN*_DEC should not be set to com* ports. Instead there are dedicated
bits for enabling decode of seri
Hello Nico,
Problem solution with registers.
Laptop: Roda RK9 13", 15" and 17"
I solved the problem with GP1-GP4 registers. It is needen to change the mask
for decosding the port 0x600 on LPC.
pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x001f0601);
Also preparation for opening the ports for CO
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