Re: [coreboot] Something wrong in last week's check-in

Am 2014-07-22 00:18, schrieb WANG FEI: I dont notice this issue one week before (I update my coreboot source code one a week), does anyone have the same issue? There weren't any issues in the area I'd suspect would be responsible (src/arch/x86/Makefile.inc). You could try to use git bisect

[coreboot] high-pitched whine on x60/t60

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 So far we have workarounds (idle=halt or processor.max_cstate=2 kernel parameter, or 'powertop --auto-tune'). I am fully aware that these are workarounds, not solutions. A libreboot user also reported that the following programme can be used (in the

Re: [coreboot] high-pitched whine on x60/t60

Hi folks, I haven't followed the previous discussion on this matter, so one question: Is this a coreboot issue? If this noise doesn't occur with the vendor firmware, has anybody checked if coreboot uses the same power management timing settings? (e.g. C4-TIMING_CNT, see [1], there might be more

Re: [coreboot] high-pitched whine on x60/t60

Nico Huber wrote: Is this a coreboot issue? Partially. has anybody checked if coreboot uses the same power management timing settings? No, but I'm quite sure that it does not. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] high-pitched whine on x60/t60

These power supply issues are quite fun, like other things. The mistake would be to say that, because there is noise, coreboot is wrong and vendor firmware is right. It can be far more subtle than that. It could even be the case that coreboot is right, the vendor code is wrong, and the correction

Re: [coreboot] high-pitched whine on x60/t60

ron minnich wrote: wrong right It's way too early for that Ron. At this point nobody even understands wtf is causing the problem. Someone competent needs to research that before a discussion about the solution. //Peter -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] high-pitched whine on x60/t60

On Tue, Jul 22, 2014 at 10:55 AM, Peter Stuge pe...@stuge.se wrote: ron minnich wrote: wrong right It's way too early for that Ron. At this point nobody even understands wtf is causing the problem. Someone competent needs to research that before a discussion about the solution. I'm not

Re: [coreboot] f2a85-m vga binary revision

i'll summarize my off-list discussion with ruik here. i've slightly, or moderately, edited some of my previous answers to ruik. in this email i've updated, corrected and integrated various information i gave. On 07/17/2014 06:04 PM, Rudolf Marek wrote: Hi Andrew, I seen also some freezes and

[coreboot] FYI: latest ACPICA acpidump is broken

Hi, ruiktest ~ # /tmp/acpidump Could not get ACPI tables, AE_BAD_HEADER It seems there is a bug in ACPICA, coreboot is using revision 0 (ACPI 1.0) if there is no XSDT. But ACPICA expect always ACPI 2.0 style which have a len record. This is bit more complicated, coreboot creates a header with

[coreboot] Will an ASUS M5A97 R2.0 work with coreboot?

Hello I own an ASUS M5A97 R2.0 and I would like to know if coreboot is supported. I think the Northbridge is an AMD 970 and the Southbridge is SB950 (I don't know for sure though). My CPU is an FX 6350 (Piledriver). Here's the output of lspci -tvnn: -[:00]-+-00.0 Advanced Micro Devices,