Dear Nitin,
Am 23.04.20 um 14:35 schrieb nitin.ramesh.si...@gmail.com:
I am using coreboot to boot Denverton cpu (CPU C3558) based board.
Nice. Are you going to send it upstream?
I can see that the cpu frequency is set to the correct value i.e. "2200 Mhz"
under the coreboot logs.
.
"
CPU
Hello Matt,
Thank you for your response. I see that SeaBIOS still can’t handle the FMAP
structure.
The pointer depends on the FMAP layout and this is different to chromium
devices.
For the UP squared board I did not find any other solution than to set
CONFIG_CBFS_LOCATION=0xFFFC and
to
HI Paul,
I have tried different measures to increase the load on CPU, but still the
frequency reflects the same value ie. 800Mz.
My question is why this behavior is different w.r.t the one when system boots
up with BIOS.
When I boot with BIOS, I can see that frequency output stays at 2200Mhz.
Hello Nitin,
Since you are running Linux, do you see anything interesting in the output
of dmesg? You could filter for warnings and errors by running "dmesg -l
warn,err", but it might be better to provide the full log.
Recently, I have started experiencing a similar issue with a i7-3720QM and
Dear Nitin,
Am 24.04.20 um 11:53 schrieb nitin.ramesh.si...@gmail.com:
I have tried different measures to increase the load on CPU, but
still the frequency reflects the same value ie. 800Mz.
My question is why this behavior is different w.r.t the one when
system boots up with BIOS.
If you
Hi Paul,
As far as cpu init is concerned, I haven't modified the cpu initialization
sequence for the given board. The code is located under following sub-folder
"src/soc/intel/denverton_ns/cpu.c".
The given CPU (CPU C3558) has 4 cores, and I am noticing the following logs
while booting up,
Nitin,
We have encountered both of these issues and have corrected them in our own
code base for a particular client. We are not in a position to upstream our
changes, but I can tell you the source of each problem.
1. CPU frequency: For Denverton SKUs that do NOT support turbo mode (like
the one
Hi Jay,
Thanks for your suggestion.
I was able to figure out the given problem by inserting few debug prints
under the file "cpu.c" , it seems the stepping mode is not getting set for
given cpu, along with apic id coming out as 4.
The observation matches with your comments as well.
Once
On Fri, Apr 24, 2020 at 4:59 AM Wolfgang Kamp - datakamp
wrote:
> Hello Matt,
>
>
>
> Thank you for your response. I see that SeaBIOS still can’t handle the
> FMAP structure.
>
> The pointer depends on the FMAP layout and this is different to chromium
> devices.
>
> For the UP squared board I
Hi Jonathan,
I'll have a look, but I cannot help on the IIO stuff, as we still don't
have access to Intel's confidential documents.
Kind Regards,
Patrick Rudolph
B.Sc. Electrical Engineering
System Firmware Developer
9elements Agency GmbH, Kortumstraße 19-21, 44787 Bochum, Germany
Email:
Hi,
On Thu, 2020-04-23 at 08:15 +, Wolfgang Kamp - datakamp wrote:
> Am I correct that the problem still exists that SeaBios can’t find
> the CBFS in apl platform?
I used this as workaround:
https://review.coreboot.org/c/coreboot/+/32327
It requires that you put the CBFS at the end of
Hello Wolfgang,
On 21.04.20 16:50, Wolfgang Kamp - datakamp wrote:
> I found out that the panel backlight enable function in libgfxinit for
> Broxton platform (Intel x5-E3940) will not work for me.
> The Backlight Enabling Sequence Description in the Intel document Doc Ref #
> IHD-OS-BXT-Vol
12 matches
Mail list logo
