Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

Addressing over 8G is not supported by the chipset used on nehalem thinkpad laptops (X201) Stupid limitation, but it is not the CPU fault. On Sat, Jan 21, 2017 at 5:55 AM, Stefan Tauner < stefan.tau...@alumni.tuwien.ac.at> wrote: > Hi Vladimir, > > since you have REed the raminit for Nehalem

[coreboot] Weird issue: payloads not showing after seabios

Hello I am sorry if this is a total noob question, but I can't get any other payload to show other that the default seabios payload or memtest86. nvramcui, tint, coreinfo (all automatically added by coreboot as secondary payloads) or grub (added manually with cbfstool) show nothing, or cause a

[coreboot] More details about ram issues

Hello On Tue, Nov 8, 2016 at 11:30 AM, Patrick Rudolph wrote: > Good point, I've should have mentioned that. > Well, I found out by myself the hard way after scratching my head. It is the best way to learn I suppose :-) > At the moment there's no such functionality I'm

[coreboot] Removing Intel ME from the X230 coreboot

Hello Did you release any of your work to remove the ME for a X230? I am interested in attempting that on a W520. On https://www.coreboot.org/pipermail/coreboot/2016-September/082049.html you mention you left ROMP, BUP, KERNEL, POLICY and FTCS. Any update on that? Is it the minimal set?? I

[coreboot] Patch: support for the Lenovo Thinkpad W520

Hello I am new to coreboot. I tried to run coreboot on my Thinkpad W520 to replace my Sandy Bridge CPU by a Ivy Bridge CPU, since several people reported it worked very well. Following their suggestions, I simply tried to flash a T520 image to save time. It didn't work at all. I was very angry I

Re: [coreboot] Patch: support for the Lenovo Thinkpad W520

016 um 09:33 schrieb Charlotte Plusplus: > Please use git ( > https://www.coreboot.org/Development_Guidelines#How_to_contribute ) and > gerrit ( http://review.coreboot.org/#/q/status:open ) to upload your > patch. This allows easy reviewing and commenting, including an automatic > build fo

Re: [coreboot] More details about ram issues

So I did many more tests today (more than 6h, and flashing around 30 times), with SPD settings hardcoded into raminit, and without the mrc cache interfering. TLDR: coreboot tries to increase the frequency without increasing the voltage, and that doesn't work for all memory. Basically, with the

Re: [coreboot] Patch: support for the Lenovo Thinkpad W520

Hello On 11/6/16, Nico Huber wrote: > http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/6-chipset-c200-chipset-datasheet.pdf Thanks a lot for the documentation the detailed the explaination! I will try to fix my devicetree. Now if only I could find

Re: [coreboot] Removing Intel ME from the X230 coreboot

to further trim the intel ME? Thanks Charlotte On 11/6/16, Federico Amedeo Izzo <federico.izz...@gmail.com> wrote: > On 11/06/2016 10:11 AM, Charlotte Plusplus wrote: >> Hello >> >> Did you release any of your work to remove the ME for a X230? >> >> I am

[coreboot] Why is subsystemid required to find a uPD7020200

Hello The USB3 on a W520 is provided by a uPD7020200 on PCIe port 7, so I just had in my device tree: device pci 1c.6 on end Yet in the boot I was getting: PCI: Static device PCI: 00:1c.6 not found, disabling it. After googlging about this, I found the x230 uses subsystemid device

Re: [coreboot] Nehalem not booting with two ram sticks

Hello On Tue, Nov 22, 2016 at 2:50 PM, Kyösti Mälkki wrote: > >> I tried using the MRC blob to compare the timings, but I must have done >> something wrong in my code as it didn't work at all >> > > See following commits: > 5c10abe nb/intel/sandybridge: increase

Re: [coreboot] Nehalem not booting with two ram sticks

Hello On Tue, Nov 22, 2016 at 4:28 PM, Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > If MCU is later, could you, please, explain how you did this in IVB > Coreboot code (since this might be beneficial to Federico's attempts)? > Edit devicetree.cb and set: register

Re: [coreboot] Nehalem not booting with two ram sticks

I have had similar issues with Corsair ram on the W520 recently: sometimes not booting at all, sometimes being unstable (in memest) after a succesfull raminit. The only way I could get the 4 dimms to work was to hardcode some SPDs, or set the MCU to a much slower speed. Like you, I found

Re: [coreboot] Rettungsboot

the shared kernel Charlotte On Sun, Nov 27, 2016 at 7:26 PM, ron minnich <rminn...@gmail.com> wrote: > > > On Sun, Nov 27, 2016 at 4:22 PM Charlotte Plusplus < > pluspluscharlo...@gmail.com> wrote: > >> >> >> In my ideal scenario, coreboot would have the

[coreboot] How to access temperature sensors on 'modern' thinkpads?

Hello I am still interested in lowering the power consumption. To try to find the culprit, I am thinking about monitoring temperature sensors. On the W520 specs, I see on p 70 ("Thermal sensor"): S0: PCH/BASE COVER S1: NVIDIA S2: GBE S3: WWAN S4: DIMM(TOP) S5: DIMM(BOTTOM) S6: WLAN S7: EXPRESS

Re: [coreboot] Rettungsboot

Hudson <hud...@trmm.net> wrote: > On Sun, Nov 27, 2016 at 07:30:07PM -0500, Charlotte Plusplus wrote: > > [...] > > With the amount of flash we have, sharing the kernel and initrd doesn't > > seem like a bad idea. > > The problem is if a bad kernel or initrd is flashed

Re: [coreboot] Rettungsboot

Hello On Sat, Nov 26, 2016 at 6:19 PM, Trammell Hudson wrote: > The 4MB flash in the older thinkpads is a little tight, but still > sufficient for a text-based modern Linux kernel -- the biggest issue is > the cryptsetup tool brings in quite a few dependencies right now, >

Re: [coreboot] native video init question

in the payloads, if it cause security issues, I guess I can do without it. Charlotte On Wed, Nov 16, 2016 at 7:32 AM, Nico Huber <nico.hu...@secunet.com> wrote: > On 16.11.2016 06:08, Charlotte Plusplus wrote: > > Hello > > > > On Tue, Nov 15, 2016 at 6:46 PM, Nico

Re: [coreboot] Powersavings: 8W of difference between bios and coreboot

Hello Super interesting, I didn't know all that! Currently, I have only set in devicetree: device pci 00.0 on end # host bridge device pci 01.0 off end # NVidia device pci 02.0 on end # Intel and in my nvram options I have: hybrid_graphics_mode = Integrated Only I assumed that would be

Re: [coreboot] Powersavings: 8W of difference between bios and coreboot

0 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Charlotte On Fri, Nov 18, 2016 at 4:04 PM, Charlotte Plusplus < pluspluscharlo...@gmail.com> wrote: > Hello > > Su

[coreboot] Powersavings: 8W of difference between bios and coreboot

Hello Since I started using coreboot, I have noticed my battery doesn't seem to last as long. I have a very simple linux install on a separate partition that I use to compare power consumption, so I decided to verify if my perception was true. After some quick tests, I noticed the power profile

Re: [coreboot] native video init question

the documentation of the registers to use this information to get native video init working. Is there anything else I should run before I have to give it back?? Charlotte On Wed, Nov 16, 2016 at 10:06 PM, Charlotte Plusplus < pluspluscharlo...@gmail.com> wrote: > Hello > > Yes I have included t

Re: [coreboot] More details about ram issues

Hello On Fri, Nov 11, 2016 at 7:53 AM, Nico Huber wrote: > > After reading more about XMP and SPD, it is my understanding that : > > - JEDEC specs stop at 1600, and after that XMP is required > > - even before 1600, XMP also offers profiles, and they are not optional: > > some

Re: [coreboot] More details about ram issues

Hello On Sat, Nov 12, 2016 at 7:28 PM, Nico Huber wrote: > Looks like it's booting the fallback path, maybe because something went > wrong on the normal path? I haven't got USB debug working with the MRC > blob reliably for over a year now, btw. But you should definitely see >

[coreboot] using overlayfs to have several coreboot dev envs

Hello With the cross compiling tool chain, coreboot takes 1G. If you are a bit short on space, or if you want to save writes to your SSD, instead of having multiple copies of the coreboot source folder, I have found out overlayfs is very practical. If you have done git clone in

Re: [coreboot] More details about ram issues

Hello On Fri, Nov 11, 2016 at 5:32 PM, Nico Huber wrote: > The XMP implementation just needs to be completed to also do > the voltage > part. > > Which either does not work if the board is not designed for it or would > include hardware modifications. > No it doesn't. The

Re: [coreboot] More details about ram issues

Hello On Fri, Nov 11, 2016 at 5:37 PM, Nico Huber wrote: > > The W520 does only have 1.5V DDR voltage. If it's stable with vendor > > bios, it's not a DDR voltage problem at all. > Based on my reading of the block diagram and crossing that with a cpu pinout and the cpu specs, I

Re: [coreboot] Powersavings: 8W of difference between bios and coreboot

(Local0, Arg0) } } Else { NoOp } } } On Sat, Nov 19, 2016 at 1:57 AM, Charlotte Plusplus < pluspluscharlo...@gmail.com> wrote: >

Re: [coreboot] native video init question

nc 48 x 10 Front porch 60 x 10 Spread spectrum clock Dual channel Polarities 1, 1 Data M1=10108272, N1=8388608 Link frequency 27 kHz Link M1=280785, N1=524288 Pixel N=7, M1=22, M2=8, P1=2 Pixel clock 144489 kHz waiting for panel powerup panel powered up On Thu, Nov 17, 2016 at 11:54 PM, Charlo

Re: [coreboot] More details about ram issues

Huber <nic...@gmx.de> wrote: > On 12.11.2016 05:00, Charlotte Plusplus wrote: > > Hello > > > > On Fri, Nov 11, 2016 at 5:37 PM, Nico Huber <nic...@gmx.de> wrote: > > > >>> The W520 does only have 1.5V DDR voltage. If it's stable with vendo

Re: [coreboot] Why is subsystemid required to find a uPD7020200

Huber <nico.hu...@secunet.com> wrote: > On 15.11.2016 03:03, Charlotte Plusplus wrote: > > Hello > > > > The USB3 on a W520 is provided by a uPD7020200 on PCIe port 7, so I just > > had in my device tree: > > device pci 1c.6 on end > > > >

Re: [coreboot] native video init question

Hello The correct timings are detected by X (cf below), so I checked the existing gma_ivybridge init and I thought it may calculate clocks wrong. Then I found about https://review.coreboot.org/#/c/16504/ addressing just this, so I tried to port it to gma_ivybridge Unfortunately I must I have

Re: [coreboot] using overlayfs to have several coreboot dev envs

If you refactor that code, could you make it easier to add the fallback? One of the main reason I use overlayfs is to keep a separate fallback Overlayfs may remain a good option when working on separate source trees, but when the differences are just in the .config. it would be nice to specify

[coreboot] native video init question

Hello Here is the current status of my W520: - native video init gives a garbled image (picture available upon request lol). it may be due to the resolution of the screen being hardcoded somewhere, or more likely me using the wrong information since the W520 uses 1980x1080 - non native video

Re: [coreboot] latest greatest thinkpad with coreboot

I see recommendations for a X230, but I disagree. If you really want the best, it's a W520 or a W530. In either, you can have 32G of Ram, and you can replace the default CPU with a Intel i7 3940XM cpu. But only on the W520 you will have a full size display port and (more important) an eSATAp

Re: [coreboot] Wiki page for Lenovo Thinkpad W520

Hello I would be very happy to help with pictures, source, binaries, info etc. But since Denver, I have been just a bit behind. Too many side projects :-) Anyway, I will get back in touch soon. If you use my previously released binary, you should be fine. The port to the current coreboot I did

Re: [coreboot] Cherry Trail Support

It is this the small cool machine I bought with me in Denver and showed around. Cherry trail seems to have made its way to a lot of cheap laptop and tablets too (BestBuy Insignia 11' tablet) On Sun, Jul 16, 2017 at 5:48 AM, Arne Zachlod wrote: > Hi all, > > I got a GPD

Re: [coreboot] Wiki page for Lenovo Thinkpad W520

as show on a memtest Charlotte On Tue, Jul 18, 2017 at 2:55 AM, Iru Cai <mytbk920...@gmail.com> wrote: > Hi Charlotte, > > On Tue, Jul 18, 2017 at 1:37 PM, Charlotte Plusplus < > pluspluscharlo...@gmail.com> wrote: > >> Hello >> >> I would be very happy