subject:"\[coreboot\] southbridge\/intel\/i82801gx\/i82801gx.h"

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-17 Thread Riko Ho

continuing the chat,
for displaying "Hello world" on serial

#define CLKIN_DEV PNP_DEV(0x2e, IT8718F_GPIO)

void mainboard_romstage_entry(unsigned long bist)
{
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);

ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);


How can I write "Hello world !" ? and where ?

Could it be :

ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);

ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

printk(" HELLO WORLD ! FROM COREBOOT...");
..
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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-16 Thread Riko Ho


Will coreboot run on basic mode without "microcode" ?
I've read about it :
http://inertiawar.com/microcode/

On 16/10/2016 1:10 PM, Antonius Riko wrote:

Is that the one ?
-rw-rw-r--   1 bianchi bianchi 524288 Oct 16 13:04 coreboot.rom

can it be uploaded as *.hex or *.bin to my flash ? my flash is W39V040FB

inside /coreboot/build/




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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Antonius Riko

Is that the one ?
-rw-rw-r--   1 bianchi bianchi 524288 Oct 16 13:04 coreboot.rom

can it be uploaded as *.hex or *.bin to my flash ? my flash is W39V040FB

inside /coreboot/build/
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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Antonius Riko

I retry it without "microcode." it can compile completely, but where
can I find coreboot.rom to be burn to flash chip ,

Debug result :
bianchi@ubuntu:~/coreboot$ make menuconfig
configuration written to /home/bianchi/coreboot/.config

*** End of the configuration.
*** Execute 'make' to start the build or try 'make help'.

bianchi@ubuntu:~/coreboot$ make
#
# configuration written to /home/bianchi/coreboot/.config
#
build/auto.conf:1974:warning: override: reassigning to symbol
CONSOLE_SERIAL_TEGRA210_UART_CHOICES
CC bootblock/mainboard/intel/i946gz/static.o
CC bootblock/arch/x86/boot.o
GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
ROMCC  generated/bootblock.inc
CC bootblock/arch/x86/bootblock_romcc.o
CC bootblock/arch/x86/cpu_common.o
CC bootblock/arch/x86/id.o
CC bootblock/arch/x86/memcpy.o
CC bootblock/arch/x86/memset.o
CC bootblock/arch/x86/mmap_boot.o
CC bootblock/arch/x86/walkcbfs.o
CC bootblock/commonlib/cbfs.o
CC bootblock/commonlib/lz4_wrapper.o
CC bootblock/commonlib/mem_pool.o
CC bootblock/commonlib/region.o
CC bootblock/console/die.o
CC bootblock/console/post.o
CC bootblock/cpu/x86/lapic/boot_cpu.o
CC bootblock/cpu/x86/mtrr/earlymtrr.o
CC bootblock/device/device_simple.o
CC bootblock/device/i2c.o
CC bootblock/drivers/uart/uart8250io.o
CC bootblock/drivers/uart/util.o
CC bootblock/lib/boot_device.o
CC bootblock/lib/bootmode.o
FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
CC bootblock/lib/cbfs.o
CC bootblock/lib/cbmem_console.o
CC bootblock/lib/delay.o
CC bootblock/lib/fmap.o
CC bootblock/lib/gcc.o
CC bootblock/lib/halt.o
CC bootblock/lib/hexdump.o
CC bootblock/lib/libgcc.o
CC bootblock/lib/memchr.o
CC bootblock/lib/memcmp.o
CC bootblock/lib/prog_loaders.o
CC bootblock/lib/prog_ops.o
CC bootblock/lib/version.o
CC bootblock/vboot/bootmode.o
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/static.o
CC romstage/arch/x86/acpi_s3.o
CC romstage/arch/x86/assembly_entry.o
CC romstage/arch/x86/boot.o
CC romstage/arch/x86/cbfs_and_run.o
CC romstage/arch/x86/cbmem.o
CC romstage/arch/x86/cpu_common.o
CC romstage/arch/x86/memcpy.o
CP romstage/arch/x86/memlayout.ld
CC romstage/arch/x86/memmove.o
CC romstage/arch/x86/memset.o
CC romstage/arch/x86/mmap_boot.o
CC romstage/arch/x86/postcar_loader.o
CC romstage/commonlib/cbfs.o
CC romstage/commonlib/lz4_wrapper.o
CC romstage/commonlib/mem_pool.o
CC romstage/commonlib/region.o
CC romstage/console/console.o
CC romstage/console/die.o
CC romstage/console/init.o
CC romstage/console/post.o
CC romstage/console/printk.o
CC romstage/console/vtxprintf.o
CC romstage/cpu/intel/car/romstage.o
CC romstage/cpu/intel/microcode/microcode.o
CC romstage/cpu/x86/car.o
CC romstage/cpu/x86/lapic/apic_timer.o
CC romstage/cpu/x86/lapic/boot_cpu.o
CC romstage/cpu/x86/mtrr/earlymtrr.o
CC romstage/device/device_simple.o
CC romstage/device/i2c.o
CC romstage/device/pci_early.o
CC romstage/drivers/pc80/rtc/mc146818rtc.o
CC romstage/drivers/pc80/rtc/mc146818rtc_early.o
CC romstage/drivers/uart/uart8250io.o
CC romstage/drivers/uart/util.o
CC romstage/lib/boot_device.o
CC romstage/lib/bootmode.o
CC romstage/lib/cbfs.o
CC romstage/lib/cbmem_common.o
CC romstage/lib/cbmem_console.o
CC romstage/lib/compute_ip_checksum.o
CC romstage/lib/delay.o
CC romstage/lib/fmap.o
CC romstage/lib/gcc.o
CC romstage/lib/halt.o
CC romstage/lib/hexdump.o
CC romstage/lib/imd.o
CC romstage/lib/imd_cbmem.o
CC romstage/lib/libgcc.o
CC romstage/lib/memchr.o
CC romstage/lib/memcmp.o
CC romstage/lib/memrange.o
CC romstage/lib/prog_loaders.o
CC romstage/lib/prog_ops.o
CP romstage/lib/program.ld
CC ro

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Antonius Riko

Why did it stop ?
Any clues ?

bianchi@ubuntu:~/coreboot$ make
#
# configuration written to /home/bianchi/coreboot/.config
#
CC bootblock/mainboard/intel/i946gz/static.o
CC bootblock/arch/x86/boot.o
GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
ROMCC  generated/bootblock.inc
CC bootblock/arch/x86/bootblock_romcc.o
CC bootblock/arch/x86/cpu_common.o
CC bootblock/arch/x86/id.o
CC bootblock/arch/x86/memcpy.o
CC bootblock/arch/x86/memset.o
CC bootblock/arch/x86/mmap_boot.o
CC bootblock/arch/x86/walkcbfs.o
CC bootblock/commonlib/cbfs.o
CC bootblock/commonlib/lz4_wrapper.o
CC bootblock/commonlib/mem_pool.o
CC bootblock/commonlib/region.o
CC bootblock/console/die.o
CC bootblock/console/post.o
CC bootblock/cpu/x86/lapic/boot_cpu.o
CC bootblock/cpu/x86/mtrr/earlymtrr.o
CC bootblock/device/device_simple.o
CC bootblock/device/i2c.o
CC bootblock/drivers/uart/uart8250io.o
CC bootblock/drivers/uart/util.o
CC bootblock/lib/boot_device.o
CC bootblock/lib/bootmode.o
FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
CC bootblock/lib/cbfs.o
CC bootblock/lib/cbmem_console.o
CC bootblock/lib/delay.o
CC bootblock/lib/fmap.o
CC bootblock/lib/gcc.o
CC bootblock/lib/halt.o
CC bootblock/lib/hexdump.o
CC bootblock/lib/libgcc.o
CC bootblock/lib/memchr.o
CC bootblock/lib/memcmp.o
CC bootblock/lib/prog_loaders.o
CC bootblock/lib/prog_ops.o
CC bootblock/lib/version.o
CC bootblock/vboot/bootmode.o
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/static.o
CC romstage/arch/x86/acpi_s3.o
CC romstage/arch/x86/assembly_entry.o
CC romstage/arch/x86/boot.o
CC romstage/arch/x86/cbfs_and_run.o
CC romstage/arch/x86/cbmem.o
CC romstage/arch/x86/cpu_common.o
CC romstage/arch/x86/memcpy.o
CP romstage/arch/x86/memlayout.ld
CC romstage/arch/x86/memmove.o
CC romstage/arch/x86/memset.o
CC romstage/arch/x86/mmap_boot.o
CC romstage/arch/x86/postcar_loader.o
CC romstage/commonlib/cbfs.o
CC romstage/commonlib/lz4_wrapper.o
CC romstage/commonlib/mem_pool.o
CC romstage/commonlib/region.o
CC romstage/console/console.o
CC romstage/console/die.o
CC romstage/console/init.o
CC romstage/console/post.o
CC romstage/console/printk.o
CC romstage/console/vtxprintf.o
CC romstage/cpu/intel/car/romstage.o
CC romstage/cpu/intel/microcode/microcode.o
CC romstage/cpu/x86/car.o
CC romstage/cpu/x86/lapic/apic_timer.o
CC romstage/cpu/x86/lapic/boot_cpu.o
CC romstage/cpu/x86/mtrr/earlymtrr.o
CC romstage/device/device_simple.o
CC romstage/device/i2c.o
CC romstage/device/pci_early.o
CC romstage/drivers/pc80/rtc/mc146818rtc.o
CC romstage/drivers/pc80/rtc/mc146818rtc_early.o
CC romstage/drivers/uart/uart8250io.o
CC romstage/drivers/uart/util.o
CC romstage/lib/boot_device.o
CC romstage/lib/bootmode.o
CC romstage/lib/cbfs.o
CC romstage/lib/cbmem_common.o
CC romstage/lib/cbmem_console.o
CC romstage/lib/compute_ip_checksum.o
CC romstage/lib/delay.o
CC romstage/lib/fmap.o
CC romstage/lib/gcc.o
CC romstage/lib/halt.o
CC romstage/lib/hexdump.o
CC romstage/lib/imd.o
CC romstage/lib/imd_cbmem.o
CC romstage/lib/libgcc.o
CC romstage/lib/memchr.o
CC romstage/lib/memcmp.o
CC romstage/lib/memrange.o
CC romstage/lib/prog_loaders.o
CC romstage/lib/prog_ops.o
CP romstage/lib/program.ld
CC romstage/lib/ramtest.o
CC romstage/lib/romstage_stack.o
CC romstage/lib/stack.o
CC romstage/lib/version.o
CC romstage/mainboard/intel/i946gz/romstage.o
CC romstage/northbridge/intel/i945/debug.o
CC romstage/northbridge/intel/i945/early_init.o
CC romstage/northbridge/intel/i945/errata.o
CC romstage/nort

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Nico Huber

On 15.10.2016 15:44, Riko Ho wrote:
> So I must do rm .config and make menu config then don't select :
> 
>  CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I
> did, I forget already...
> Can you read it from .config ?
Yes, it would have shown up as a line that says
CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y

> 
> Anyway, what's the safe mode / default for make menuconfig ? What's the
> payload option should I make ?
I usually head straight to the mainboard selection, keeping everything
else as is. The payload doesn't matter, as long as coreboot doesn't boot
through. You can just leave it at the default "SeaBIOS", or change it
to "None" until you have a working coreboot.

Nico

> 
> 
> On 15/10/2016 9:12 PM, Nico Huber wrote
> 
>> On 15.10.2016 14:57, Antonius Riko wrote:
>>> I did rm .config and did make again :
>>>
>>> bianchi@ubuntu:~/coreboot$ make clean
>>> bianchi@ubuntu:~/coreboot$ make
>>> #
>>> # configuration written to /home/bianchi/coreboot/.config
>>> #
>>>  HOSTCC util/sconfig/lex.yy.o
>>>  HOSTCC util/sconfig/sconfig.tab.o
>>>  HOSTCC util/sconfig/main.o
>>>  HOSTCC util/sconfig/sconfig (link)
>>>  SCONFIGmainboard/intel/i946gz/devicetree.cb
>>>  HOSTCC nvramtool/cli/nvramtool.o
>>>  HOSTCC nvramtool/cli/opts.o
>>>  HOSTCC nvramtool/cmos_lowlevel.o
>>>  HOSTCC nvramtool/cmos_ops.o
>>>  HOSTCC nvramtool/common.o
>>>  HOSTCC nvramtool/compute_ip_checksum.o
>>>  HOSTCC nvramtool/hexdump.o
>>>  HOSTCC nvramtool/input_file.o
>>>  HOSTCC nvramtool/layout.o
>>>  HOSTCC nvramtool/accessors/layout-common.o
>>>  HOSTCC nvramtool/accessors/layout-text.o
>>>  HOSTCC nvramtool/accessors/layout-bin.o
>>>  HOSTCC nvramtool/lbtable.o
>>>  HOSTCC nvramtool/reg_expr.o
>>>  HOSTCC nvramtool/cbfs.o
>>>  HOSTCC nvramtool/accessors/cmos-mem.o
>>>  HOSTCC nvramtool/nvramtool (link)
>>>  OPTION option_table.h
>>>  CC bootblock/mainboard/intel/i946gz/static.o
>>>  CC bootblock/arch/x86/boot.o
>>>  GENgenerated/bootblock.ld
>>>  CP bootblock/arch/x86/bootblock.ld
>>>  HOSTCC util/romcc/romcc (this may take a while)
>>>  ROMCC  generated/bootblock.inc
>>>  CC bootblock/arch/x86/bootblock_romcc.o
>>>  CC bootblock/arch/x86/cpu_common.o
>>>  GENbuild.h
>>>  CC bootblock/arch/x86/id.o
>>>  CC bootblock/arch/x86/memcpy.o
>>>  CC bootblock/arch/x86/memset.o
>>>  CC bootblock/arch/x86/mmap_boot.o
>>>  CC bootblock/arch/x86/timestamp.o
>>>  CC bootblock/arch/x86/walkcbfs.o
>>>  CC bootblock/commonlib/cbfs.o
>>>  CC bootblock/commonlib/lz4_wrapper.o
>>>  CC bootblock/commonlib/mem_pool.o
>>>  CC bootblock/commonlib/region.o
>>>  CC bootblock/console/die.o
>>>  CC bootblock/console/post.o
>>>  CC bootblock/cpu/x86/lapic/boot_cpu.o
>>>  CC bootblock/cpu/x86/mtrr/earlymtrr.o
>>>  CC bootblock/device/device_simple.o
>>>  CC bootblock/device/i2c.o
>>>  CC bootblock/drivers/uart/uart8250io.o
>>>  CC bootblock/drivers/uart/util.o
>>>  CC bootblock/lib/boot_device.o
>>>  CC bootblock/lib/bootmode.o
>>>  HOSTCC cbfstool/fmaptool.o
>>>  HOSTCC cbfstool/cbfs_sections.o
>>>  HOSTCC cbfstool/fmap_from_fmd.o
>>>  HOSTCC cbfstool/fmd.o
>>>  HOSTCC cbfstool/fmd_parser.o
>>>  HOSTCC cbfstool/fmd_scanner.o
>>>  HOSTCC cbfstool/fmap.o
>>>  HOSTCC cbfstool/kv_pair.o
>>>  HOSTCC cbfstool/valstr.o
>>>  HOSTCC cbfstool/fmaptool (link)
>>>  FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
>>> build/fmap.fmd build/fmap.fmap
>>> SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated
>>> header)
>>> The sections containing CBFSes are: COREBOOT
>>>  CC bootblock/lib/cbfs.o
>>>  CC bootblock/lib/cbmem_console.o
>>>  CC bootblock/lib/delay.o
>>>  CC bootblock/lib/fmap.o
>>>  CC bootblock/lib/gcc.o
>>>  CC bootblock/lib/halt.o
>>>  CC bootblock/lib/hexdump.o
>>>  CC bootblock/lib/libgcc.o
>>>  CC bootblock/lib/memchr.o
>>>  CC bootblock/lib/memcmp.o
>>>  CC bootblock/lib/prog_loaders.o
>>>  CC bootblock/lib/prog_ops.o
>>>  CC bootblock/lib/timestamp.o
>>>  CC bootblock/lib/version.o
>>>  CC bootblock/vboot/bootmode.o
>>>  LINK   cbfs/fallback/bootblock.debug
>>>  OBJCOPYcbfs/fallback/bootblock.elf
>>>  OBJCOPYbootblock.raw.bin
>>>  CC romstage/mainboard/intel/i946gz/static.o
>>>  CC ro

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Riko Ho


So I must do rm .config and make menu config then don't select :

 CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I did, I 
forget already...
Can you read it from .config ?

Anyway, what's the safe mode / default for make menuconfig ? What's the payload 
option should I make ?


On 15/10/2016 9:12 PM, Nico Huber wrote


On 15.10.2016 14:57, Antonius Riko wrote:

I did rm .config and did make again :

bianchi@ubuntu:~/coreboot$ make clean
bianchi@ubuntu:~/coreboot$ make
#
# configuration written to /home/bianchi/coreboot/.config
#
 HOSTCC util/sconfig/lex.yy.o
 HOSTCC util/sconfig/sconfig.tab.o
 HOSTCC util/sconfig/main.o
 HOSTCC util/sconfig/sconfig (link)
 SCONFIGmainboard/intel/i946gz/devicetree.cb
 HOSTCC nvramtool/cli/nvramtool.o
 HOSTCC nvramtool/cli/opts.o
 HOSTCC nvramtool/cmos_lowlevel.o
 HOSTCC nvramtool/cmos_ops.o
 HOSTCC nvramtool/common.o
 HOSTCC nvramtool/compute_ip_checksum.o
 HOSTCC nvramtool/hexdump.o
 HOSTCC nvramtool/input_file.o
 HOSTCC nvramtool/layout.o
 HOSTCC nvramtool/accessors/layout-common.o
 HOSTCC nvramtool/accessors/layout-text.o
 HOSTCC nvramtool/accessors/layout-bin.o
 HOSTCC nvramtool/lbtable.o
 HOSTCC nvramtool/reg_expr.o
 HOSTCC nvramtool/cbfs.o
 HOSTCC nvramtool/accessors/cmos-mem.o
 HOSTCC nvramtool/nvramtool (link)
 OPTION option_table.h
 CC bootblock/mainboard/intel/i946gz/static.o
 CC bootblock/arch/x86/boot.o
 GENgenerated/bootblock.ld
 CP bootblock/arch/x86/bootblock.ld
 HOSTCC util/romcc/romcc (this may take a while)
 ROMCC  generated/bootblock.inc
 CC bootblock/arch/x86/bootblock_romcc.o
 CC bootblock/arch/x86/cpu_common.o
 GENbuild.h
 CC bootblock/arch/x86/id.o
 CC bootblock/arch/x86/memcpy.o
 CC bootblock/arch/x86/memset.o
 CC bootblock/arch/x86/mmap_boot.o
 CC bootblock/arch/x86/timestamp.o
 CC bootblock/arch/x86/walkcbfs.o
 CC bootblock/commonlib/cbfs.o
 CC bootblock/commonlib/lz4_wrapper.o
 CC bootblock/commonlib/mem_pool.o
 CC bootblock/commonlib/region.o
 CC bootblock/console/die.o
 CC bootblock/console/post.o
 CC bootblock/cpu/x86/lapic/boot_cpu.o
 CC bootblock/cpu/x86/mtrr/earlymtrr.o
 CC bootblock/device/device_simple.o
 CC bootblock/device/i2c.o
 CC bootblock/drivers/uart/uart8250io.o
 CC bootblock/drivers/uart/util.o
 CC bootblock/lib/boot_device.o
 CC bootblock/lib/bootmode.o
 HOSTCC cbfstool/fmaptool.o
 HOSTCC cbfstool/cbfs_sections.o
 HOSTCC cbfstool/fmap_from_fmd.o
 HOSTCC cbfstool/fmd.o
 HOSTCC cbfstool/fmd_parser.o
 HOSTCC cbfstool/fmd_scanner.o
 HOSTCC cbfstool/fmap.o
 HOSTCC cbfstool/kv_pair.o
 HOSTCC cbfstool/valstr.o
 HOSTCC cbfstool/fmaptool (link)
 FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
 CC bootblock/lib/cbfs.o
 CC bootblock/lib/cbmem_console.o
 CC bootblock/lib/delay.o
 CC bootblock/lib/fmap.o
 CC bootblock/lib/gcc.o
 CC bootblock/lib/halt.o
 CC bootblock/lib/hexdump.o
 CC bootblock/lib/libgcc.o
 CC bootblock/lib/memchr.o
 CC bootblock/lib/memcmp.o
 CC bootblock/lib/prog_loaders.o
 CC bootblock/lib/prog_ops.o
 CC bootblock/lib/timestamp.o
 CC bootblock/lib/version.o
 CC bootblock/vboot/bootmode.o
 LINK   cbfs/fallback/bootblock.debug
 OBJCOPYcbfs/fallback/bootblock.elf
 OBJCOPYbootblock.raw.bin
 CC romstage/mainboard/intel/i946gz/static.o
 CC romstage/arch/x86/acpi_s3.o
 GENgenerated/assembly.inc
 CC romstage/arch/x86/assembly_entry.o
 CC romstage/arch/x86/boot.o
 CC romstage/arch/x86/cbfs_and_run.o
 CC romstage/arch/x86/cbmem.o
 CC romstage/arch/x86/cpu_common.o
 CC romstage/arch/x86/memcpy.o
 CP romstage/arch/x86/memlayout.ld
 CC romstage/arch/x86/memmove.o
 CC romstage/arch/x86/memset.o
 CC romstage/arch/x86/mmap_boot.o
 CC romstage/arch/x86/postcar_loader.o
 CC romstage/arch/x86/timestamp.o
 CC romstage/commonlib/cbfs.o
 CC romstage/commonlib/lz4_wrapper.o
 CC romstage/commonlib/mem_pool.o
 CC romstage/commonlib/region.o

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Nico Huber

On 15.10.2016 14:57, Antonius Riko wrote:
> I did rm .config and did make again :
> 
> bianchi@ubuntu:~/coreboot$ make clean
> bianchi@ubuntu:~/coreboot$ make
> #
> # configuration written to /home/bianchi/coreboot/.config
> #
> HOSTCC util/sconfig/lex.yy.o
> HOSTCC util/sconfig/sconfig.tab.o
> HOSTCC util/sconfig/main.o
> HOSTCC util/sconfig/sconfig (link)
> SCONFIGmainboard/intel/i946gz/devicetree.cb
> HOSTCC nvramtool/cli/nvramtool.o
> HOSTCC nvramtool/cli/opts.o
> HOSTCC nvramtool/cmos_lowlevel.o
> HOSTCC nvramtool/cmos_ops.o
> HOSTCC nvramtool/common.o
> HOSTCC nvramtool/compute_ip_checksum.o
> HOSTCC nvramtool/hexdump.o
> HOSTCC nvramtool/input_file.o
> HOSTCC nvramtool/layout.o
> HOSTCC nvramtool/accessors/layout-common.o
> HOSTCC nvramtool/accessors/layout-text.o
> HOSTCC nvramtool/accessors/layout-bin.o
> HOSTCC nvramtool/lbtable.o
> HOSTCC nvramtool/reg_expr.o
> HOSTCC nvramtool/cbfs.o
> HOSTCC nvramtool/accessors/cmos-mem.o
> HOSTCC nvramtool/nvramtool (link)
> OPTION option_table.h
> CC bootblock/mainboard/intel/i946gz/static.o
> CC bootblock/arch/x86/boot.o
> GENgenerated/bootblock.ld
> CP bootblock/arch/x86/bootblock.ld
> HOSTCC util/romcc/romcc (this may take a while)
> ROMCC  generated/bootblock.inc
> CC bootblock/arch/x86/bootblock_romcc.o
> CC bootblock/arch/x86/cpu_common.o
> GENbuild.h
> CC bootblock/arch/x86/id.o
> CC bootblock/arch/x86/memcpy.o
> CC bootblock/arch/x86/memset.o
> CC bootblock/arch/x86/mmap_boot.o
> CC bootblock/arch/x86/timestamp.o
> CC bootblock/arch/x86/walkcbfs.o
> CC bootblock/commonlib/cbfs.o
> CC bootblock/commonlib/lz4_wrapper.o
> CC bootblock/commonlib/mem_pool.o
> CC bootblock/commonlib/region.o
> CC bootblock/console/die.o
> CC bootblock/console/post.o
> CC bootblock/cpu/x86/lapic/boot_cpu.o
> CC bootblock/cpu/x86/mtrr/earlymtrr.o
> CC bootblock/device/device_simple.o
> CC bootblock/device/i2c.o
> CC bootblock/drivers/uart/uart8250io.o
> CC bootblock/drivers/uart/util.o
> CC bootblock/lib/boot_device.o
> CC bootblock/lib/bootmode.o
> HOSTCC cbfstool/fmaptool.o
> HOSTCC cbfstool/cbfs_sections.o
> HOSTCC cbfstool/fmap_from_fmd.o
> HOSTCC cbfstool/fmd.o
> HOSTCC cbfstool/fmd_parser.o
> HOSTCC cbfstool/fmd_scanner.o
> HOSTCC cbfstool/fmap.o
> HOSTCC cbfstool/kv_pair.o
> HOSTCC cbfstool/valstr.o
> HOSTCC cbfstool/fmaptool (link)
> FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
> build/fmap.fmd build/fmap.fmap
> SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
> The sections containing CBFSes are: COREBOOT
> CC bootblock/lib/cbfs.o
> CC bootblock/lib/cbmem_console.o
> CC bootblock/lib/delay.o
> CC bootblock/lib/fmap.o
> CC bootblock/lib/gcc.o
> CC bootblock/lib/halt.o
> CC bootblock/lib/hexdump.o
> CC bootblock/lib/libgcc.o
> CC bootblock/lib/memchr.o
> CC bootblock/lib/memcmp.o
> CC bootblock/lib/prog_loaders.o
> CC bootblock/lib/prog_ops.o
> CC bootblock/lib/timestamp.o
> CC bootblock/lib/version.o
> CC bootblock/vboot/bootmode.o
> LINK   cbfs/fallback/bootblock.debug
> OBJCOPYcbfs/fallback/bootblock.elf
> OBJCOPYbootblock.raw.bin
> CC romstage/mainboard/intel/i946gz/static.o
> CC romstage/arch/x86/acpi_s3.o
> GENgenerated/assembly.inc
> CC romstage/arch/x86/assembly_entry.o
> CC romstage/arch/x86/boot.o
> CC romstage/arch/x86/cbfs_and_run.o
> CC romstage/arch/x86/cbmem.o
> CC romstage/arch/x86/cpu_common.o
> CC romstage/arch/x86/memcpy.o
> CP romstage/arch/x86/memlayout.ld
> CC romstage/arch/x86/memmove.o
> CC romstage/arch/x86/memset.o
> CC romstage/arch/x86/mmap_boot.o
> CC romstage/arch/x86/postcar_loader.o
> CC romstage/arch/x86/timestamp.o
> CC romstage/commonlib/cbfs.o
> CC romstage/commonlib/lz4_wrapper.o
> CC romstage/commonlib/mem_pool.o
> CC romstage/commonlib/region.o
> CC romstage/console/console.o
> CC romstage/console/die.o
> CC romstage/console/init.o
> CC romstage/console/post.o
> CC romstage/console/printk.o
> CC r

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Antonius Riko

I did rm .config and did make again :

bianchi@ubuntu:~/coreboot$ make clean
bianchi@ubuntu:~/coreboot$ make
#
# configuration written to /home/bianchi/coreboot/.config
#
HOSTCC util/sconfig/lex.yy.o
HOSTCC util/sconfig/sconfig.tab.o
HOSTCC util/sconfig/main.o
HOSTCC util/sconfig/sconfig (link)
SCONFIGmainboard/intel/i946gz/devicetree.cb
HOSTCC nvramtool/cli/nvramtool.o
HOSTCC nvramtool/cli/opts.o
HOSTCC nvramtool/cmos_lowlevel.o
HOSTCC nvramtool/cmos_ops.o
HOSTCC nvramtool/common.o
HOSTCC nvramtool/compute_ip_checksum.o
HOSTCC nvramtool/hexdump.o
HOSTCC nvramtool/input_file.o
HOSTCC nvramtool/layout.o
HOSTCC nvramtool/accessors/layout-common.o
HOSTCC nvramtool/accessors/layout-text.o
HOSTCC nvramtool/accessors/layout-bin.o
HOSTCC nvramtool/lbtable.o
HOSTCC nvramtool/reg_expr.o
HOSTCC nvramtool/cbfs.o
HOSTCC nvramtool/accessors/cmos-mem.o
HOSTCC nvramtool/nvramtool (link)
OPTION option_table.h
CC bootblock/mainboard/intel/i946gz/static.o
CC bootblock/arch/x86/boot.o
GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
HOSTCC util/romcc/romcc (this may take a while)
ROMCC  generated/bootblock.inc
CC bootblock/arch/x86/bootblock_romcc.o
CC bootblock/arch/x86/cpu_common.o
GENbuild.h
CC bootblock/arch/x86/id.o
CC bootblock/arch/x86/memcpy.o
CC bootblock/arch/x86/memset.o
CC bootblock/arch/x86/mmap_boot.o
CC bootblock/arch/x86/timestamp.o
CC bootblock/arch/x86/walkcbfs.o
CC bootblock/commonlib/cbfs.o
CC bootblock/commonlib/lz4_wrapper.o
CC bootblock/commonlib/mem_pool.o
CC bootblock/commonlib/region.o
CC bootblock/console/die.o
CC bootblock/console/post.o
CC bootblock/cpu/x86/lapic/boot_cpu.o
CC bootblock/cpu/x86/mtrr/earlymtrr.o
CC bootblock/device/device_simple.o
CC bootblock/device/i2c.o
CC bootblock/drivers/uart/uart8250io.o
CC bootblock/drivers/uart/util.o
CC bootblock/lib/boot_device.o
CC bootblock/lib/bootmode.o
HOSTCC cbfstool/fmaptool.o
HOSTCC cbfstool/cbfs_sections.o
HOSTCC cbfstool/fmap_from_fmd.o
HOSTCC cbfstool/fmd.o
HOSTCC cbfstool/fmd_parser.o
HOSTCC cbfstool/fmd_scanner.o
HOSTCC cbfstool/fmap.o
HOSTCC cbfstool/kv_pair.o
HOSTCC cbfstool/valstr.o
HOSTCC cbfstool/fmaptool (link)
FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
CC bootblock/lib/cbfs.o
CC bootblock/lib/cbmem_console.o
CC bootblock/lib/delay.o
CC bootblock/lib/fmap.o
CC bootblock/lib/gcc.o
CC bootblock/lib/halt.o
CC bootblock/lib/hexdump.o
CC bootblock/lib/libgcc.o
CC bootblock/lib/memchr.o
CC bootblock/lib/memcmp.o
CC bootblock/lib/prog_loaders.o
CC bootblock/lib/prog_ops.o
CC bootblock/lib/timestamp.o
CC bootblock/lib/version.o
CC bootblock/vboot/bootmode.o
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/static.o
CC romstage/arch/x86/acpi_s3.o
GENgenerated/assembly.inc
CC romstage/arch/x86/assembly_entry.o
CC romstage/arch/x86/boot.o
CC romstage/arch/x86/cbfs_and_run.o
CC romstage/arch/x86/cbmem.o
CC romstage/arch/x86/cpu_common.o
CC romstage/arch/x86/memcpy.o
CP romstage/arch/x86/memlayout.ld
CC romstage/arch/x86/memmove.o
CC romstage/arch/x86/memset.o
CC romstage/arch/x86/mmap_boot.o
CC romstage/arch/x86/postcar_loader.o
CC romstage/arch/x86/timestamp.o
CC romstage/commonlib/cbfs.o
CC romstage/commonlib/lz4_wrapper.o
CC romstage/commonlib/mem_pool.o
CC romstage/commonlib/region.o
CC romstage/console/console.o
CC romstage/console/die.o
CC romstage/console/init.o
CC romstage/console/post.o
CC romstage/console/printk.o
CC romstage/console/vtxprintf.o
CC romstage/cpu/intel/car/romstage.o
CC romstage/cpu/intel/microcode/microcode.o
CC romstage/cpu/x86/car.o
CC romstage/cpu/x86/lapic/apic_timer.o
CC romstage/cpu/x86/lapic/boot_cpu.o

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Antonius Riko

Hi,

make clean, did helpthanks

now in the next stage, I got this error :
Include CPU microcode in CBFS
> 1. Generate from tree (CPU_MICROCODE_CBFS_GENERATE)
  2. Include external microcode header files
(CPU_MICROCODE_CBFS_EXTERNAL_HEADER)
  3. Do not include microcode updates (CPU_MICROCODE_CBFS_NONE)
choice[1-3]: 1
Microcode binary path and filename (CPU_UCODE_BINARIES) []
*
* Northbridge
*
*
* Southbridge
*
*
* Super I/O
*
*
* Embedded Controllers
*
Vboot non-volatile storage in CMOS. (VBOOT_VBNV_CMOS) [N/y/?] n
Vboot non-volatile storage in EC. (VBOOT_VBNV_EC) [N/y/?] n
Verify firmware with vboot. (VBOOT) [N/y/?] (NEW) y
*
* Generic Drivers
*
AS3722 RTC support (DRIVERS_AS3722_RTC) [N/y] n
Realtek 8168 reset (REALTEK_8168_RESET) [N/y/?] n
Serial port on SuperIO (DRIVERS_UART_8250IO) [Y/n] y
Oxford OXPCIe952 (DRIVERS_UART_OXPCIE) [N/y/?] n
UART's PCI bus, device, function address (UART_PCI_ADDR) [0x0] 0x0
USB 2.0 EHCI debug dongle support (USBDEBUG) [N/y/?] (NEW) y
  Enable early (pre-RAM) usbdebug (USBDEBUG_IN_ROMSTAGE) [Y/n/?] (NEW) y
  Type of dongle
  > 1. Net20DC or compatible (USBDEBUG_DONGLE_STD) (NEW)
2. BeagleBone (USBDEBUG_DONGLE_BEAGLEBONE) (NEW)
3. BeagleBone Black (USBDEBUG_DONGLE_BEAGLEBONE_BLACK) (NEW)
4. FTDI FT232H UART (USBDEBUG_DONGLE_FTDI_FT232H) (NEW)
  choice[1-4]: 1
I2C TPM (I2C_TPM) [Y] (NEW) y
I2C TPM Driver
> 1. Generic I2C TPM Driver (I2C_TPM_GENERIC) (NEW)
  2. CR50 I2C TPM Driver (I2C_TPM_CR50) (NEW)
choice[1-2]: 1
I2C TPM chip bus (DRIVER_TPM_I2C_BUS) [0x9] (NEW) 1
I2C TPM chip address (DRIVER_TPM_I2C_ADDR) [0x2] (NEW) 0x2
IRQ or GPE to use for TPM interrupt (DRIVER_TPM_I2C_IRQ) [-1] (NEW) 18
Generate I2C TPM ACPI device (DRIVER_I2C_TPM_ACPI) [N/y] n
Support Intel PCI-e WiFi adapters (DRIVERS_INTEL_WIFI) [Y/n/?] y
PS/2 keyboard init (DRIVERS_PS2_KEYBOARD) [N/y/?] n
Silicon Image SIL3114 (DRIVERS_SIL_3114) [N/y/?] n
TI TPS65913 support (DRIVERS_TI_TPS65913) [N/y] n
TI TPS65913 RTC support (DRIVERS_TI_TPS65913_RTC) [N/y] n
*
* Console
*
Squelch AP CPUs from early console. (SQUELCH_EARLY_SMP) [Y/n/?] y
Serial port console output (CONSOLE_SERIAL) [Y/n/?] y
  *
  * I/O mapped, 8250-compatible
  *
  Index for UART port to use for console (UART_FOR_CONSOLE) [0] 0
  *
  * Serial port base address = 0x3f8
  *
  Baud rate
1. 921600 (CONSOLE_SERIAL_921600)
2. 460800 (CONSOLE_SERIAL_460800)
3. 230400 (CONSOLE_SERIAL_230400)
  > 4. 115200 (CONSOLE_SERIAL_115200)
5. 57600 (CONSOLE_SERIAL_57600)
6. 38400 (CONSOLE_SERIAL_38400)
7. 19200 (CONSOLE_SERIAL_19200)
8. 9600 (CONSOLE_SERIAL_9600)
  choice[1-8]: 4
spkmodem (console on speaker) console output (SPKMODEM) [N/y/?] n
USB dongle console output (CONSOLE_USB) [N/y/?] (NEW) y
Use onboard VGA as primary video device (ONBOARD_VGA_IS_PRIMARY) [N/y/?] n
Network console over NE2000 compatible Ethernet adapter (CONSOLE_NE2K)
[N/y/?] n
Send console output to a CBMEM buffer (CONSOLE_CBMEM) [Y/n/?] y
  Room allocated for console output in CBMEM (CONSOLE_CBMEM_BUFFER_SIZE)
[0x2] 0x2
Default console log level
> 1. 8: SPEW (DEFAULT_CONSOLE_LOGLEVEL_8)
  2. 7: DEBUG (DEFAULT_CONSOLE_LOGLEVEL_7)
  3. 6: INFO (DEFAULT_CONSOLE_LOGLEVEL_6)
  4. 5: NOTICE (DEFAULT_CONSOLE_LOGLEVEL_5)
  5. 4: WARNING (DEFAULT_CONSOLE_LOGLEVEL_4)
  6. 3: ERR (DEFAULT_CONSOLE_LOGLEVEL_3)
  7. 2: CRIT (DEFAULT_CONSOLE_LOGLEVEL_2)
  8. 1: ALERT (DEFAULT_CONSOLE_LOGLEVEL_1)
  9. 0: EMERG (DEFAULT_CONSOLE_LOGLEVEL_0)
choice[1-9]: 1
Don't show any POST codes (NO_POST) [N/y] n
  Store post codes in CMOS for debugging (CMOS_POST) [N/y/?] n
  Show POST codes on the debug console (CONSOLE_POST) [N/y/?] n
  Send POST codes to an external device (POST_DEVICE) [Y/n] y
Device to send POST codes to
> 1. None (POST_DEVICE_NONE)
  2. LPC (POST_DEVICE_LPC)
  3. PCI/PCIe (POST_DEVICE_PCI_PCIE)
choice[1-3]: 1
  Send POST codes to an IO port (POST_IO) [Y/n/?] y
IO port for POST codes (POST_IO_PORT) [0x80] 0x80
*
* Debugging
*
GDB debugging support (GDB_STUB) [Y/n/?] y
  Wait for a GDB connection (GDB_WAIT) [N/y/?] n
Halt when hitting a BUG() or assertion error (FATAL_ASSERTS) [N/y/?] n
Output verbose CBFS debug messages (DEBUG_CBFS) [Y/n/?] y
Output verbose RAM init debug messages (DEBUG_RAM_SETUP) [N/y/?] n
Check PIRQ table consistency (DEBUG_PIRQ) [Y/n/?] y
Output verbose SMI debug messages (DEBUG_SMI) [N/y/?] (NEW) y
Debug SMM relocation code (DEBUG_SMM_RELOCATION) [N/y/?] (NEW) y
Output verbose malloc debug messages (DEBUG_MALLOC) [Y/n/?] y
Output verbose ACPI debug messages (DEBUG_ACPI) [Y/n/?] y
Output verbose TPM debug messages (DEBUG_TPM) [N/y/?] (NEW) y
Output verbose USB 2.0 EHCI debug dongle messages (DEBUG_USBDEBUG) [N/y/?]
(NEW) y
Trace function calls (TRACE) [Y/n/?] y
Debug boot state machine (DEBUG_BOOT_STATE) [Y/n/?] y
*
* Restart config...
*
*
* Chipset
*
*
* SoC
*
*
* CPU
*
Include CPU microcode in CBFS
> 1. Generate from tree (CPU_MICROCODE_CBFS_GENERATE)
  2. Include external microcode header files
(CP

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Nico Huber

Hi,

On 15.10.2016 13:26, Antonius Riko wrote:
> I closed the patch
> 
> //#include 
> //#include 
> //#include 
> 
> and I got error :
> 
> bianchi@ubuntu:~/coreboot$ make
> GENgenerated/bootblock.ld
> CP bootblock/arch/x86/bootblock.ld
> LINK   cbfs/fallback/bootblock.debug
> OBJCOPYcbfs/fallback/bootblock.elf
> OBJCOPYbootblock.raw.bin
> CC romstage/mainboard/intel/i946gz/romstage.o
> LINK   cbfs/fallback/romstage.debug
> build/romstage/mainboard/intel/i946gz/romstage.o: In function
> `mainboard_romstage_entry':
> /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214:
> undefined reference to `southbridge_detect_s3_resume'
> /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217:
> undefined reference to `enable_smbus'
> build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte':
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> more undefined references to `smbus_read_byte' follow
> src/arch/x86/Makefile.inc:264: recipe for target
> 'build/cbfs/fallback/romstage.debug' failed
> make: *** [build/cbfs/fallback/romstage.debug] Error 1

it's hard to reproduce with only the Kconfig snippet. Here's what I've
tried: copied src/mainboard/intel/d945gclf to i946gz, used your Kconfig
below and the following Kconfig.name:

config BOARD_INTEL_I946GZ
bool "I946GZ"

Then I got:
build/romstage/mainboard/intel/i946gz/romstage.o: In function
`mainboard_romstage_entry':
/home/icon/coreboot/src/mainboard/intel/i946gz/romstage.c:162: undefined
reference to `lpc47m15x_enable_serial'
/home/icon/coreboot/src/mainboard/intel/i946gz/romstage.c:163: undefined
reference to `lpc47m15x_enable_serial'

which is ok, given that I mixed the d945gclf/romstage.c with your
Kconfig.

Maybe it's just a leftover from your previous try; did you do a `make
clean`? If that doesn't help, maybe your .config is just messed up
because of the Kconfig changes. You should try with a fresh .config
(i.e. `rm .config` then `make menuconfig` again and select intel/i945gz).

Nico

PS. Please use the "reply" function of your mail client, if it has any.
That way mails can be sorted in one thread correctly which makes
the mailing list life a lot easier.

> 
> my Kconfig at /src/mainboard/intel/i946gz :
> 
> ##
> ## This file is part of the coreboot project.
> ##
> ## Copyright (C) 2009 coresystems GmbH
> ##
> ## This program is free software; you can redistribute it and/or modify
> ## it under the terms of the GNU General Public License as published by
> ## the Free Software Foundation; version 2 of the License.
> ##
> ## This program is distributed in the hope that it will be useful,
> ## but WITHOUT ANY WARRANTY; without even the implied warranty of
> ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> ## GNU General Public License for more details.
> ##
> if BOARD_INTEL_I946GZ
> 
> config BOARD_SPECIFIC_OPTIONS # dummy
>   def_bool y
>   select CPU_INTEL_SOCKET_LGA775
> select NORTHBRIDGE_INTEL_I945
>   select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
>   ##select NORTHBRIDGE_INTEL_I946GZ
>   ##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ
>   select CHECK_SLFRCS_ON_RESUME
>   select SOUTHBRIDGE_INTEL_I82801GX
>   select SUPERIO_ITE_IT8718F
>   select HAVE_OPTION_TABLE
>   select HAVE_PIRQ_TABLE
>   select HAVE_MP_TABLE
>   select HAVE_ACPI_TABLES
>   select HAVE_ACPI_RESUME
>   select BOARD_ROMSIZE_KB_512
>   select CHANNEL_XOR_RANDOMIZATION
>   select MAINBOARD_HAS_NATIVE_VGA_INIT
>   select INTEL_EDID
> 
> config MAINBOARD_DIR
>   string
>   default intel/i946gz
> 
> config MAINBOARD_PART_NUMBER
>   string
>   default "I946GZ"
> 
> config MMCONF_BASE_ADDRESS
>   hex
>   default 0xf000
> 
> config IRQ_SLOT_COUNT
>   int
>   default 18
> 
> config MAX_CPUS
>   int
>   default 1
> 
> endif # BOARD_INTEL_I946GZ
> 
> 
> 
> Including .c files is a bad idea. We did that before and still do in
> some places, but will get rid of it in the future hopefully. Also you
> are mixing romstage (early_*.c) and ramstage (lpc.c) code here.
> 
> I guess the remaining errors are caused by the mixing.
> 
> Hope that helps,
> Nico
> 
> ==
> 
> 
> 


-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Antonius Riko

Thanks, for the response
Here's what I've got, what else do I miss here ?

I closed the patch

//#include 
//#include 
//#include 

and I got error :
bianchi at ubuntu
:~/coreboot$ make
GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/romstage.o
LINK   cbfs/fallback/romstage.debug
build/romstage/mainboard/intel/i946gz/romstage.o: In function
`mainboard_romstage_entry':
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214:
undefined reference to `southbridge_detect_s3_resume'
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217:
undefined reference to `enable_smbus'
build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte':
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
more undefined references to `smbus_read_byte' follow
src/arch/x86/Makefile.inc:264: recipe for target
'build/cbfs/fallback/romstage.debug' failed
make: *** [build/cbfs/fallback/romstage.debug] Error 1

my Kconfig at /src/mainboard/intel/i946gz :

##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
if BOARD_INTEL_I946GZ

config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_LGA775
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
##select NORTHBRIDGE_INTEL_I946GZ
##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_ITE_IT8718F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_EDID

config MAINBOARD_DIR
string
default intel/i946gz

config MAINBOARD_PART_NUMBER
string
default "I946GZ"

config MMCONF_BASE_ADDRESS
hex
default 0xf000

config IRQ_SLOT_COUNT
int
default 18

config MAX_CPUS
int
default 1

endif # BOARD_INTEL_I946GZ



Including .c files is a bad idea. We did that before and still do in
some places, but will get rid of it in the future hopefully. Also you
are mixing romstage (early_*.c) and ramstage (lpc.c) code here.

I guess the remaining errors are caused by the mixing.

Hope that helps,
Nico
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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Antonius Riko

I closed the patch

//#include 
//#include 
//#include 

and I got error :

bianchi@ubuntu:~/coreboot$ make
GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/romstage.o
LINK   cbfs/fallback/romstage.debug
build/romstage/mainboard/intel/i946gz/romstage.o: In function
`mainboard_romstage_entry':
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214:
undefined reference to `southbridge_detect_s3_resume'
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217:
undefined reference to `enable_smbus'
build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte':
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
more undefined references to `smbus_read_byte' follow
src/arch/x86/Makefile.inc:264: recipe for target
'build/cbfs/fallback/romstage.debug' failed
make: *** [build/cbfs/fallback/romstage.debug] Error 1

my Kconfig at /src/mainboard/intel/i946gz :

##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
if BOARD_INTEL_I946GZ

config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_LGA775
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
##select NORTHBRIDGE_INTEL_I946GZ
##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_ITE_IT8718F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_EDID

config MAINBOARD_DIR
string
default intel/i946gz

config MAINBOARD_PART_NUMBER
string
default "I946GZ"

config MMCONF_BASE_ADDRESS
hex
default 0xf000

config IRQ_SLOT_COUNT
int
default 18

config MAX_CPUS
int
default 1

endif # BOARD_INTEL_I946GZ



Including .c files is a bad idea. We did that before and still do in
some places, but will get rid of it in the future hopefully. Also you
are mixing romstage (early_*.c) and ramstage (lpc.c) code here.

I guess the remaining errors are caused by the mixing.

Hope that helps,
Nico

==
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Nico Huber

Hi Rick,

from your messages on IRC, I guess you almost got it. You have to select
SOUTHBRIDGE_INTEL_I82801GX in your mainboard's Kconfig. Just do a `git
grep select\ SOUTHBRIDGE_INTEL_I82801GX` and you'll find where it's set
for other boards. The correct files should then be added by Makefiles.

More answers inline below...

On 15.10.2016 10:24, Antonius Riko wrote:
> Everyone,
> 
> I tried to port I946GZ and following from 945 example on intel mainboard,
> 
> and I got error when compiling :
> 
> build/romstage/mainboard/intel/i946gz/romstage.o: In function
> `mainboard_romstage_entry':
> /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined
> reference to `southbridge_detect_s3_resume'
> /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217: undefined
> reference to `enable_smbus'
> build/romstage/northbridge/intel/i945/raminit.o: In function
> `spd_read_byte':
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> more undefined references to `smbus_read_byte' follow
> src/arch/x86/Makefile.inc:264: recipe for target
> 'build/cbfs/fallback/romstage.debug' failed
> make: *** [build/cbfs/fallback/romstage.debug] Error 1
> 
> When I patch it with :
> 
> #include 
> #include 
> #include 

Including .c files is a bad idea. We did that before and still do in
some places, but will get rid of it in the future hopefully. Also you
are mixing romstage (early_*.c) and ramstage (lpc.c) code here.

I guess the remaining errors are caused by the mixing.

Hope that helps,
Nico

> 
> the errors are gone but I got :
>GENgenerated/bootblock.ld
> CP bootblock/arch/x86/bootblock.ld
> LINK   cbfs/fallback/bootblock.debug
> OBJCOPYcbfs/fallback/bootblock.elf
> OBJCOPYbootblock.raw.bin
> CC romstage/mainboard/intel/i946gz/romstage.o
> In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
> src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_enable_ioapic':
> src/southbridge/intel/i82801gx/lpc.c:52:20: error: passing argument 1 of
> 'pcie_write_config8' makes integer from pointer without a cast
> [-Werror=int-conversion]
>   pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
> ^
> In file included from src/arch/x86/include/arch/io.h:247:0,
>  from src/mainboard/intel/i946gz/romstage.c:20:
> src/arch/x86/include/arch/pci_mmio_cfg.h:49:6: note: expected 'pci_devfn_t
> {aka unsigned int}' but argument is of type 'struct device *'
>  void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
>   ^
> In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
> src/southbridge/intel/i82801gx/lpc.c: In function
> 'i82801gx_enable_serial_irqs':
> src/southbridge/intel/i82801gx/lpc.c:66:20: error: passing argument 1 of
> 'pcie_write_config8' makes integer from pointer without a cast
> [-Werror=int-conversion]
>   pci_write_config8(dev, SERIRQ_CNTL,
> ^
> In file included from src/arch/x86/include/arch/io.h:247:0,
>  from src/mainboard/intel/i946gz/romstage.c:20:
> src/arch/x86/include/arch/pci_mmio_cfg.h:49:6: note: expected 'pci_devfn_t
> {aka unsigned int}' but argument is of type 'struct device *'
>  void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
>   ^
> In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
> src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_pirq_init':
> src/southbridge/intel/i82801gx/lpc.c:95:24: error: invalid type argument of
> '->' (have 'device_t {aka unsigned int}')
>   config_t *config = dev->chip_info;
> ^
> src/southbridge/intel/i82801gx/lpc.c:97:43: error: dereferencing pointer to
> incomplete type 'config_t {aka struct southbridge_intel_i82801gx_config}'
>   pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
>^
> src/southbridge/intel/i82801gx/lpc.c:111:17: error: 'all_devices'
> undeclared (first use in this function)
>   for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
>  ^
> src/southbridge/intel/i82801gx/lpc.c:111:17: note: each undeclared
> identifier is reported only once for each function it appears in
> src/southbridge/intel/i82801gx/lpc.c:111:56: error: invalid type argument
> of '->' (have 'device_t {aka unsigned int}')
>   for (irq_dev = all_device

[coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Antonius Riko

Everyone,

I tried to port I946GZ and following from 945 example on intel mainboard,

and I got error when compiling :

build/romstage/mainboard/intel/i946gz/romstage.o: In function
`mainboard_romstage_entry':
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined
reference to `southbridge_detect_s3_resume'
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217: undefined
reference to `enable_smbus'
build/romstage/northbridge/intel/i945/raminit.o: In function
`spd_read_byte':
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
more undefined references to `smbus_read_byte' follow
src/arch/x86/Makefile.inc:264: recipe for target
'build/cbfs/fallback/romstage.debug' failed
make: *** [build/cbfs/fallback/romstage.debug] Error 1

When I patch it with :

#include 
#include 
#include 

the errors are gone but I got :
   GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/romstage.o
In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_enable_ioapic':
src/southbridge/intel/i82801gx/lpc.c:52:20: error: passing argument 1 of
'pcie_write_config8' makes integer from pointer without a cast
[-Werror=int-conversion]
  pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
^
In file included from src/arch/x86/include/arch/io.h:247:0,
 from src/mainboard/intel/i946gz/romstage.c:20:
src/arch/x86/include/arch/pci_mmio_cfg.h:49:6: note: expected 'pci_devfn_t
{aka unsigned int}' but argument is of type 'struct device *'
 void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
  ^
In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
src/southbridge/intel/i82801gx/lpc.c: In function
'i82801gx_enable_serial_irqs':
src/southbridge/intel/i82801gx/lpc.c:66:20: error: passing argument 1 of
'pcie_write_config8' makes integer from pointer without a cast
[-Werror=int-conversion]
  pci_write_config8(dev, SERIRQ_CNTL,
^
In file included from src/arch/x86/include/arch/io.h:247:0,
 from src/mainboard/intel/i946gz/romstage.c:20:
src/arch/x86/include/arch/pci_mmio_cfg.h:49:6: note: expected 'pci_devfn_t
{aka unsigned int}' but argument is of type 'struct device *'
 void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
  ^
In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_pirq_init':
src/southbridge/intel/i82801gx/lpc.c:95:24: error: invalid type argument of
'->' (have 'device_t {aka unsigned int}')
  config_t *config = dev->chip_info;
^
src/southbridge/intel/i82801gx/lpc.c:97:43: error: dereferencing pointer to
incomplete type 'config_t {aka struct southbridge_intel_i82801gx_config}'
  pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
   ^
src/southbridge/intel/i82801gx/lpc.c:111:17: error: 'all_devices'
undeclared (first use in this function)
  for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 ^
src/southbridge/intel/i82801gx/lpc.c:111:17: note: each undeclared
identifier is reported only once for each function it appears in
src/southbridge/intel/i82801gx/lpc.c:111:56: error: invalid type argument
of '->' (have 'device_t {aka unsigned int}')
  for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
^
src/southbridge/intel/i82801gx/lpc.c:114:15: error: invalid type argument
of '->' (have 'device_t {aka unsigned int}')
   if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
   ^
src/southbridge/intel/i82801gx/lpc.c:114:35: error: invalid type argument
of '->' (have 'device_t {aka unsigned int}')
   if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
   ^
src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_gpi_routing':
src/southbridge/intel/i82801gx/lpc.c:136:24: error: invalid type argument
of '->' (have 'device_t {aka unsigned int}')
  config_t *config = dev->chip_info;
^
src/southbridge/intel/i82801gx/lpc.c: In function 'i8

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[coreboot] southbridge/intel/i82801gx/i82801gx.h

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