Re: [coreboot] Skylake ME power down mitigation timer
On Wed, Oct 12, 2016 at 1:48 PM, Trammell Hudson wrote: > On Wed, Oct 12, 2016 at 10:08:38AM -0700, Duncan Laurie wrote: > > I wouldn't read too much into the data in there, it turns out the ME > > release that added this output detail (which we shipped in this device) > > also got it wrong so the data is not reliable. > > Interesting. Do you mean the ME firmware release that was installed > in the boot ROM? Has Intel shipped an updated firmware file for the > platform? > > The power down mitigation thing you see is related to an errata and not part of the usual watchdog timers. I turn off the AMT watchdog timer in our images so hopefully you will not see a problem there. Intel makes new ME releases for all current and legacy platforms on a pretty regular basis, but we don't update unless there is a good reason. > > > The only drawback so far is that FSP takes quite a bit longer > > > to complete. > > I should say "FSPMemoryInit" takes longer; "FSPTempRamInit" is still > as fast as before. > > I've removed all of the code from the ME firmware image, except the rbe, > kernel, syslib and bup files. I've also resized the ME region from > 0x1000-0x1F to 0x1000-0xF. This potentially makes another 1 MB > available to the coreboot payload. > > I suspect the longer time spent in FspMemoryInit is due to FSP attempting to send HECI messages to the ME and timing out. It looks like Kabylake FSP 2.0 exposes an option for HeciTimeouts which could be set to 0 to disable the timeouts. But that is not part of the Skylake FSP 1.1, so you won't be able to take advantage of it quite yet. Once we're done with Kabylake integration and the Kabylake FSP 2.0 is released that may be an option. > > > It's been up for almost two hours without shutting down. > > The system has been functional most of the day, so the 30 minute > timer does not seem to be active on this platform. Everything seems > to work fine: S3 suspend/resume is slow, but does the right thing now, > and powertop says the system is around 5W idle (Qubes with a 4.4 kernel, > mjg59 mentioned that kernel can't take advantage of low power states). > > Ya without ME firmware you're not going to get very low idle numbers since it is involved in a lot of power management and clock gating. But the fact that it works at all is progress... -duncan -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Skylake ME power down mitigation timer
On Wed, Oct 12, 2016 at 10:08:38AM -0700, Duncan Laurie wrote: > I wouldn't read too much into the data in there, it turns out the ME > release that added this output detail (which we shipped in this device) > also got it wrong so the data is not reliable. Interesting. Do you mean the ME firmware release that was installed in the boot ROM? Has Intel shipped an updated firmware file for the platform? > > The only drawback so far is that FSP takes quite a bit longer > > to complete. I should say "FSPMemoryInit" takes longer; "FSPTempRamInit" is still as fast as before. I've removed all of the code from the ME firmware image, except the rbe, kernel, syslib and bup files. I've also resized the ME region from 0x1000-0x1F to 0x1000-0xF. This potentially makes another 1 MB available to the coreboot payload. > > It's been up for almost two hours without shutting down. The system has been functional most of the day, so the 30 minute timer does not seem to be active on this platform. Everything seems to work fine: S3 suspend/resume is slow, but does the right thing now, and powertop says the system is around 5W idle (Qubes with a 4.4 kernel, mjg59 mentioned that kernel can't take advantage of low power states). -- Trammell -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Skylake ME power down mitigation timer
I wouldn't read too much into the data in there, it turns out the ME release that added this output detail (which we shipped in this device) also got it wrong so the data is not reliable. -duncan On Wed, Oct 12, 2016 at 10:03 AM, Trammell Hudson wrote: > Does anyone have experience with how long the Management Engine's > "Power Down Mitigation" timer is on Skylake? My Chell Chromebook > with modified ME firmware reports this on bootup / S3 resume: > > ME: FW Partition Table : BAD > ME: Bringup Loader Failure : YES > ME: Firmware Init Complete : YES > ME: Manufacturing Mode : YES > ME: Boot Options Present: YES > ME: Update In Progress : YES > ME: D3 Support : YES > ME: D0i3 Support: YES > ME: Low Power State Enabled : YES > ME: Power Gated : YES > ME: CPU Replaced: YES > ME: CPU Replacement Valid : YES > ME: Current Working State : Unknown (15) > ME: Current Operation State : M0 without UMA but with error > ME: Current Operation Mode : M0 without UMA > ME: Error Code : Preboot > ME: Progress Phase : > ME: Power Management Event : CM0PG->CM0 > ME: Progress Phase State: Unknown phase: 0x0f state: 0xff > ME: Power Down Mitigation : YES > ME: PD Mitigation State : Issue Detected but not Recovered > ME: Encryption Key Override : Workaround Applied > ME: Encryption Key Check: FAIL > ME: PCH Configuration Info : Changed > ME: Firmware SKU: Unknown (0x7) > > It's been up for almost two hours without shutting down. > The only drawback so far is that FSP takes quite a bit longer > to complete. > > > -- > Trammell > > -- > coreboot mailing list: coreboot@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
