Re: [cryptography] 5x speedup for AES using SSE5?

2008-08-24 Thread Eric Young
Paul Crowley wrote: http://www.ddj.com/hpc-high-performance-computing/201803067 In the above Dr Dobb's article from a little over a year ago, AMD Senior Fellow Leendert vanDoorn states the Advanced Encryption Standard (AES) algorithm gets a factor of 5 performance improvement by using the

Re: [cryptography] 5x speedup for AES using SSE5?

2008-08-24 Thread Peter Gutmann
Speaking of CPU-specific optimisations, I've seen a few algorithm proposals from the last few years that assume that an algorithm can be scaled linearly in the number of CPU cores, treating a multicore CPU as some kind of SIMD engine with all cores operating in lock-step, or at least engaging in

Period for public comments on XTS (as standardized by IEEE std 1619-2007) ends Sept 3, 2008

2008-08-24 Thread Matt Ball
Hi Folks, Please remember that the 90-day public comment period for XTS ends Sept 3, which is coming up very quickly. If you have any comments you would like to submit to NIST concerning XTS-AES (as specified in IEEE Std 1619-2007), please send an e-mail to [EMAIL PROTECTED] The excerpt of IEEE

Re:5x speedup for AES using SSE5?

2008-08-24 Thread Eric Young
Eric Young wrote: I've not looked at it enough yet, but currently I'm doing an AES round in about 140 cycles a block (call it 13 per round plus overhead) on a AMD64, (220e6 bytes/sec on a 2ghz cpu) using normal instructions. Urk, correction, I forgot I've recently upgraded from a 2ghz machine