Reviewed-by: Ray Ni
> -Original Message-
> From: Liu, Zhiguang
> Sent: Tuesday, May 11, 2021 10:32 AM
> To: devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A ;
> Gao, Zhichao ; Ni, Ray
> Subject: [Patch V3] MdeModulePkg: Retrive boot manager menu from any fv
>
> REF:
5-level paging can be enabled on CPU which supports up to 52 physical
address size. But when the feature was enabled, the 48 address size
limit was not removed and the 5-level paging testing didn't access
address >= 2^48. So the issue wasn't detected until recently an
address >= 2^48 is accessed.
Reviewed-by: Sai Chaganty
-Original Message-
From: Chuang, SofiaX
Sent: Monday, May 10, 2021 12:54 PM
To: devel@edk2.groups.io
Cc: Chuang, SofiaX ; Ni, Ray ;
Chaganty, Rangasai V
Subject: [edk2-devel][PATCH v5 1/7] IntelSiliconPkg/ReportCpuHobLib: Add
ReportCpuHobLib
From: SofiaX
Reviewed-by: Ray Ni
> -Original Message-
> From: Chuang, SofiaX
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Ni, Ray ;
> Chaganty, Rangasai V
>
> Subject: [edk2-devel][PATCH v5 1/7] IntelSiliconPkg/ReportCpuHobLib: Add
> ReportCpuHobLib
>
>
*Reminder:* TianoCore Bug Triage - APAC / NAMO
*When:* Tuesday, 11 May 2021, 6:30pm to 7:30pm, (GMT-07:00) America/Los Angeles
*Where:*
Reviewed-by: Sai Chaganty
-Original Message-
From: Chuang, SofiaX
Sent: Monday, May 10, 2021 12:55 PM
To: devel@edk2.groups.io
Cc: Chuang, SofiaX ; Chiu, Chasel
; Desimone, Nathaniel L
; Chaganty, Rangasai V
; Kethi Reddy, Deepika
; Esakkithevar, Kathappan
Subject:
Reviewed-by: Sai Chaganty
-Original Message-
From: Chuang, SofiaX
Sent: Monday, May 10, 2021 12:54 PM
To: devel@edk2.groups.io
Cc: Chuang, SofiaX ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Luo, Heng
Subject: [edk2-devel][PATCH v5 2/7] TigerlakeOpenBoard: Move ReportCpuHob
I created the PR https://github.com/tianocore/edk2/pull/1637 for merge.
Thanks,
Bob
From: Kinney, Michael D
Sent: Tuesday, May 11, 2021 11:09 PM
To: Sughosh Ganu ; Feng, Bob C ;
Liming Gao ; Chen, Christine ;
Kinney, Michael D
Cc: devel@edk2.groups.io
Subject: RE: [edk2-devel] [PATCH v2]
This patch is good to me.
Reviewed-by: Bob Feng
Thanks,
Bob
-Original Message-
From: devel@edk2.groups.io On Behalf Of Sughosh Ganu
Sent: Thursday, April 22, 2021 3:51 PM
To: devel@edk2.groups.io
Cc: Kinney, Michael D ; Feng, Bob C
; Liming Gao ; Chen, Christine
; Sughosh Ganu
I’m always happy to resolve any Xcode issues.
Thanks,
Andrew Fish
> On May 11, 2021, at 7:41 AM, Laszlo Ersek wrote:
>
> On 05/11/21 02:14, Rebecca Cran wrote:
>> Thanks. The obvious toolchains that are missing from ReadMe.rst are any
>> versions of XCODE and CLANG.
>> Also, it might be nice
`CreateDirectoryIfCreating` is used only if `PermitCreation` is set.
`NewNodeIsDirectory` might not set in case of error, but that would lead
to leaving the function before invalid use.
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Cc: Jordan
Compiling for IA32 target with gcc-5.5.0 emits "maybe-uninitialized" warnings.
Compilation command: build -a IA32 -p OvmfPkg/OvmfPkgIa32.dsc -t GCC49
Sergei Dmitrouk (2):
ShellPkg/UefiShellCommandLib: suppress incorrect gcc warning
OvmfPkg/VirtioFsDxe: suppress incorrect gcc warnings
`Dupes` is used only if `Duplicates != NULL` and function is left if
allocation of memory for `Dupes` fails, so it can't be used
uninitialized.
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
Cc: Ray Ni
Cc: Zhichao Gao
Signed-off-by: Sergei Dmitrouk
---
Thanks Isaac. I'll make those changes at submission time.
-Original Message-
From: Oram, Isaac W
Sent: Tuesday, May 11, 2021 3:13 PM
To: Desimone, Nathaniel L ; devel@edk2.groups.io
Cc: Chiu, Chasel ; Kinney, Michael D
; Abbas, Mohamed ; Michael
Kubacki ; Bobroff, Zachary ;
The newer BCM2711 SoC's don't have a DMA constraint on the emmc2
controller. So we don't need to do the 1G translation. Lets
allow the AML to detect the SoC revision and return a different
_DMA resource.
Signed-off-by: Jeremy Linton
---
Platform/RaspberryPi/AcpiTables/Emmc.asl | 39
Now that we are doing SoC detection and adjusting the DMA
window it should be safe to turn DMA on by default.
Signed-off-by: Jeremy Linton
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 4 ++--
Platform/RaspberryPi/RPi4/RPi4.dsc | 2 +-
2 files changed, 3
The _DMA range needs to change depending on the SOC in use, this
was part of the problem with enabling DMA by default because there
wasn't a clear way to determine the SOC revision in use.
Now that we have an id register for that, we can pick the correct
_DMA at runtime. Lets also flip DMA on by
Under normal circumstances GenetSimpleNetworkTransmit won't be
called unless the rest of the network stack detects the link is
up. So, during normal operation when the adapter is initialized
the link naturally transitions to link up, and then is ready for
activity later in the boot sequence. If
When PXE booting with grub the network link
isn't given a chance to resume so grub's transmit
calls fail. This results in failed boots. Similarly
the DMA range for the adapter isn't right since it
doesn't have a 32-bit restriction. Again this keeps
grub from failing on 8G devices,
v1-v2:
The genet is capable of addressing the entire memory space
on the RPI4. Lets allow it to dma into those regions.
This solves intermittent issues with grub/etc being able
to communicate when the 3G limit is lifted on 8G boards.
Signed-off-by: Jeremy Linton
Reviewed-by: Jared McNeill
---
When PXE booting with grub the network link
isn't given a chance to resume so grub's transmit
calls fail. This results in failed boots. Similarly
the DMA range for the adapter isn't right since it
doesn't have a 32-bit restriction. Again this keeps
grub from failing on 8G devices,
v1-v2:
Series Reviewed-by: Isaac Oram
-Original Message-
From: Desimone, Nathaniel L
Sent: Tuesday, May 11, 2021 2:54 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Kinney, Michael D
; Oram, Isaac W ; Abbas,
Mohamed ; Michael Kubacki
; Bobroff, Zachary ;
DOPPALAPUDI, HARIKRISHNA
Subject:
Series Reviewed-by: Isaac Oram
Some nit observations. Not critical, but nice to update.
Patch 05/18:
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
would be better if it included MdePkg/MdePkg.dec in [Packages] section.
Patch 16/18:
Thanks!!
Reviewed-by: Samer El-Haj-Mahmoud
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Heinrich
> Schuchardt via groups.io
> Sent: Friday, April 30, 2021 3:40 PM
> To: EDK II Development
> Cc: Eric Jin ; G Edhaya Chandran
> ; Barton Gao ; Arvin
> Chen ; Samer
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3324
The SEV-ES stacks currently share a page with the reset code and data.
Separate the SEV-ES stacks from the reset vector code and data to avoid
possible stack overflows from overwriting the code and/or data.
When SEV-ES is enabled, invoke
Hi Etienne,
Thank you for this patch.
I am getting build errors in VariableMmDependency.inf when building for
ARM. Not sure if you are getting these or it is my development
environment (I am building on a Windows Host PC). Can you let me know
which AArch32 GCC compiler you are using, please?
Hi Etienne,
Thank you for this patch.
A space should not be there between a unary operator add its operand.
See
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/52_spacing#5-2-2-3-do-not-put-space-between-unary-operators-and-their-object
However, the existing
Hi Etienne,
Thank you for this patch.
Please find my comments below marked [SAMI].
Regards,
Sami Mujawar
On 04/05/2021 04:20 PM, Etienne Carriere wrote:
Change GenFv for Arm architecture to generate a specific jump
instruction as image entry instruction, when the target entry label
is
Hi Etienne,
Thank you for this patch.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/05/2021 04:20 PM, Etienne Carriere wrote:
Changes in ArmPkg to prepare building StandaloneMm firmware for
32bit Arm architectures.
Adds MmCommunicationDxe driver and ArmMmuPeiLib and
Hi Etienn,
This patch looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/05/2021 04:20 PM, Etienne Carriere wrote:
Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit
function IDs as per SMCCC specification. Defines also generic ARM
SVC identifier
Pushed as 8549b1739183..e1efa61c33f7
Thanks,
Regards,
Sami Mujawar
On 11/05/2021, 08:47, "Pranav Madhu" wrote:
Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami
Low Power Idle (LPI) and Collaborative Processor
For this series.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/05/2021, 08:47, "Pranav Madhu" wrote:
Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami
Low Power Idle (LPI) and Collaborative Processor
On 05/10/21 16:24, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385
>
> A VS2012 build fails with a cast conversion warning when the SEV-ES work
> area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.
>
> When casting from a PCD value to a pointer, the
On 5/11/21 6:55 AM, Laszlo Ersek wrote:
> I don't fully understand the updates in this patch:
>
> On 05/07/21 22:38, Brijesh Singh wrote:
>> BZ:
>>
On 05/10/21 21:33, Lendacky, Thomas wrote:
> On 5/10/21 9:24 AM, Lendacky, Thomas via groups.io wrote:
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385
>>
>> A VS2012 build fails with a cast conversion warning when the SEV-ES work
>> area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR
On 5/11/21 5:29 AM, Laszlo Ersek wrote:
> On 05/07/21 22:38, Brijesh Singh wrote:
>> BZ:
>>
On 05/10/21 16:24, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385
>
> A VS2012 build fails with a cast conversion warning when the SEV-ES work
> area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.
>
> When casting from a PCD value to a pointer, the
On Tue, 11 May 2021 at 05:03, gaoliming wrote:
>
> Thanks for your update. This version patches are good to me.
>
> Reviewed-by: Liming Gao
>
Merged as #1633
Thanks all,
> > -邮件原件-
> > 发件人: Rebecca Cran
> > 发送时间: 2021年5月11日 5:53
> > 收件人: devel@edk2.groups.io; Jiewen Yao ; Jian J
> >
Reviewed by Jenny Huang.
-Original Message-
From: Sheng, W
Sent: Thursday, April 29, 2021 11:55 PM
To: devel@edk2.groups.io
Cc: Huang, Jenny ; Yao, Jiewen ;
Ni, Ray ; Chaganty, Rangasai V
Subject: [PATCH] IntelSiliconPkg/VTd: Support queued invalidation interface
Add queued
Gentle reminder for ITS changes review.
The accompanying qemu git branch with ITS changes is available at
https://github.com/shashi-j/qemu.git
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75018):
This patch looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 10/05/2021 10:53 PM, Rebecca Cran wrote:
AARCH64 support has been added to BaseRngLib via the optional
ARMv8.5 FEAT_RNG.
Refactor RngDxe to support AARCH64, note support for it in the
VALID_ARCHITECTURES line
On 5/11/21 4:59 AM, Laszlo Ersek wrote:
> On 05/07/21 22:38, Brijesh Singh wrote:
>> From: Tom Lendacky
>>
>> BZ:
>>
This patch looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 10/05/2021 10:53 PM, Rebecca Cran wrote:
Make BaseRngLib more generic by moving x86-specific functionality into
'Rand' and adding files under 'AArch64' to support the optional ARMv8.5
RNG instruction RNDR that
Hi Sughosh,
Thanks for the reminder.
We need to wait for one of the BaseTools maintainers to provide an Rb for the
V2 version of this patch, then we will be able to merge.
Thanks,
Mike
From: Sughosh Ganu
Sent: Tuesday, May 11, 2021 3:21 AM
To: Kinney, Michael D ; Feng, Bob C
; Liming Gao ;
Acked-by: Jiewen Yao
Need ARM expert to double confirm.
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Ard
> Biesheuvel
> Sent: Tuesday, May 11, 2021 10:44 PM
> To: Rebecca Cran ; Yao, Jiewen
> ; Wang, Jian J
> Cc: edk2-devel-groups-io ; Kinney, Michael D
> ; Liming
On Mon, 10 May 2021 at 23:53, Rebecca Cran wrote:
>
> AARCH64 support has been added to BaseRngLib via the optional
> ARMv8.5 FEAT_RNG.
>
> Refactor RngDxe to support AARCH64, note support for it in the
> VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc.
>
> Signed-off-by:
On 05/11/21 02:14, Rebecca Cran wrote:
> Thanks. The obvious toolchains that are missing from ReadMe.rst are any
> versions of XCODE and CLANG.
> Also, it might be nice to specify _which_ GCC5 versions are supported,
> since that covers gcc 5 through 11 and gcc 5.x currently causes a build
>
Pushed as 67988fb53dbc..8549b1739183 with minor edits to doxygen comment
style.
Thanks.
Regards,
Sami Mujawar
On 10/05/2021 09:06 PM, Pranav Madhu wrote:
Changes since V2:
- Introduced CPU container object into DSDT
- Addressed comments from Sami
Changes since V1:
- Rebase the patches on
I don't fully understand the updates in this patch:
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> The Flush parameter is used to provide a hint whether the specified range
> is Mmio address. Now that we have a dedicated helper to clear the
Hi Sami,
Please find my response:
>
> Hi Pranav,
>
> Please find my response inline marked [SAMI].
>
> Regards,
>
> Sami Mujawar
>
>
> On 10/05/2021 09:06 PM, Pranav Madhu wrote:
> > The RD-E1-Edge platform includes two clusters with eight multi-thread
> > CPUs. Each of the CPUs include 32KB L1
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
> for the Mmio address range.
>
> Cc: James Bottomley
> Cc: Min Xu
> Cc: Jiewen Yao
> Cc: Tom Lendacky
> Cc:
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
> for the Mmio address range.
>
> Cc: James Bottomley
> Cc: Min Xu
> Cc: Jiewen Yao
> Cc: Tom Lendacky
> Cc:
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
> for the Mmio and NonExistent address range.
>
> Cc: James Bottomley
> Cc: Min Xu
> Cc: Jiewen Yao
> Cc: Tom
Hi Sami,
Please find my comments inline:
>
> Hi Pranav,
>
> Comparing with the V2 series, I see that updates to the following files or
> corresponding patches are missing in this series.
>
> - RdV1Mc/Pptt.aslc
> - RdN2/Pptt.aslc
>
> Is this intentional?
No
RdN2:
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> The MemEncryptSevClearMmioPageEncMask() helper can be used for clearing
> the memory encryption mask for the Mmio region.
>
> The MemEncryptSevClearMmioPageEncMask() is a simplifies version of
Hi Pranav,
Comparing with the V2 series, I see that updates to the following files
or corresponding patches are missing in this series.
- RdV1Mc/Pptt.aslc
- RdN2/Pptt.aslc
Is this intentional?
Regards,
Sami Mujawar
On 10/05/2021 09:06 PM, Pranav Madhu wrote:
Changes since V2:
-
Hi Pranav,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 10/05/2021 09:06 PM, Pranav Madhu wrote:
The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache.
On 05/07/21 22:38, Brijesh Singh wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> The RMPADJUST instruction will be used by the SEV-SNP guest to modify the
> RMP permissions for a guest page. See AMD APM volume 3 for further
> details.
>
> Cc: James
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> The PVALIDATE instruction validates or rescinds validation of a guest
> page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS
> bits OF, ZF, AF, PF and SF are set based on this
hi,
Can this patch be merged. Thanks.
-sughosh
On Mon, 26 Apr 2021 at 21:27, Kinney, Michael D
wrote:
> Reviewed-by: Michael D Kinney
>
> Mike
>
> > -Original Message-
> > From: devel@edk2.groups.io On Behalf Of Sughosh
> Ganu
> > Sent: Friday, April 23, 2021 4:29 AM
> > To:
On 05/07/21 22:38, Brijesh Singh wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is
> enabled in the guest VM. See the GHCB spec section for additional
> details.
(1) The actual section
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../DEBUG/FVTEMPMEMORYSILICON.Fv | Bin 0 -> 131072 bytes
.../DEBUG/FVTEMPMEMORYSILICON.Fv.txt | 4
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../RELEASE/FVTEMPMEMORYSILICON.Fv| Bin 0 -> 131072 bytes
.../RELEASE/FVTEMPMEMORYSILICON.Fv.txt| 4
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../DEBUG/FVPOSTMEMORYSILICON.Fv | Bin 0 -> 196608 bytes
.../DEBUG/FVPOSTMEMORYSILICON.Fv.txt | 3
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../RELEASE/FVPOSTMEMORYSILICON.Fv| Bin 0 -> 196608 bytes
.../RELEASE/FVPOSTMEMORYSILICON.Fv.txt| 3
This patch series adds silicon firmware volumes back
into the PurleySiliconBinPkg. Note that actual
binaries provided by this patch series are the original
binaries from 2018, which are unlikely to boot with the
new PurleyRefreshSiliconPkg. The purpose of this patch
series is to reinstate the
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../Intel/PurleySiliconBinPkg/FV/License.txt | 37 +++
1 file changed, 37 insertions(+)
create mode
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../BoardMtOlympus/GitEdk2MinMtOlympus.bat| 74 +++
.../BoardMtOlympus/OpenBoardPkg.dsc | 221 +++
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
Platform/Intel/Readme.md | 34 ++
Readme.md| 1 +
2 files changed, 35
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c | 362 ++
.../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf| 40 ++
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../BasePlatformHookLib/BasePlatformHookLib.c | 292 +
.../BasePlatformHookLib.inf | 36 +
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../Acpi/BoardAcpiDxe/AmlOffsetTable.c| 290 ++
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 547
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
Maintainers.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Maintainers.txt b/Maintainers.txt
index
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../Library/PchResetCommonLib.h | 59 +++
.../Pch/IncludePrivate/PchHHsioAx.h | 16 ++
This patch series revives the PurleyOpenBoardPkg. The package has been
upgraded to support the newest MinPlatformPkg and the new advanced
feature architecture. Build issues with the newest EDK II have been
fixed. Finally, I believe most (if not all) MinPlatform Architecture
violations have been
Cc: Chasel Chiu
Cc: Mike Kinney
Cc: Isaac Oram
Cc: Mohamed Abbas
Cc: Michael Kubacki
Cc: Zachary Bobroff
Cc: Harikrishna Doppalapudi
Signed-off-by: Nate DeSimone
---
.../Intel/PurleyRefreshSiliconPkg/SiPkg.dec | 390 ++
.../SiPkgCommonLib.dsc| 33
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Chuang, SofiaX
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Liming Gao ;
> Dong, Eric
> Subject: [edk2-devel][PATCH v5 6/7]
> MiniPlatformPkg:
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Chuang, SofiaX
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chiu, Chasel
> ; Desimone, Nathaniel L
>
> Subject: [edk2-devel][PATCH v5 5/7] WhiskeylakeOpenBoard: Move library path
>
>
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Chuang, SofiaX
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Jeremy Soller
> Subject: [edk2-devel][PATCH v5 4/7]
> KabylakeOpenBoard: Move
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Chuang, SofiaX
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Agyeman, Prince
> ; Chiu, Chasel
> Subject: [edk2-devel][PATCH v5 3/7]
> SimicsOpenBoard: Move ReportCpuHob library path
>
>
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> The Page State Change NAE exit will be used by the SEV-SNP guest to
> request a page state change using the GHCB protocol. See the GHCB
> spec section 4.1.6 and 2.3.1 for more detail on the
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> An SEV-SNP guest is required to perform the GHCB GPA registration. See
> the GHCB specification for further details.
>
> Cc: James Bottomley
> Cc: Min Xu
> Cc: Jiewen Yao
> Cc: Tom Lendacky
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> Version 2 of GHCB introduces advertisement of features that are supported
> by the hypervisor. See the GHCB spec section 2.2 for an additional details.
>
> Cc: James Bottomley
> Cc: Min Xu
>
Reviewed-by: Heng Luo
> -Original Message-
> From: Chuang, SofiaX
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chaganty, Rangasai V
> ; Desimone, Nathaniel L
> ; Luo, Heng
> Subject: [edk2-devel][PATCH v5 2/7]
> TigerlakeOpenBoard: Move
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> Version 2 of the GHCB spec introduces several new SNP-specific NAEs.
> Unfortunately, the names for those NAEs break the alignment. Add some
> white spaces so that the SNP support patches do not
On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> Define the SEV-SNP MSR bits.
>
> Cc: James Bottomley
> Cc: Min Xu
> Cc: Jiewen Yao
> Cc: Tom Lendacky
> Cc: Jordan Justen
> Cc: Ard Biesheuvel
> Cc: Laszlo Ersek
> Cc: Erdem Aktas
> Cc:
Enable ACPI CPPC mechanism for RD-N2 as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-N2
RD-N2 platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 214
Enable ACPI CPPC mechanism for RD-V1 quad-chip platform as defined by
the ACPI specification. The implementation uses AMU registers accessible
as Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set the
desired
RD-V1 quad-chip platform supports two LPI states, LPI1 (Standby WFI) and
LPI3 (Power-down). Add idle support for RD-V1 quad-chip platform.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 144
1 file changed, 144 insertions(+)
diff --git
Enable CPPC mechanism for RD-V1 platform as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-V1
RD-V1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). Add idle support for RD-V1 platform.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 128
1 file changed, 128 insertions(+)
diff --git
RD-N1-Edge platform in multi chip configuration supports 2 LPI states,
LPI1 (Standby WFI) and LPI3 (Power-down). The cluster supports LPI2
(Power-down) state. The LPI implementation also supports combined power
state for core and cluster.
Signed-off-by: Pranav Madhu
---
Add helper macros required for use with ACPI collaborative processor
performance control (CPPC). This patch adds macros for initializing ACPI
_CPC and _PSD control method. The CPC initializer macro initializes _CPC
control method with revision 3 as specified in Arm FFH specification
1.1. The CPC
SGI-575 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132
Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami
Low Power Idle (LPI) and Collaborative Processor Performance Control
(CPPC) are two power management mechanisms described in ACPI 6.4
specification. OSPM uses the _LPI object to select a
Add helper macros required for use with ACPI Operating System
Capabilities (_OSC) control method. The macros for capability DWORD and
return status value DWORD are defined.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 16
1 file changed, 16
RD-N1-Edge platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
From: SofiaX Chuang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298
Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Rangasai V Chaganty
Cc: Deepika Kethi Reddy
Cc: Kathappan Esakkithevar
---
From: SofiaX Chuang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298
Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Jeremy Soller
---
.../KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 11 ---
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