Thanks and will send v4 soon.
From: Kinney, Michael D
Sent: Wednesday, August 23, 2023 1:47 AM
To: Chris Li OS; Nong, Foster; devel@edk2.groups.io; Gao, Liming
Cc: Yao, Jiewen; Ni, Ray; Open Source Submission; Kinney, Michael D
Subject: RE: [edk2-devel]
[AMD Official Use Only - General]
Please see my answers inline.
> -Original Message-
> From: disc...@edk2.groups.io On Behalf Of
> Konstantin Aladyshev via groups.io
> Sent: Wednesday, August 23, 2023 1:54 AM
> To: Chang, Abner
> Cc: disc...@edk2.groups.io; devel@edk2.groups.io
>
SCT spec: https://bugzilla.tianocore.org/show_bug.cgi?id=4374
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4419
-Implement MemoryOverwriteRequestControlLock Locked with
Key State test cases
-Add remaining Assertions 33 - 49 from SCT spec
-Add Test Case to
From: "Abhi.Singh"
SCT spec: https://bugzilla.tianocore.org/show_bug.cgi?id=4374
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4419
-Implement initial test infrastructure for all test cases
including updates to: CommonGenFramework.sh, UEFI_SCT.dsc,
and Category.ini.
-Add Guid.c and
SCT spec: https://bugzilla.tianocore.org/show_bug.cgi?id=4374
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4419
-Implement MemoryOverwriteRequestControlLock Locked No Key
State test cases
-Add Assertions 23 - 32 from SCT spec
-Add Test Case to MemoryOverwriteRequestFunctionTest
Cc: G
SCT spec: https://bugzilla.tianocore.org/show_bug.cgi?id=4374
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4419
-Implement MemoryOverwriteRequestControlLockSetVariable test
cases
-Add Assertions 9 through 18 from SCT spec
-Add Test Case to MemoryOverwriteRequestFunctionTest
Cc: G
SCT spec: https://bugzilla.tianocore.org/show_bug.cgi?id=4374
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4419
-Implement MemoryOverwriteRequestControlLock Unlocked State
test cases
-Add Assertions 19, 20, 21, and 22 from SCT spec
-Add Test Case to MemoryOverwriteRequestFunctionTest
These tests support platform firmware that implement
MemoryOverwriteRequestControl & MemoryOverwriteRequestControlLock
UEFI variables in accordance with TCG PC Platform Reset Attack
Mitigation Specification.
The 6 patches are split up according to the six sections
documented in the SCT spec
SCT spec: https://bugzilla.tianocore.org/show_bug.cgi?id=4374
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4419
-Implement MemoryOverwriteRequestControlSetVariable test cases
-Add Assertions 5, 6, 7, and 8 from SCT spec
-Add Test Case to MemoryOverwriteRequestFunctionTest
Cc: G Edhaya
Hi Abhi,
See inline comments...
On 8/17/23 11:10 AM, Abhimanyu Singh via groups.io wrote:
From: "Abhi.Singh"
SCT Platform Reset Check Test
SCT spec: https://bugzilla.tianocore.org/show_bug.cgi?id=4374
Test: https://bugzilla.tianocore.org/show_bug.cgi?id=4419
-Implement initial test
On Tue, Aug 22, 2023 at 18:53:43 +0200, Marcin Juszkiewicz wrote:
> From: Shashi Mallela
>
> SBSA Reference Platform has GIC ITS support. Let make use of it to have
> complex PCI Express setups.
>
> Base address is read from TF-A via SMC call.
>
> If firmware is used with QEMU 8.0 or older
Working BZ link: 3759 – SCT test fails when RouteConfig returns
EFI_ACCESS_DENIED (tianocore.org) (
https://bugzilla.tianocore.org/show_bug.cgi?id=3759 )
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View/Reply Online (#107959):
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3759
HIIConfigAccess and HIIConfigRouting Protocol RouteConfig tests assertions
store a failure when RouteConfig returns EFI_ACCESS_DENIED. In the UEFI SPEC
RouteConfig in both protocols can return EFI_ACCESS_DENIED when the action
violates a
Thanks for the answer!
I was a little bit confused about the part, that in the same package I
actually need to provide different library implementations for the
same 'ManageabilityTransportLib', thanks for the clarification!
I think your DSC example should go into the package documentation.
As
Yes.
Mike
> -Original Message-
> From: Chris Li OS
> Sent: Tuesday, August 22, 2023 2:42 AM
> To: Nong, Foster ; Kinney, Michael D
> ; devel@edk2.groups.io; Gao, Liming
>
> Cc: Yao, Jiewen ; Ni, Ray ; Open
> Source Submission
> Subject: Re: [edk2-devel] [PATCH v3 1/1] MdePkg: Add
Reviewed-by: Michael D Kinney
> -Original Message-
> From: Jayaprakash, N
> Sent: Monday, August 21, 2023 8:22 PM
> To: devel@edk2.groups.io
> Cc: Jayaprakash, N ; Rebecca Cran
> ; Kinney, Michael D ;
> Kloper, Dimitry
> Subject: [edk2-libc Patch 1/1] edk2-libc/StdLib: file
SBSA Reference Platform can have GIC ITS present. And when it has then
we can have complex PCI Express setup (and some other things).
On systems with GIC ITS support it's address is read from TF-A via SMC
call. IORT is generated, MADT has ITS information. Linux boots and sees
GIC ITS as expected.
From: Shashi Mallela
SBSA Reference Platform has GIC ITS support. Let make use of it to have
complex PCI Express setups.
Base address is read from TF-A via SMC call.
If firmware is used with QEMU 8.0 or older then there will be no GIC ITS
support. In such case we would not add information
[AMD Official Use Only - General]
Hi Aladyshev,
We use library class to specify the desire transport interface for the
management protocol, such as MCTP, PLDM and IPMI. This way we can flexibly
support any transport interface for the management protocol.
Here is the example of using
My understanding is zero length arrays have not been legal C code since C89.
They may still function as a compiler extension.
struct foo {
size_t len;
char. Str[]0];
};
I seem to remember the reason we did not use the C99 flexible array members is
back in the day as Visual Studio 2003
Hi!
I'm trying to build `ManageabilityPkg` from the edk2-platforms
repo to issue PLDM messages via MCTP over KCS. Is it possible with
the current code? I see all the building blocks, but have trouble
putting it all together.
The main question that bothers me is what implementation should I set
Hi Mike and Foster,
So the preferred definition is as below?
RegisterBlock[]; // offset 0x0C
From: Nong, Foster
Sent: Monday, August 21, 2023 9:59 AM
To: Kinney, Michael D; Chris Li OS; devel@edk2.groups.io; Gao, Liming
Cc: Yao,
On Tue, 22 Aug 2023 at 08:25, Gerd Hoffmann wrote:
>
> On Thu, Jul 20, 2023 at 03:45:57PM +0200, Ard Biesheuvel wrote:
> > Instead of relying on raising the TPL to protect the critical sections
> > that manipulate the global bitmask that keeps track of bounce buffer
> > allocations, use
Hi Liming,
This is a bug fix and can cause data loss if the variable size > 4k.
Can it be included for the edk2-stable202308? Let me know if it requires
a BZ id.
I tried running the CI tests for this patch. But 2 of tests failed and I
don't think it has anything to do with this patch. If you are
On Thu, Jul 20, 2023 at 03:45:57PM +0200, Ard Biesheuvel wrote:
> Instead of relying on raising the TPL to protect the critical sections
> that manipulate the global bitmask that keeps track of bounce buffer
> allocations, use compare-and-exchange to manage the global variable, and
> tweak the
On Tue, Aug 22, 2023 at 09:57:14AM +0800, YuanhaoXie wrote:
> Disable PcdFirstTimeWakeUpAPsBySipi for IntelTdx, Microvm, and Xen to
> preserve the original execution of INIT-SIPI-SIPI.
>
> Cc: Eric Dong
> Cc: Ray Ni
> Cc: Rahul Kumar
> Cc: Gerd Hoffmann
> Cc: Ard Biesheuvel
> Cc: Jiewen Yao
On Wed, Aug 16, 2023 at 03:11:46PM -0500, Michael Roth wrote:
> PcdFirstTimeWakeUpAPsBySipi was recently introduced to indicate when
> the full INIT-SIPI-SIPI sequence can be skipped for AP bringup. It is
> true by default, but needs to be disabled for QEMU/OVMF where early INIT
> is not
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