Hi Ard,
Thanks,
Chao
On 2024/4/25 20:58, Ard Biesheuvel wrote:
On Thu, 25 Apr 2024 at 14:13, Chao Li wrote:
Separate QemuFwCfgLibMmio.c into two files named QemuFwCfgLibMmio.c and
QemuFwCfgLibMmioDxe.c, added a new header named
QemuFwCfgLibMmioInternal.h for MMIO version.
Build-tested only
Hi EDKII stewards,
Could you please review the libspdm license?
The libspdm(https://github.com/DMTF/libspdm) is a implementation that follows
the DMTF SPDM(https://www.dmtf.org/standards/spdm) spec.
And the libspdm library is under DMTF repo.
The license is:
Hello Everyone,
I'm working on a project with edk2, and these guys are trying to port edk2
to STM32MP25 platforms. I have a problem with the module SerialPortLib,
specifically the function *SerialPortPoll*. I made a test that adds a line
of debug in this function and adds a MmioWrite8 to a
It is near to the GicDistributorBase (0x4ac1) of STM32MP25
Le jeu. 25 avr. 2024 à 02:21, Andrew (EFI) Fish a écrit :
> The fault address is 0x0004AC14. Is that in the address range of
> the GIC for this platform? What does that Physical address map to you on
> the STM32MP25?
>
>
On Thu, Apr 25, 2024 at 11:42:01AM +0100, Alejandro Vallejo wrote:
> Hi,
>
> On 25/04/2024 08:31, Gerd Hoffmann wrote:
> > On Wed, Apr 24, 2024 at 02:36:32PM +0100, Alejandro Vallejo wrote:
> >> Bump the compile-time constant for maximum processor count from 64 to 128
> >> in order to allow that
Hi Felix/ Liming,
Thank you for your comments. Patch 6 has been updated to only focus on
consolidating the revision macros.
Patch Link:
https://edk2.groups.io/g/devel/message/118246?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Csachin%2C20%2C2%2C0%2C105721897
PR Link:
Hi Ard,
Thanks,
Chao
On 2024/4/25 21:02, Ard Biesheuvel wrote:
On Thu, 25 Apr 2024 at 14:13, Chao Li wrote:
Added the HOB methods to load and store the QEMU firmware configure
address, data address and DMA address, which are not enabled during the
DXE stage.
Build-tested only (with
Hi Ard,
Thanks,
Chao
On 2024/4/26 09:20, Chao Li wrote:
Hi Ard,
On 2024/4/25 21:02, Ard Biesheuvel wrote:
On Thu, 25 Apr 2024 at 14:13, Chao Li wrote:
Added the HOB methods to load and store the QEMU firmware configure
address, data address and DMA address, which are not enabled during
Looks good to me.
Reviewed-by: Yi Li
-Original Message-
From: Hou, Wenxing
Sent: Wednesday, April 24, 2024 4:25 PM
To: devel@edk2.groups.io
Cc: Yao, Jiewen ; Li, Yi1
Subject: [PATCH v2] Add SHA3/SM3 functions with openssl for Mbedtls
REF:
Hi Gerd,
Thanks,
Chao
On 2024/4/25 15:40, Gerd Hoffmann wrote:
Hi,
+EFI_GUID mFwCfgSelectorAddressGuid = FW_CONFIG_SELECTOR_ADDRESS_HOB_GUID;
+EFI_GUID mFwCfgDataAddressGuid = FW_CONFIG_DATA_ADDRESS_HOB_GUID;
+EFI_GUID mFwCfgDmaAddressGuid = FW_CONFIG_DMA_ADDRESS_HOB_GUID;
On Thu, 25 Apr 2024 at 10:10, Chao Li wrote:
>
> Hi Gerd,
>
>
> Thanks,
> Chao
> On 2024/4/25 15:40, Gerd Hoffmann wrote:
>
> Hi,
>
> +EFI_GUID mFwCfgSelectorAddressGuid = FW_CONFIG_SELECTOR_ADDRESS_HOB_GUID;
> +EFI_GUID mFwCfgDataAddressGuid = FW_CONFIG_DATA_ADDRESS_HOB_GUID;
> +EFI_GUID
Hi Ard and Gerd,
Thanks,
Chao
On 2024/4/25 16:11, Ard Biesheuvel wrote:
On Thu, 25 Apr 2024 at 10:10, Chao Li wrote:
Hi Gerd,
Thanks,
Chao
On 2024/4/25 15:40, Gerd Hoffmann wrote:
Hi,
+EFI_GUID mFwCfgSelectorAddressGuid = FW_CONFIG_SELECTOR_ADDRESS_HOB_GUID;
+EFI_GUID
Hi,
> That means the SMMRevId is 0_xx64h for AMD64 processor. But I am not
> sure what the value is for AMD32 processor. Maybe 0 according to the
> OVMF logic.
The smm emulation in the linux kernel uses 0 and 0x64.
> But, I am very suspicious about the logic in AMD's version as below:
> ---
Hi,
> +UINTN mFwCfgSelectorAddress;
> +UINTN mFwCfgDataAddress;
> +UINTN mFwCfgDmaAddress;
Hmm, global variables for PEI? I think the point of storing these in
the HOB is to avoid the need for global variables? Also does that work
when running PEI in-place from flash?
> +RETURN_STATUS
>
Hi,
> Let me explain more why need this change:
>
> 1. The EFI_SMM_SMRAM_MEMORY_GUID HOB, as defined in the PI specification, is
> used to describe the SMRAM memory regions supported by the platform. This HOB
> should be produced during the memory detection phase to align with the PI
>
On Wed, Apr 24, 2024 at 02:36:32PM +0100, Alejandro Vallejo wrote:
> Bump the compile-time constant for maximum processor count from 64 to 128
> in order to allow that many vCPUs to be brought online on Xen guests with
> the default OVMF configuration.
> + # UefiCpuPkg PCDs related to initial AP
Hi,
> +EFI_GUID mFwCfgSelectorAddressGuid = FW_CONFIG_SELECTOR_ADDRESS_HOB_GUID;
> +EFI_GUID mFwCfgDataAddressGuid = FW_CONFIG_DATA_ADDRESS_HOB_GUID;
> +EFI_GUID mFwCfgDmaAddressGuid = FW_CONFIG_DMA_ADDRESS_HOB_GUID;
Oh. I assumed that would be obvious (because it's common
>
> Creating the EFI_SMM_SMRAM_MEMORY_GUID HOB should be moved to its
> own
> function. Also move over the comments from SmmAccess describing the
> regions please.
>
> Adding a reference to the PI spec section describing this would be good
> too.
>
Got it, I will refine the patch to V4 based
Hi Gerd,
Thanks,
Chao
On 2024/4/25 15:53, Gerd Hoffmann wrote:
Hi,
+UINTN mFwCfgSelectorAddress;
+UINTN mFwCfgDataAddress;
+UINTN mFwCfgDmaAddress;
Hmm, global variables for PEI? I think the point of storing these in
the HOB is to avoid the need for global variables? Also does that
Hi @gaoliming,
Could you provide the eta when the patch can be merged?
Thanks,
Xianglei
-Original Message-
From: Cai, Xianglei
Sent: Thursday, April 18, 2024 5:00 PM
To: gaoliming ; devel@edk2.groups.io
Cc: Ni, Ray ; Lewandowski, Krzysztof
; Huang, Jenny ; Shih,
More ; Chiu, Ian
Hi Gerd,
I get it, I will refactor the code as soon as I can, it looks like
there's still some work and will take some time. I will try to send the
V3 tonight if possible.
Thanks,
Chao
On 2024/4/25 17:02, Gerd Hoffmann wrote:
On Thu, Apr 25, 2024 at 04:06:13PM +0800, Chao Li wrote:
Hi
Hi,
On 25/04/2024 08:31, Gerd Hoffmann wrote:
> On Wed, Apr 24, 2024 at 02:36:32PM +0100, Alejandro Vallejo wrote:
>> Bump the compile-time constant for maximum processor count from 64 to 128
>> in order to allow that many vCPUs to be brought online on Xen guests with
>> the default OVMF
Added the HOB methods to load and store the QEMU firmware configure
address, data address and DMA address, which are not enabled during the
DXE stage.
Build-tested only (with "ArmVirtQemu.dsc and RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Added the PEI stage library for QemuFwCfgMmioLib, which uses the FDT to
find the fw_cfg and parse it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Co-authored-by: Xianglai Li
Signed-off-by: Chao Li
---
Separate QemuFwCfgLibMmio.c into two files named QemuFwCfgLibMmio.c and
QemuFwCfgLibMmioDxe.c, added a new header named
QemuFwCfgLibMmioInternal.h for MMIO version.
Build-tested only (with "ArmVirtQemu.dsc and RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard
Patch1: Added three PCDs for QemuFwCfgLibMmio
Patch2: Sparate QemuFwCfgLibMmio.c into two files and default as DXE
stage library.
Patch3: Added QemuFwCfgMmiLib PEI version
Patch4: Rename QemuFwCfgLibMmio.inf to QemuFwCfgMmioDxeLib.inf and
enable it in AARCH64 and RISCV64.
V1 -> V2:
1. Use HOBs
Copy QemuFwCfgLibMmio.inf to QemuFwCfgMmioDxeLib.inf,
QemuFwCfgLibMmio.inf will be deleted when all platforms switching is
completed.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
On Thu, Apr 25, 2024 at 04:06:13PM +0800, Chao Li wrote:
> Hi Gerd,
>
>
> Thanks,
> Chao
> On 2024/4/25 15:53, Gerd Hoffmann wrote:
> >Hi,
> >
> > > +UINTN mFwCfgSelectorAddress;
> > > +UINTN mFwCfgDataAddress;
> > > +UINTN mFwCfgDmaAddress;
> > Hmm, global variables for PEI? I think
Hi @gaoliming
Could you provide the eta when the patch can be merged?
Thanks,
Xianglei
-Original Message-
From: Cai, Xianglei
Sent: Thursday, April 18, 2024 4:59 PM
To: gaoliming ; devel@edk2.groups.io
Cc: Ni, Ray ; Lewandowski, Krzysztof
; Huang, Jenny ; Shih,
More
Subject: RE:
We can have more than one PCI Express bus. So instead of having static
description in DSDT we create SSDT table for each existing PCIe bus.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 +
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |
SbsaQemu assumes that there is only one PCI Express bus. But there can
be multiple PCIe buses as NUMA systems can get 'pxb-pcie' HostBridge
devices added.
Let scan for all PCIe buses and report them back so EDK2 will be able to
find all expansions.
Signed-off-by: Marcin Juszkiewicz
---
/AcpiTables/Dsdt.asl | 302 --
Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 --
.../Drivers/SbsaQemuAcpiDxe/SsdtTemplate.asl| 82 +++
10 files changed, 982 insertions(+), 439 deletions(-)
---
base-commit: 73cfdc4afff3e641be217b31b985761ef8338412
change-id: 20240425
We want to have dynaminc PCI Express variables. Which forces us to
generate MCFG from C code.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 -
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 83
All of platforms are switching to QemuFwCfgMmioDxeLib.inf, remove
QemuFwCfgLibMmio.inf now.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf | 51
Enable QemuFwCfgMmioDxeLib.inf in ArmVirtQemu.dsc and
ArmVirtQemuKernel.dsc.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Cc: Leif Lindholm
Cc: Sami Mujawar
Signed-off-by: Chao Li
Enable QemuFwCfgMmioDxeLib.inf in RiscVVirtQemu.dsc
Build-tested only (with "RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Chao Li
---
On Thu, 25 Apr 2024 at 14:13, Chao Li wrote:
>
> Separate QemuFwCfgLibMmio.c into two files named QemuFwCfgLibMmio.c and
> QemuFwCfgLibMmioDxe.c, added a new header named
> QemuFwCfgLibMmioInternal.h for MMIO version.
>
> Build-tested only (with "ArmVirtQemu.dsc and RiscVVirtQemu.dsc").
>
> BZ:
Hi,
> It's a bit more complicated than setting it at build time, but we can
> always ask Xen how many vcpu we have and set the PCD accordingly. This
> is something that can happen in OvmfPkg/XenPlatformPei module.
Exactly.
> But to be honest, I don't know if it's worth it, because I don't
On Thu, 25 Apr 2024 at 14:13, Chao Li wrote:
>
> Added the HOB methods to load and store the QEMU firmware configure
> address, data address and DMA address, which are not enabled during the
> DXE stage.
>
> Build-tested only (with "ArmVirtQemu.dsc and RiscVVirtQemu.dsc").
>
> BZ:
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