Re: [edk2-devel] [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include headers

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty  

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:15 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include 
headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files common to CPU modules.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h 
   |  45 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
 | 106 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclockingConfig.h
| 141 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h  
   |  54 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h
  | 179 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h
 |  78 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h
   | 149 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h 
   |  66 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h 
   |  16 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h 
   | 113 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h 
   |  88 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h   
   |  23 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h  
   | 100 
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h   
   | 261 
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h 
   |  90 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h
   | 118 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h  
   |  84 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h  
   | 123 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPolicyProtocol.h
   |  50 
 19 files changed, 1884 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
new file mode 100644
index 00..47a98131d0
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
@@ -0,0 +1,45 @@
+/** @file
+  CPU Config Block.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+#define CPU_CONFIG_REVISION 3
+
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  CPU Configuration Structure.
+
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Deprecate and move SkipMpInit to CpuConfigLibPreMemConfig.
+  Revision 3:
+  - Move DebugInterfaceEnable from CPU_TEST_CONFIG.
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
+  /**
+Enable or Disable Advanced Encryption Standard (AES) feature.
+For some countries, this should be disabled for legal reasons.
+-0: Disable
+- 1: Enable
+  **/
+  UINT32 AesEnable: 1;
+  UINT32 SkipMpInit   : 1;///< @deprecated since 
revision 2. For Fsp only, Silicon Initialization will skip MP Initialization 
(including BSP) if enabled. For non-FSP, this should always be 0.
+  UINT32 DebugInterfaceEnable : 1;///< Enable or Disable 
processor debug features; 0: Disable; 1: Enable.
+  UINT32 RsvdBits : 28;   ///< Reserved for future use
+  EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode 
patch that is suitable for this processor.
+} CPU_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_CONFIG_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
new file mode 100644
index 00..ce965a7510
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
@@ -0,0 +1,106 @@
+/** @file
+  CPU Security PreMemory Config Block.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+
+#define CP

Re: [edk2-devel] Determining TSC frequency programmatically

[Vitaly Cheptsov via Groups.Io]

Andrew,

Thanks for the reminder for CpuDxe.

I think we saw CpuDxe calculation some time ago, and it was most likely a 
reason we went with a very similar approach to determine the TSC frequency as a 
fallback mechanism. It, however, is in fact prone to issues, putting aside the 
non-guaranteed period and CPU frequency match. Basically, there are two 
problems:

1. The code implemented in C is subject to minor time drifts, which results in 
slightly different results across the reboots. The calculation based on CPUID 
15H is more accurate.
2. The lack of TPL changes during frequency measurement results in EFI_EVENTs 
potentially interrupting the process and thus making the resulting value very 
inaccurate. Since the value is cached there is not always a possibility to 
avoid it.

EmulatorPkg is a bit of a special case, which we think we know about :), 
actually thanks for fixing it up on macOS, this is appreciated!

All in all, I would say that there really needs to exist a decent library, 
which most likely CpuDxe should make a use of as well.

Best wishes,
Vitaly

> 16 авг. 2019 г., в 21:35, Andrew Fish  написал(а):
> 
> Vitaly,
> 
> As Mike mentioned platforms can know more info about how they are constructed 
> thus you may not want to have a lot of generic discovery code floating about 
> if you don't really need it. 
> 
> One option could be to pass up the TSC Frequency/Period via some EFI 
> mechanism so generic code can be told by platform specific code. 
> 
> The PI spec already has an abstraction for a CPU based timer that is 
> architecture neutral. The CPU Architectural Protocol has a GetTimerValue() 
> member function. 
> https://github.com/tianocore/edk2/blob/master/MdePkg/Include/Protocol/Cpu.h#L220
>  
> 
> 
> For X86 it returns TSC
> https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/CpuDxe/CpuDxe.c#L289 
> 
> 
> EFI Systems are not required to implement PI so we usually don't encourage 
> generic EFI code to go after PI APIs. 
> 
> I'd also point out that using TSC can break in things like the EmulatorPkg as 
> you end up running in ring 0 and TSC access is blocked. 
> https://github.com/tianocore/edk2/blob/master/EmulatorPkg/CpuRuntimeDxe/Cpu.c#L352
>  
> 
> https://github.com/tianocore/edk2/blob/master/EmulatorPkg/Unix/Host/EmuThunk.c#L250
>  
> 
> 
> 
> I would point that a library that did TSC frequency discovery would likely be 
> useful for the UefiCpuPkg CpuDxe driver. 
> 
> Thanks,
> 
> Andrew Fish
> 
>> On Aug 15, 2019, at 2:10 PM, Vitaly Cheptsov via Groups.Io 
>> mailto:vit9696=protonmail@groups.io>> 
>> wrote:
>> 
>> Hello,
>> 
>> I initially raised this question in a new TimerLib patch[1], but as the 
>> discussion was getting more distracted, I decided to create a separate 
>> thread in hopes new people could join.
>> 
>> The issue is that our UEFI bootloader needs to obtain TSC frequency to pass 
>> it to our specialised operating system that uses TSC for scheduling on x86.
>> 
>> For a while we went with ACPI power management timer to measure the 
>> frequency, but as modern Intel CPUs support CPUID 15H leaf 
>> (CPUID_TIME_STAMP_COUNTER) we try to use where possible for better accuracy. 
>> The issue with this CPUID leaf is that the crystal clock frequency returned 
>> in ECX register is optional and therefore can be 0. Intel SDM suggests to 
>> use a static value in this case[2], but it is completely opaque on how to 
>> match the running CPU with its static value from SDM.
>> 
>> Initially we went with CPUID model checking, but this failed badly for Xeon 
>> Scalable and Xeon W, as they share the CPUID (06_55H) but have different 
>> crystal clock frequencies (25 MHz vs 24 MHz accordingly). Donald Kuo gave a 
>> good hint in the previous thread that client CPUs usually get 24 MHz crystal 
>> clock, server CPUs have 25, and Atoms have 19.2. This, however, does not 
>> make the situation easier as we do not see a way to determine CPU vertical 
>> segment without e.g. parsing the CPUID brand string.
>> 
>> Apparently, we are not alone, and different open-source operating systems 
>> have different workarounds to this issue. For example, Linux kernel went 
>> with using marketing frequency from CPUID 16H leaf 
>> (CPUID_PROCESSOR_FREQUENCY)[3], and BSD flavours fallback to older methods 
>> when neither crystal clock frequency can be obtained through CPUID 15H, nor 
>> unambiguous CPUID models exist to be able to use static values.
>> 
>> Another issue we see with EDK II TimerLib implementations for x86 is that 
>> they are very model specific. As Michael Kinney said, the situation is not a 
>> problem when you use TimerLib for BSP bringup

Re: [edk2-devel] [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package
> DSC files
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 215
> 
>  Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc | 130
> 
>  Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc   |  69 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc |  33 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc  |  37 
>  Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc |  21 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc  |  44 
>  7 files changed, 549 insertions(+)
> 
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
> b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
> new file mode 100644
> index 00..37c77d8f63
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
> @@ -0,0 +1,215 @@
> +## @file
> +#  Component description file for the Coffee Lake silicon package DSC file.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[PcdsFeatureFlag]
> +gSiPkgTokenSpaceGuid.PcdTraceHubEnable   |FALSE
> +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
> +gSiPkgTokenSpaceGuid.PcdAtaEnable|FALSE
> +gSiPkgTokenSpaceGuid.PcdSiCsmEnable  |FALSE
> +gSiPkgTokenSpaceGuid.PcdUseHpetTimer |TRUE
> +gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE
> +gSiPkgTokenSpaceGuid.PcdAcpiEnable   |FALSE
> +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
> +gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
> +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|FALSE
> +gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
> +gSiPkgTokenSpaceGuid.PcdJhiEnable|FALSE
> +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE
> +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE
> +gSiPkgTokenSpaceGuid.PcdOverclockEnable  |FALSE
> +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable   |FALSE
> +gSiPkgTokenSpaceGuid.PcdBdatEnable   |TRUE
> +gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
> +gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
> +gSiPkgTokenSpaceGuid.PcdSaDmiEnable  |TRUE
> +gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
> +gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
> +gSiPkgTokenSpaceGuid.PcdSaOcEnable   |TRUE
> +gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
> +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable   |TRUE
> +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE
> +gSiPkgTokenSpaceGuid.PcdCflCpuEnable |FALSE
> +gSiPkgTokenSpaceGuid.PcdOcWdtEnable  |TRUE
> +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable   |TRUE
> +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
> +
> +[PcdsFixedAtBuild.common]
> +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress   |0xE000
> +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x1000
> +
> +  gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin|10
> +  gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax|18
> +
> +[PcdsDynamicDefault.common]
> +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength  |0x1000
> +
> +## Specifies the AP wait loop state during POST phase.
> +#  The value is defined as below.
> +#  1: Place AP in the Hlt-Loop state.
> +#  2: Place AP in the Mwait-Loop state.
> +#  3: Place AP in the Run-Loop state.
> +# @Prompt The AP wait loop state.
> +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> +## Specifies the AP target C-state for Mwait during POST phase.
> +#  The default value 0 means C1 state.
> +#  The value is defined as below. # @Prompt The specified AP
> +target C-state for Mwait.
> +gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
> +
> +[Defines]
> +  PLATFORM_NAME = CoffeelakeSiliconPkg
> +  PLATFORM_GUID = A45CA44C-AB04-4932-A77C-5A7179F66A22
> +  PLATFORM_VERSION = 0.4
> +  DSC_SPECIFICATION = 0x00010005
> +  OUTPUT_DIRECTORY = Build/CoffeelakeSiliconPkg
> +  SUPPORTED_ARCHITECTURES = IA32|X64
> +  BUILD_TARGETS = DEBUG|RELEASE
> +  SKUID_IDENTIFIER = DEFAULT
> +
> +  DEFINE   PLATFORM_SI_PACKAGE= CoffeelakeSiliconPkg
> +
> +  #
> +  # Defin

Re: [edk2-devel] [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty  

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:15 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and 
Include headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Create the CoffeelakeSiliconPkg to provide an initial package for
silicon initialization code for Coffee Lake (CFL) and Whiskey Lake
(WHL) generation products.

* Major areas of functionality are categorized into CPU, Management
  Engine (ME), Platform Controller Hub (PCH), and System Agent
  subdirectories.
* Common libraries and headers are kept at the root of the package.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec  | 
714 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h  |  
53 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h |  
89 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h| 
291 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h | 
157 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h   |  
64 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h |  
28 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h | 
123 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h |  
58 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h  | 
110 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h  |  
22 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h   |  
34 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h | 
319 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h |  
29 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h  |  
26 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h   |  
71 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h|  
60 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h |  
55 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h  |  
19 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h   |  
65 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h |  
23 +
 21 files changed, 2410 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec 
b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
new file mode 100644
index 00..fa8c11e93d
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
@@ -0,0 +1,714 @@
+## @file
+# Component description file for the Silicon Reference Code.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME  = SiPkg
+PACKAGE_VERSION   = 0.1
+PACKAGE_GUID  = F245E276-44A0-46b3-AEB5-9898BBCF008D
+
+[Includes]
+  Include
+  SampleCode/Include
+  SampleCode/MdeModulePkg/Include
+  SampleCode/IntelFrameworkPkg/Include
+  #
+  # SystemAgent
+  #
+  SystemAgent/Include
+  SystemAgent/MemoryInit/Include
+  SystemAgent/AcpiTables
+  #
+  # Cpu
+  #
+  Cpu/Include
+  #
+  # Me
+  #
+  Me/Include
+  #
+  # Pch
+  #
+  Pch/Include
+
+[Guids.common.Private]
+  #
+  # PCH
+  #
+  gPchDeviceTableHobGuid   = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66, 
0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}
+  gPchConfigHobGuid= { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd9, 
0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}
+  gGpioLibUnlockHobGuid= { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6, 
0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
+  gSiScheduleResetHobGuid  = { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC1, 
0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }}
+
+[Guids]
+##
+## MdeModulePkg
+##
+gEfiMemoryTypeInformationGuid  =  {0x4c19049f, 0x4137, 0x4dd3, {0x9c, 0x10, 
0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}}
+gEfiCapsuleVendorGuid  =  {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36, 
0xec, 0xbd, 0x3c, 0x8b, 0xe2}}
+gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0x0, 
0x90, 0x27, 0x3f, 0xc1, 0x4d}}
+
+##
+## IntelFrameworkPkg
+##
+gEfiSmmPeiSmramMemoryReserveGuid =  {0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 
0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}}
+
+##
+## Common
+##
+## Include/ConfigBlock/SiConfig.h
+gSiConfigGuid = {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97, 
0x38, 0x59, 0xd8 }}
+gSiPkgTokenSpaceGuid  =  {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43, 0x66, 
0x99, 0xcb, 0xe4, 

Re: [edk2-devel] [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Gao, Liming ; Desimone,
> Nathaniel L ; Kinney, Michael D
> ; Sinha, Ankit 
> Subject: [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to
> global build config and documentation
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083
> 
> * Adds the WhiskeylakeURvp board as a build option in build.cfg so it
>   it is listed as a valid build target.
> * Updates relevant Readme.md files to include instructions for
>   WhiskeylakeOpenBoardPkg.
> * Adds the maintainers for WhiskeylakeOpenBoardPkg to maintainers.txt.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Liming Gao 
> Cc: Nate DeSimone 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Maintainers.txt  |  5 +++
>  Platform/Intel/Readme.md | 44 +---
> Platform/Intel/build.cfg |  4 +-
>  Readme.md|  1 +
>  4 files changed, 38 insertions(+), 16 deletions(-)
> 
> diff --git a/Maintainers.txt b/Maintainers.txt index bc8cbd6458..b16432bf87
> 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -98,6 +98,11 @@ M: Shifei A Lu 
>  M: Xiaohu Zhou 
>  M: Isaac W Oram 
> 
> +Platform/Intel/WhiskeylakeOpenBoardPkg
> +M: Chasel Chiu 
> +M: Michael Kubacki 
> +M: Nate DeSimone 
> +
>  Platform/Intel/Tools
>  M: Bob Feng 
>  M: Liming Gao 
> diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index
> 00f42985a2..aaf6ef4d3e 100644
> --- a/Platform/Intel/Readme.md
> +++ b/Platform/Intel/Readme.md
> @@ -53,9 +53,10 @@ A UEFI firmware implementation using MinPlatformPkg
> is constructed using the fol
> 
> 
>  ## Board Support
> +* The `ClevoOpenBoardPkg` contains board implementations for Clevo
> systems.
>  * The `KabylakeOpenBoardPkg` contains board implementations for Kaby
> Lake systems.
>  * The `PurleyOpenBoardPkg` contains board implementations for Purley
> systems.
> -* The `ClevoOpenBoardPkg` contains board implementations for Clevo
> systems.
> +* The `WhiskeylakeOpenBoardPkg` contains board implementations for
> Whiskey Lake systems.
> 
>  ## Board Package Organization
>  The board package follows the standard EDK II package structure with the
> following additional elements and guidelines:
> @@ -189,7 +190,12 @@ return back to the minimum platform caller.
>|   |||---build_config.cfg: 
> BoardMtOlympus
> specific
>|   ||| build 
> settings, environment
> variables.
>|   |||---build_board.py: Optional 
> board-specific
> pre-build,
> -  |   |||   build, 
> post-build and clean
> functions.
> +  |   ||build, 
> post-build and clean
> functions.
> +  |   ||
> +  |   ||--WhiskeylakeOpenBoardPkg
> +  |   |||--WhiskeylakeURvp
> +  |   |||---build_config.cfg: 
> WhiskeylakeURvp
> specific build
> +  |   ||  settings 
> environment
> variables.
>|--FSP
>
> 
> @@ -222,19 +228,6 @@ Users can also flash the UEFI firmware image to the
> highest area of the flash re
> 
>  ### **Known limitations**
> 
> -**KabylakeOpenBoardPkg**
> -1. This firmware project has only been tested on the Intel KabylakeRvp3
> board.
> -2. This firmware project has only been tested booting to Microsoft Windows
> 10 x64 with AHCI mode and Integrated Graphic
> -  Device.
> -3. The Windows build was tested on Windows 10 with Microsoft Visual Studio
> 2015.
> -4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
> -5. The build was tested with NASM version 2.11.08.
> -
> -**PurleyOpenBoardPkg**
> -1. This firmware project has only been tested on the Microsoft MtOlympus
> board.
> -2. This firmware project has only been tested booting to Microsoft Windows
> Server 2016 with NVME on M.2 slot.
> -3. This firmware project build has only been tested using the Microsoft 
> Visual
> Studio 2015 compiler.
> -
>  **ClevoOpenBoardPkg**
>  1. Currently, support is only being added for the N1xxWU series of boards.
>  2. The Windows build was tested on Windows 10 with Microsoft Visual Studio
> 2015 compiler.
> @@ -244,6 +237,27 @@ Users can also flash the UEFI firmware image to the
> highest area of the flash re  6. The firmware project applies to all Clevo
> supported board configurations but is only being tested on System 76 Galago
>Pro devices.
> 
> +**KabylakeOpenBoardPkg**
> +1. This firmware project has only been tested on the Intel KabylakeRvp3
> board.
> +2. This firmware project has only been tested booting to Microsoft
> +Windows 10 x64 with 

Re: [edk2-devel] [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add
> library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds CPU library class instances.
> 
> * BaseCpuMailboxLibNull - Generic CPU mailbox interaction services.
> * PeiCpuPolicyLib - CPU policy configuration services.
> * PeiCpuPolicyLibPreMem - CPU policy pre-memory configuration services.
> * PeiDxeSmmCpuPlatformLib - CPU platform services.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/Base
> CpuMailboxLibNull.inf |  22 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy
> Lib.inf |  65 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy
> LibPreMem.inf   |  43 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/P
> eiDxeSmmCpuPlatformLib.inf |  39 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy
> Library.h   |  30 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/C
> puPlatformLibrary.h|  28 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/Base
> CpuMailboxLibNull.c   |  90 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPoli
> cy.c| 293 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPoli
> cyPreMem.c  | 108 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy
> Lib.c   | 434 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicy
> LibPreMem.c | 160 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/C
> puPlatformLibrary.c| 415 +++
>  12 files changed, 1727 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/Ba
> seCpuMailboxLibNull.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/Ba
> seCpuMailboxLibNull.inf
> new file mode 100644
> index 00..4fcfca4670
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/Ba
> seCpuMailboxLibNull.inf
> @@ -0,0 +1,22 @@
> +## @file
> +# Component description file for Cpu Mailbox Null Lib
> +#
> +# Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = BaseCpuMailboxLibNull
> +FILE_GUID = 74F470BC-1769-4732-B9C0-EE9AB0B12411
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = CpuMailboxLib
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +
> +[Sources]
> +BaseCpuMailboxLibNull.c
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPoli
> cyLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPoli
> cyLib.inf
> new file mode 100644
> index 00..c986e35360
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPoli
> cyLib.inf
> @@ -0,0 +1,65 @@
> +## @file
> +# Component description file for the PeiCpuPolicyLib library.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = PeiCpuPolicyLib
> +FILE_GUID = 5baafc8f-25c6-4d19-b141-585757509372
> +VERSION_STRING = 1.0
> +MODULE_TYPE = PEIM
> +LIBRARY_CLASS = CpuPolicyLib
> +
> +
> +[LibraryClasses]
> +DebugLib
> +IoLib
> +PeiServicesLib
> +BaseMemoryLib
> +MemoryAllocationLib
> +CpuPlatformLib
> +PciSegmentLib
> +SaPlatformLib
> +SiConfigBlockLib
> +PostCodeLib
> +PcdLib
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +UefiCpuPkg/UefiCpuPkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> +PeiCpuPolicyLib.c
> +PeiCpuPolicyLibrary.h
> +CpuPrintPolicy.c
> +PeiCpuPolicyLibPreMem.c
> +CpuPrintPolicyPreMem.c
> +
> +[Ppis]
> +gSiPolicyPpiGuid## CONSUMES
> +gSiPreMemPolicyPpiGuid  ## CONSUMES
> +
> +[FixedPcd]
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> +
> +[Pcd]
> +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode  ## Produces
> +
> +[Guids]
> +gCpuConfigGuid  ## PRODUCES
> +gCpuSgxConfigGuid   ## PRODUCES
> +gCpuPowerMgmtBasicConfigGuid

Re: [edk2-devel] [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode:
> Add Include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds header files common to silicon Sample Code.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha >
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformL
> ib.h |   82 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/
> Guid/SmramMemoryReserve.h  |   51 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/
> Protocol/LegacyBios.h  | 1513 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/
> Protocol/LegacyInterrupt.h |  118 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gui
> d/AcpiS3Context.h|   65 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gui
> d/ConsoleOutDevice.h |   17 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gui
> d/MemoryTypeInformation.h|   30 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Libr
> ary/ResetSystemLib.h|   80 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/
> SmmAccess.h |  137 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/
> SmmControl.h|   87 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Pro
> tocol/SmmVariable.h  |   33 +
>  11 files changed, 2213 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatfor
> mLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatfor
> mLib.h
> new file mode 100644
> index 00..829d1190fc
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatfor
> mLib.h
> @@ -0,0 +1,82 @@
> +/** @file
> +  Prototype of SEC Platform hook library.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef  _SEC_PLATFORM_LIB_H_
> +#define  _SEC_PLATFORM_LIB_H_
> +
> +#include 
> +#include 
> +
> +/**
> +  A developer supplied function to perform platform specific operations.
> +
> +  It's a developer supplied function to perform any operations appropriate to
> a
> +  given platform. It's invoked just before passing control to PEI core by SEC
> +  core. Platform developer may modify the SecCoreData passed to PEI Core.
> +  It returns a platform specific PPI list that platform wishes to pass to 
> PEI core.
> +  The Generic SEC core module will merge this list to join the final list 
> passed
> to
> +  PEI core.
> +
> +  @param  SecCoreData   The same parameter as passing to PEI core. It
> +could be overridden by this function.
> +
> +  @return The platform specific PPI list to be passed to PEI core or
> +  NULL if there is no need of such platform specific PPI list.
> +
> +**/
> +EFI_PEI_PPI_DESCRIPTOR *
> +EFIAPI
> +SecPlatformMain (
> +  IN OUT   EFI_SEC_PEI_HAND_OFF*SecCoreData
> +  );
> +
> +
> +/**
> +  This interface conveys state information out of the Security (SEC) phase 
> into
> PEI.
> +
> +  @param  PeiServices   Pointer to the PEI Services Table.
> +  @param  StructureSize Pointer to the variable describing size 
> of
> the input buffer.
> +  @param  PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.
> +
> +  @retval EFI_SUCCESS   The data was successfully returned.
> +  @retval EFI_BUFFER_TOO_SMALL  The buffer was too small.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecPlatformInformation (
> +  IN CONST EFI_PEI_SERVICES **PeiServices,
> +  IN OUT   UINT64   *StructureSize,
> + OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord
> +  );
> +
> +/**
> +  This interface conveys performance information out of the Security (SEC)
> phase into PEI.
> +
> +  This service is published by the SEC phase. The SEC phase handoff has an
> optional
> +  EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the
> +  PEI Foundation. As such, if the platform supports collecting performance
> data in SEC,
> +  this information is encapsulated into the data structure abstracted by this
> service.
> +  This information is collected for the boot-strap processor (BSP) on IA-32.
> +
> 

Re: [edk2-devel] [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add
> SMM library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds PCH SMM library class instances.
> 
> * SmmSpiFlashCommonLib
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/Sm
> mSpiFlashCommonLib.inf |  51 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiF
> lashCommon.c | 196 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiF
> lashCommonSmmLib.c   |  54 ++
>  3 files changed, 301 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/S
> mmSpiFlashCommonLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/S
> mmSpiFlashCommonLib.inf
> new file mode 100644
> index 00..abc919867c
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLi
> +++ b/SmmSpiFlashCommonLib.inf
> @@ -0,0 +1,51 @@
> +## @file
> +# SMM Library instance of Spi Flash Common Library Class # # Copyright
> +(c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +  INF_VERSION= 0x00010017
> +  BASE_NAME  = SmmSpiFlashCommonLib
> +  FILE_GUID  = 9632D96E-E849-4217-9217-DC500B8AAE47
> +  VERSION_STRING = 1.0
> +  MODULE_TYPE= DXE_SMM_DRIVER
> +  LIBRARY_CLASS  = SpiFlashCommonLib|DXE_SMM_DRIVER
> +  CONSTRUCTOR= SmmSpiFlashCommonLibConstructor
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +[LibraryClasses]
> +  PciLib
> +  IoLib
> +  MemoryAllocationLib
> +  BaseLib
> +  UefiLib
> +  SmmServicesTableLib
> +  BaseMemoryLib
> +  DebugLib
> +  MmPciLib
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Pcd]
> +  gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress  ## CONSUMES
> +  gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
> +
> +[Sources]
> +  SpiFlashCommonSmmLib.c
> +  SpiFlashCommon.c
> +
> +[Protocols]
> +  gPchSmmSpiProtocolGuid## CONSUMES
> +
> +[Depex.X64.DXE_SMM_DRIVER]
> +  gPchSmmSpiProtocolGuid
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/S
> piFlashCommon.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/S
> piFlashCommon.c
> new file mode 100644
> index 00..53711db632
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLi
> +++ b/SpiFlashCommon.c
> @@ -0,0 +1,196 @@
> +/** @file
> +  Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
> +  for module use.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +
> +PCH_SPI_PROTOCOL   *mSpiProtocol;
> +
> +//
> +// FlashAreaBaseAddress and Size for boottime and runtime usage.
> +//
> +UINTN mFlashAreaBaseAddress = 0;
> +UINTN mFlashAreaSize= 0;
> +
> +/**
> +  Enable block protection on the Serial Flash device.
> +
> +  @retval EFI_SUCCESS   Opertion is successful.
> +  @retval EFI_DEVICE_ERROR  If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiFlashLock (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Read NumBytes bytes of data from the address specified by
> +  PAddress into Buffer.
> +
> +  @param[in]  Address   The starting physical address of the read.
> +  @param[in,out]  NumBytes  On input, the number of bytes to read. On
> output, the number
> +of bytes actually read.
> +  @param[out] BufferThe destination data buffer for the read.
> +
> +  @retval EFI_SUCCESS   Opertion is successful.
> +  @retval EFI_DEVICE_ERROR  If there is any device errors.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiFlashRead (
> +  IN UINTNAddress,
> +  IN OUT UINT32   *NumBytes,
> + OUT UINT8*Buffer
> +  )
> +{
> +  ASSERT ((NumBytes != NULL) && (Buffer != NULL));
> +  if ((NumBytes == NULL) || (Buffer == NULL)) {
> +return EFI_INVALID_PARAMETER;
> +  }
> +
> +  //
> +  // This functio

Re: [edk2-devel] [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Gao, Liming ; Desimone,
> Nathaniel L ; Kinney, Michael D
> ; Sinha, Ankit 
> Subject: [edk2-platforms][PATCH V1 32/37]
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083
> 
> Header files for the WhiskeylakeURvp board instance.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Liming Gao 
> Cc: Nate DeSimone 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlat
> formHookLib.h  | 131 
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlat
> formLib.h  |  40 ++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Platfor
> mBoardConfig.h | 105 
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Platfor
> mInfo.h|  44 +++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whisk
> eylakeURvpId.h   |  12 ++
>  5 files changed, 332 insertions(+)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPl
> atformHookLib.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiP
> latformHookLib.h
> new file mode 100644
> index 00..bd849b9ee2
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Pei
> +++ PlatformHookLib.h
> @@ -0,0 +1,131 @@
> +/** @file
> +
> +  Copyright (c) 2019, Intel Corporation. All rights reserved.
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#ifndef _PEI_PLATFORM_HOOK_LIB_H_
> +#define _PEI_PLATFORM_HOOK_LIB_H_
> +
> +#include 
> +#include 
> +#include 
> +
> +
> +//EC Command to provide one byte of debug indication #define
> +BSSB_DEBUG_INDICATION 0xAE
> +/**
> +  Configure EC for specific devices
> +
> +  @param[in] PchLan   - The PchLan of PCH_SETUP variable.
> +  @param[in] BootMode - The current boot mode.
> +**/
> +VOID
> +EcInit (
> +  IN UINT8PchLan,
> +  IN EFI_BOOT_MODEBootMode
> +  );
> +
> +/**
> +  Checks if Premium PMIC present
> +
> +  @retval  TRUE  if present
> +  @retval  FALSE it discrete/other PMIC **/ BOOLEAN
> +IsPremiumPmicPresent (
> +  VOID
> +  );
> +
> +/**
> +  Pmic Programming to supprort LPAL Feature
> +
> +  @retval NONE
> +**/
> +VOID
> +PremiumPmicDisableSlpS0Voltage (
> +  VOID
> +  );
> +
> +/**
> +Pmic Programming to supprort LPAL Feature
> +  @retval NONE
> +**/
> +VOID
> +PremiumPmicEnableSlpS0Voltage(
> +  VOID
> +  );
> +
> +/**
> +  Do platform specific programming pre-memory. For example, EC init,
> +Chipset programming
> +
> +  @retval  Status
> +**/
> +EFI_STATUS
> +PlatformSpecificInitPreMem (
> +  VOID
> +  );
> +
> +/**
> +  Do platform specific programming post-memory.
> +
> +  @retval  Status
> +**/
> +EFI_STATUS
> +PlatformSpecificInit (
> +  VOID
> +  );
> +
> +/**
> +  Configure GPIO and SIO Before Memory is ready.
> +
> +  @retval  EFI_SUCCESS   Operation success.
> +**/
> +EFI_STATUS
> +BoardInitPreMem (
> +  VOID
> +  );
> +
> +/**
> +  Configure GPIO and SIO
> +
> +  @retval  EFI_SUCCESS   Operation success.
> +**/
> +EFI_STATUS
> +BoardInit (
> +  VOID
> +  );
> +
> +/**
> +Voltage Margining Routine
> +
> +@retval  EFI_SUCCESS   Operation success
> +**/
> +EFI_STATUS
> +VoltageMarginingRoutine(
> +  VOID
> +  );
> +
> +/**
> +  Detect recovery mode
> +
> +  @retval  EFI_SUCCESS   System in Recovery Mode
> +  @retval  EFI_UNSUPPORTED   System doesn't support Recovery Mode
> +  @retval  EFI_NOT_FOUND System is not in Recovery Mode
> +**/
> +EFI_STATUS
> +IsRecoveryMode (
> +  VOID
> +  );
> +
> +/**
> +  Early board Configuration before Memory is ready.
> +
> +  @retval  EFI_SUCCESS  Operation success.
> +**/
> +EFI_STATUS
> +BoardInitEarlyPreMem (
> +  VOID
> +  );
> +#endif
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPl
> atformLib.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiP
> latformLib.h
> new file mode 100644
> index 00..d65586dbb9
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Pei
> +++ PlatformLib.h
> @@ -0,0 +1,40 @@
> +/** @file
> +
> +  Copyright (c) 2019, Intel Corporation. All rights reserved.
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#ifndef _PEI_PLATFORM_LIB_H_
> +#define _PEI_PLATFORM_LIB_H_
> +
> +
> +
> +#define PEI_DEVICE_DISABLED 0
> +#define PEI_DEVICE_ENABLED  1
> +
> +typedef struct {
> +  UINT8   Register;
> +  UINT32  Value;
> +} PCH_GPIO_DEV;
> +
> +//
> +// GPIO Initialization Data Structure
> +//
> +typedef struct{
> +  PCH_GPIO_DEV Use_Sel;
> +  PCH_GPIO_DEV Use_Sel2;
> +  PCH_GPIO_DEV Use_Sel3;
> +  PCH_GPIO_DEV Io_Sel;
> +  PCH_GP

Re: [edk2-devel] [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Gao, Liming ; Desimone,
> Nathaniel L ; Kinney, Michael D
> ; Sinha, Ankit 
> Subject: [edk2-platforms][PATCH V1 36/37]
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083
> 
> Adds the DSC and build files necessary to build the
> WhiskeylakeURvp board instance.
> 
> Key files
> =
> * build_config.cfg - Board-specific build configuration file.
> * OpenBoardPkg.dsc - The WhiskeylakeURvp board description file.
> * OpenBoardPkgConfig.dsc - Used for feature-related PCD
>   customization.
> * OpenBoardPkgPcd.dsc - Used for other PCD customization.
> * OpenBoardPkg.fdf - The WhiskeylakeURvp board flash file.
> * FlashMapInclude.fdf - The WhiskeylakeURvp board flash map.
> * OpenBoardPkgBuildOption.dsc - Sets build options Based
>   on PCD values.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Liming Gao 
> Cc: Nate DeSimone 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> .dsc| 385 +++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> BuildOption.dsc | 154 +
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Config.dsc  | 128 
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Pcd.dsc | 245 +++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/Fla
> shMapInclude.fdf |  49 ++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> .fdf| 706 
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cf
> g|  33 +
>  7 files changed, 1700 insertions(+)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> new file mode 100644
> index 00..eea809140c
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> @@ -0,0 +1,385 @@
> +## @file
> +#  Platform description.
> +#
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> +  #
> +  # Set platform specific package/folder name, same as passed from PREBUILD
> script.
> +  # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as
> package build folder
> +  # DEFINE only takes effect at R9 DSC and FDF.
> +  #
> +  DEFINE  PLATFORM_PACKAGE  = MinPlatformPkg
> +  DEFINE  PLATFORM_SI_PACKAGE   = CoffeelakeSiliconPkg
> +  DEFINE  PLATFORM_SI_BIN_PACKAGE   = CoffeelakeSiliconBinPkg
> +  DEFINE  PLATFORM_FSP_BIN_PACKAGE  = CoffeeLakeFspBinPkg
> +  DEFINE  PLATFORM_BOARD_PACKAGE= WhiskeylakeOpenBoardPkg
> +  DEFINE  BOARD = WhiskeylakeURvp
> +  DEFINE  PROJECT   =
> $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
> +
> +  #
> +  # Platform On/Off features are defined here
> +  #
> +  !include OpenBoardPkgConfig.dsc
> +
> +###
> #
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +###
> #
> +[Defines]
> +  PLATFORM_NAME   = $(PLATFORM_PACKAGE)
> +  PLATFORM_GUID   =
> 84D0F5BD-0EF3-4CC0-9B09-F2D0F2AA5C5E
> +  PLATFORM_VERSION= 0.1
> +  DSC_SPECIFICATION   = 0x00010005
> +  OUTPUT_DIRECTORY= Build/$(PROJECT)
> +  SUPPORTED_ARCHITECTURES = IA32|X64
> +  BUILD_TARGETS   = DEBUG|RELEASE
> +  SKUID_IDENTIFIER= ALL
> +
> +
> +  FLASH_DEFINITION= $(PROJECT)/OpenBoardPkg.fdf
> +
> +  FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
> +  DEFINE   TOP_MEMORY_ADDRESS = 0x0
> +
> +  #
> +  # Default value for OpenBoardPkg.fdf use
> +  #
> +  DEFINE BIOS_SIZE_OPTION = SIZE_70
> +
> +###
> #
> +#
> +# SKU Identification section - list of all SKU IDs supported by this
> +#  Platform.
> +#
> +###
> #
> +[SkuIds]
> +  0|DEFAULT  # The entry: 0|DEFAULT is reserved and always
> required.
> +  0x60|WhiskeylakeURvp
> +
> +###
> #
> +#
> +# Library Class section - list of all Library Classes needed by this 
>

Re: [edk2-devel] [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D 
> Subject: [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add
> CoffeelakeSiliconPkg maintainers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Signed-off-by: Michael Kubacki 
> ---
>  Maintainers.txt | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/Maintainers.txt b/Maintainers.txt index 876ae5612a..bc8cbd6458
> 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -125,9 +125,14 @@ Silicon/Intel/Vlv2DeviceRefCodePkg
>  M: Zailiang Sun 
>  M: Yi Qian 
> 
> +Silicon/Intel/CoffeelakeSiliconPkg
> +M: Chasel Chiu 
> +M: Michael Kubacki 
> +M: Sai Chaganty 
> +
>  Silicon/Intel/KabylakeSiliconPkg
>  M: Chasel Chiu 
> -M: Michael A Kubacki 
> +M: Michael Kubacki 
>  M: Sai Chaganty 
> 
>  Silicon/Intel/LewisburgPkg
> --
> 2.16.2.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM private library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add
> SMM private library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds PCH SMM private library class instances.
> 
> * SmmPchPrivateLib
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/Sm
> mPchPrivateLib.inf | 32 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/Sm
> mPchPrivateLib.c   | 58 
>  2 files changed, 90 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/S
> mmPchPrivateLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/
> SmmPchPrivateLib.inf
> new file mode 100644
> index 00..5cbad21fa5
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPriva
> +++ teLib/SmmPchPrivateLib.inf
> @@ -0,0 +1,32 @@
> +## @file
> +#  PCH SMM private lib.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = SmmPchPrivateLib
> +FILE_GUID = FE6495FB-7AA9-4A24-BF3E-4698F7BCE0EE
> +VERSION_STRING = 1.0
> +MODULE_TYPE = DXE_SMM_DRIVER
> +LIBRARY_CLASS = SmmPchPrivateLib
> +
> +
> +[LibraryClasses]
> +BaseLib
> +IoLib
> +DebugLib
> +CpuPlatformLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +
> +[Sources]
> +SmmPchPrivateLib.c
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/S
> mmPchPrivateLib.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/
> SmmPchPrivateLib.c
> new file mode 100644
> index 00..85a3086874
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPriva
> +++ teLib/SmmPchPrivateLib.c
> @@ -0,0 +1,58 @@
> +/** @file
> +  PCH SMM private lib.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/**
> +  Set InSmm.Sts bit
> +**/
> +VOID
> +PchSetInSmmSts (
> +  VOID
> +  )
> +{
> +  UINT32  Data32;
> +
> +  ///
> +  /// Read memory location FED30880h OR with 0001h, place the
> +result in EAX,
> +  /// and write data to lower 32 bits of MSR 1FEh (sample code
> +available)
> +  ///
> +  Data32 = MmioRead32 (0xFED30880);
> +  AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE_ADDR, Data32 | BIT0);
> +  ///
> +  /// Read FED30880h back to ensure the setting went through.
> +  ///
> +  Data32 = MmioRead32 (0xFED30880);
> +}
> +
> +/**
> +  Clear InSmm.Sts bit
> +**/
> +VOID
> +PchClearInSmmSts (
> +  VOID
> +  )
> +{
> +  UINT32  Data32;
> +
> +  ///
> +  /// Read memory location FED30880h AND with FFFEh, place the
> +result in EAX,
> +  /// and write data to lower 32 bits of MSR 1FEh (sample code
> +available)
> +  ///
> +  Data32 = MmioRead32 (0xFED30880);
> +  AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE_ADDR, Data32 & (UINT32)
> +(~BIT0));
> +  ///
> +  /// Read FED30880h back to ensure the setting went through.
> +  ///
> +  Data32 = MmioRead32 (0xFED30880);
> +}
> --
> 2.16.2.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add
> Base library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds Pch/Library/Private Base library class instances.
> 
> * BaseGpioHelpersLibNull
> * BasePchSpiCommonlib
> * BaseSiScheduleResetLib
> * BaseSiScheduleResetLibFsp
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibN
> ull/BaseGpioHelpersLibNull.inf |   26 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLi
> b/BasePchSpiCommonLib.inf   |   28 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLi
> b/BaseSiScheduleResetLib.inf |   40 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLi
> b/BaseSiScheduleResetLibFsp.inf  |   40 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibN
> ull/BaseGpioHelpersLibNull.c   |  108 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLi
> b/SpiCommon.c   | 1081 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLi
> b/BaseSiScheduleResetLib.c   |   70 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLi
> b/BaseSiScheduleResetLibCommon.c |  125 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLi
> b/BaseSiScheduleResetLibFsp.c|   61 ++
>  9 files changed, 1579 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLib
> Null/BaseGpioHelpersLibNull.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLib
> Null/BaseGpioHelpersLibNull.inf
> new file mode 100644
> index 00..5502af824f
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLib
> Null/BaseGpioHelpersLibNull.inf
> @@ -0,0 +1,26 @@
> +## @file
> +# Component description file for the NULL GpioHelpersLib
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = BaseGpioHelpersLib
> +FILE_GUID = AB282608-2A50-4AE3-9242-64064ECF40D4
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = GpioHelpersLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +
> +[Sources]
> +BaseGpioHelpersLibNull.c
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommon
> Lib/BasePchSpiCommonLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommo
> nLib/BasePchSpiCommonLib.inf
> new file mode 100644
> index 00..ea23e628c8
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommo
> nLib/BasePchSpiCommonLib.inf
> @@ -0,0 +1,28 @@
> +## @file
> +#  Component description file for the PchSpiCommonLib
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION= 0x00010005
> +  BASE_NAME  = BasePchSpiCommonLib
> +  FILE_GUID  = A37CB67E-7D85-45B3-B07E-BF65BDB603E8
> +  MODULE_TYPE= BASE
> +  VERSION_STRING = 1.0
> +  LIBRARY_CLASS  = PchSpiCommonLib
> +
> +[Sources]
> +  SpiCommon.c
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[LibraryClasses]
> +  IoLib
> +  DebugLib
> +  PmcLib
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleRese
> tLib/BaseSiScheduleResetLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleRese
> tLib/BaseSiScheduleResetLib.inf
> new file mode 100644
> index 00..de7f6eeb73
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleRese
> tLib/BaseSiScheduleResetLib.inf
> @@ -0,0 +1,40 @@
> +## @file
> +# Component description file for Si Reset Schedule Library.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = BaseSiScheduleResetLib
> +FILE_GUID = E6F3D551-36C0-4737-80C7-47FC57593163
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = SiScheduleResetLib
> +#
> +# The follo

Re: [edk2-devel] [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add
> Base library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds PCH Base library class instances.
> 
> * BaseResetSystemLib
> * BaseSmbusLib
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRes
> etSystemLib.inf |  38 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.
> inf |  39 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRes
> etSystemLib.c   | 153 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.
> c   | 993 
>  4 files changed, 1223 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseR
> esetSystemLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseR
> esetSystemLib.inf
> new file mode 100644
> index 00..8d68f2dd83
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/
> +++ BaseResetSystemLib.inf
> @@ -0,0 +1,38 @@
> +## @file
> +# Component description file for Intel Ich7 Reset System Library.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = BaseResetSystemLib
> +FILE_GUID = D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +UEFI_SPECIFICATION_VERSION = 2.00
> +LIBRARY_CLASS = ResetSystemLib
> +CONSTRUCTOR = BaseResetSystemLibConstructor # # The following
> +information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 IPF
> +#
> +
> +[LibraryClasses]
> +IoLib
> +DebugLib
> +PmcLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +
> +[Sources]
> +BaseResetSystemLib.c
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLi
> b.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLi
> b.inf
> new file mode 100644
> index 00..f3388a2624
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSm
> +++ busLib.inf
> @@ -0,0 +1,39 @@
> +## @file
> +# Component description file for PCH Smbus Library.
> +#
> +# SMBUS Library that layers on top of the I/O Library to directly #
> +access a standard SMBUS host controller.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = BaseSmbusLib
> +FILE_GUID = 5C4D0430-F81B-42D3-BB88-4A6CD2796FF8
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = SmbusLib
> +CONSTRUCTOR = BaseSmbusLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 IPF EBC #
> +
> +[LibraryClasses]
> +BaseLib
> +DebugLib
> +IoLib
> +PciSegmentLib
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> +BaseSmbusLib.c
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseR
> esetSystemLib.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseR
> esetSystemLib.c
> new file mode 100644
> index 00..a603f5e794
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/
> +++ BaseResetSystemLib.c
> @@ -0,0 +1,153 @@
> +/** @file
> +  System reset library services.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED UINT16
> mBaseResetSystemABase;
> +
> +/**
> +  Calling this function causes a system-wide reset. This sets
> +  all circuitry within the system to its initial state. This type of
> +reset
> +  is asynchronous to system operation and operates without regard to
> +  cycle boundaries.
> +
> +  System reset should not return, if it returns, it means the system
> +does
> +  not support cold reset.
> +**/
> +VOID
> +EFIAPI
> +ResetCold (
> +  VOID
> +  )
> +{
> +  IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); }
> +
> +/**
> +  Calling this function causes a system-wide initialization. The
> +processors
> +  are set to their initial state, a

Re: [edk2-devel] [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE
> private library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds PCH DXE private library class instances.
> 
> * DxeGpioNameBufferLib
> * DxePchHdaLib
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLi
> b/DxeGpioNameBufferLib.inf |  32 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePch
> HdaLib.inf |  43 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLi
> b/GpioNameBufferDxe.c  |  20 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHd
> aEndpoints.c| 333 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHd
> aLib.c  | 886 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHd
> aNhltConfig.c   | 439 ++
>  6 files changed, 1753 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBuffe
> rLib/DxeGpioNameBufferLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBuffe
> rLib/DxeGpioNameBufferLib.inf
> new file mode 100644
> index 00..0dc8f9749d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBuffe
> rLib/DxeGpioNameBufferLib.inf
> @@ -0,0 +1,32 @@
> +## @file
> +# Component description file for the DxeGpioMemLib
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = DxeGpioNameBufferLib
> +FILE_GUID = 16EC6AA8-81D5-4847-B6CB-662CDAB863F2
> +VERSION_STRING = 1.0
> +MODULE_TYPE = DXE_DRIVER
> +LIBRARY_CLASS = GpioNameBufferLib
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> +#
> +
> +[LibraryClasses]
> +BaseLib
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> +GpioNameBufferDxe.c
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxeP
> chHdaLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxeP
> chHdaLib.inf
> new file mode 100644
> index 00..a8a3f60b53
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxeP
> chHdaLib.inf
> @@ -0,0 +1,43 @@
> +## @file
> +# Component information file for PCH HD Audio Library
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = DxePchHdaLib
> +FILE_GUID = DA915B7F-EE08-4C1D-B3D0-DE7C52AB155A
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = PchHdaLib
> +
> +
> +[LibraryClasses]
> +BaseLib
> +DebugLib
> +MemoryAllocationLib
> +BaseMemoryLib
> +PchInfoLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +
> +[Pcd]
> +  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId
> +  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> +  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> +  gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> +  gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> +
> +
> +[Sources]
> +PchHdaLib.c
> +PchHdaEndpoints.c
> +PchHdaNhltConfig.c
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBuffe
> rLib/GpioNameBufferDxe.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBuffe
> rLib/GpioNameBufferDxe.c
> new file mode 100644
> index 00..af53387faf
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBuffe
> rLib/GpioNameBufferDxe.c
> @@ -0,0 +1,20 @@
> +/** @file
> +  This file contains implementation of the GpioMemLib for DXE phase
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include 
> +
> +STATIC CHAR8 mGpioNameBuffer[GPIO_NAME_LENGTH_MAX];
> +
> +CHAR8*
> +GpioGetStaticNameBuffer (
> +  VOID
> +  )
> +{
> +  return mGpioNameBuffer;
> +}
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchH
> daEndpoints.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchH
> daEndpoints.c
> new file mode 100644
> i

Re: [edk2-devel] [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE
> library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds PCH DXE library class instances.
> 
> * DxePchPolicyLib
> * DxeResetSystemLib
> * DxeRuntimeResetSystemLib
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicy
> Lib.inf   |  41 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetS
> ystemLib.inf   |  49 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/D
> xeRuntimeResetSystemLib.inf |  52 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicy
> Lib.c | 218 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetS
> ystemLib.c | 310 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/D
> xeRuntimeResetSystemLib.c   | 323 
>  6 files changed, 993 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPoli
> cyLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPoli
> cyLib.inf
> new file mode 100644
> index 00..8845ab796c
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/Dxe
> +++ PchPolicyLib.inf
> @@ -0,0 +1,41 @@
> +## @file
> +# Component description file for the PeiPchPolicy library.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = DxePchPolicyLib
> +FILE_GUID = E2179D04-7026-48A5-9475-309CEA2F21A3
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = DxePchPolicyLib
> +
> +
> +[LibraryClasses]
> +BaseMemoryLib
> +UefiBootServicesTableLib
> +DebugLib
> +ConfigBlockLib
> +SiConfigBlockLib
> +PchInfoLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> +DxePchPolicyLib.c
> +
> +
> +[Guids]
> +gHdAudioDxeConfigGuid
> +gGpioDxeConfigGuid
> +
> +[Protocols]
> +gPchPolicyProtocolGuid ## PRODUCES
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeRes
> etSystemLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeRes
> etSystemLib.inf
> new file mode 100644
> index 00..0bb2d6e247
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/D
> +++ xeResetSystemLib.inf
> @@ -0,0 +1,49 @@
> +## @file
> +# Component description file for Intel Ich7 Reset System Library.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = DxeResetSystemLib
> +FILE_GUID = 239383BC-499E-4DC5-8CDC-F85AF27B1BC4
> +VERSION_STRING = 1.0
> +MODULE_TYPE = DXE_DRIVER
> +UEFI_SPECIFICATION_VERSION = 2.00
> +LIBRARY_CLASS = ResetSystemLib
> +CONSTRUCTOR = DxeResetSystemLibConstructor # # The following
> +information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 IPF
> +#
> +
> +[LibraryClasses]
> +IoLib
> +BaseLib
> +DebugLib
> +TimerLib
> +BaseMemoryLib
> +UefiBootServicesTableLib
> +PmcLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +
> +[Sources]
> +DxeResetSystemLib.c
> +
> +
> +[Protocols]
> +gPchResetCallbackProtocolGuid ## CONSUMES
> +
> +
> +[Guids]
> +gPchGlobalResetGuid
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib
> /DxeRuntimeResetSystemLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib
> /DxeRuntimeResetSystemLib.inf
> new file mode 100644
> index 00..a1777293ab
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSyst
> +++ emLib/DxeRuntimeResetSystemLib.inf
> @@ -0,0 +1,52 @@
> +## @file
> +# Component description file for Intel Ich7 Reset System Library.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = DxeRuntimeResetSystemLib
> +FILE_GUID = 1026813A-E46F-43D1-B709-FF1F996F2E72
> +VERSION_STRING = 1.0
> +MODULE_TYPE = DXE_RUNTIME_DRIVER
> +UEFI_SPECIFICATION_VERSION = 2.00
> +LIBRARY_CLASS = ResetSystemLib
> +CONSTRUCTO

Re: [edk2-devel] [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: Add library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: Add
> library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds ME library class instances.
> 
> * PeiMePolicyLib - PEI ME policy configuration services.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi
> b.inf   |  44 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi
> brary.h |  25 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi
> b.c | 251 
>  3 files changed, 320 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy
> Lib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy
> Lib.inf
> new file mode 100644
> index 00..85a227f950
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMe
> +++ PolicyLib.inf
> @@ -0,0 +1,44 @@
> +## @file
> +# Component description file for the PeiMePolicyLib libbrary.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved.  # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = PeiMePolicyLib
> +FILE_GUID = 2655FA94-4559-F393-B0B1-85A8E79C1532
> +VERSION_STRING = 1.0
> +MODULE_TYPE = PEIM
> +LIBRARY_CLASS = PeiMePolicyLib
> +
> +
> +[LibraryClasses]
> +DebugLib
> +IoLib
> +PeiServicesLib
> +BaseMemoryLib
> +MemoryAllocationLib
> +ConfigBlockLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> +PeiMePolicyLib.c
> +PeiMePolicyLibrary.h
> +
> +
> +[Ppis]
> +gSiPolicyPpiGuid   ## PRODUCES
> +gSiPreMemPolicyPpiGuid ## PRODUCES
> +
> +
> +[Guids]
> +gMePeiPreMemConfigGuid
> +gMePeiConfigGuid
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy
> Library.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy
> Library.h
> new file mode 100644
> index 00..3ac6a639e9
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMe
> +++ PolicyLibrary.h
> @@ -0,0 +1,25 @@
> +/** @file
> +  Header file for the PeiMePolicy library.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#ifndef _PEI_ME_POLICY_LIBRARY_H_
> +#define _PEI_ME_POLICY_LIBRARY_H_
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include  #include 
> +#include  #include  #include
> + #include 
> +#include  #include 
> +
> +#endif // _PEI_ME_POLICY_LIBRARY_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy
> Lib.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy
> Lib.c
> new file mode 100644
> index 00..6f3d70b841
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMe
> +++ PolicyLib.c
> @@ -0,0 +1,251 @@
> +/** @file
> +  This file is PeiMePolicy library.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#include "PeiMePolicyLibrary.h"
> +
> +/**
> +  Load default settings for ME config block in pre-mem phase.
> +
> +  @param[in] ConfigBlockPointer The pointer to the config 
> block
> +**/
> +VOID
> +LoadMePeiPreMemDefault (
> +  IN VOID   *ConfigBlockPointer
> +  );
> +
> +/**
> +  Load default settings for ME config block in PEI phase.
> +
> +  @param[in] ConfigBlockPointer The pointer to the config 
> block
> +**/
> +VOID
> +LoadMePeiDefault (
> +  IN VOID   *ConfigBlockPointer
> +  );
> +
> +STATIC COMPONENT_BLOCK_ENTRY  mMeCompontBlockPreMemBlocks [] = {
> +  {&gMePeiPreMemConfigGuid, sizeof (ME_PEI_PREMEM_CONFIG),
> +ME_PEI_PREMEM_CONFIG_REVISION,  LoadMePeiPreMemDefault} };
> +
> +STATIC COMPONENT_BLOCK_ENTRY  mMeCompontBlockBlocks [] = {
> +  {&gMePeiConfigGuid,   sizeof (ME_PEI_CONFIG),
> ME_PEI_CONFIG_REVISION, LoadMePeiDefault}
> +};
> +
> +/**
> +  Load default settings for ME config block in pre-mem phase.
> +
> +  @param[in] ConfigBlockPointer The pointer to the config 
> block
> +**/
> +VOID
> +LoadMePeiPreMemDefault (
> +  IN VOID   *ConfigBlockPointer
> +  )
> +{
> +  ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig;
> +  MePeiPreMemConfig = ConfigBlockPointer;
> +
> +  MePeiPreMemConfig->HeciTime

Re: [edk2-devel] [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package
> common library instances
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds package-level library class instances.
> 
> * BaseConfigBlockLib - Library functions for config block management.
> * BaseSiConfigBlockLib - Library functions for managing component
>   config blocks.
> * DxeAslUpdateLib - Services to update ACPI tables.
> * PeiDxeSmmMmPciLib - Services to manage PCI Express addresses.
> * PeiStallPpiLib - Installs an instance of EFI_PEI_STALL_PPI.
> * PeiSiPolicyLib - Installs an instance of the Silicon Policy PPI.
>   Prints the Silicon Policy PPI values when DEBUG prints are enabled.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlo
> ckLib.inf |  29 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfig
> BlockLib.inf |  33 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib
> .inf   |  40 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdat
> eLibNull.inf   |  30 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmm
> MmPciLib.inf   |  35 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiStallPpiLib.
> inf  |  31 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
> |  51 +++
>  
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
> |  35 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlo
> ckLib.c   | 146 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfig
> BlockLib.c   |  87 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib
> .c | 403 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdat
> eLibNull.c | 126 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmm
> MmPciLib.c |  32 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiStallPpiLib.
> c|  78 
>  Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
> | 214 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMe
> m.c | 122 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/SiPrintPolicy.c
> |  36 ++
>  17 files changed, 1528 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigB
> lockLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigB
> lockLib.inf
> new file mode 100644
> index 00..a7def2481d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigB
> lockLib.inf
> @@ -0,0 +1,29 @@
> +## @file
> +# Component INF file for the BaseConfigBlock library.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = BaseConfigBlockLib
> +FILE_GUID = 1EC07EA8-7808-4e06-9D79-309AE331D2D5
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = ConfigBlockLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> +BaseConfigBlockLib.c
> +
> +[LibraryClasses]
> +DebugLib
> +BaseMemoryLib
> +MemoryAllocationLib
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiCon
> figBlockLib.inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiCon
> figBlockLib.inf
> new file mode 100644
> index 00..b04dc3cfa4
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiCon
> figBlockLib.inf
> @@ -0,0 +1,33 @@
> +## @file
> +# Component description file for the BaseSiConfigBlockLib library.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = BaseSiConfigBlockLib
> +FILE_GUID = 6C068D0F-F48E-48CB-B369-433E507AF4A2
> +VERSION_STRING = 1.0
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = SiConfigBlockLib
> +
> +
> +[LibraryClasses]
> +DebugLib
> +IoLib
> +ConfigBlockLib
> +
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +CoffeelakeSiliconPkg/SiPkg.dec
> +
> +
> +[Sources]
> +BaseSiConfigBlockLib.c
> +
> +
>

Re: [edk2-devel] [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add
> Private include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds the following header files:
>  * Pch/Include/Private
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h
> |  16 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h
> | 273 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoints.h
> | 115 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h|
> 92 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h
> | 269 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h  |
> 58 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleResetHob.
> h |  25 ++
>  7 files changed, 848 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h
> new file mode 100644
> index 00..6c9d10e928
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h
> @@ -0,0 +1,16 @@
> +/** @file
> +CnlPchLp Dx HSIO Header File
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _CNL_PCH_LP_HSIO_DX_H_
> +#define _CNL_PCH_LP_HSIO_DX_H_
> +
> +#define CNL_PCH_LP_HSIO_VER_DX   0x7
> +
> +
> +extern UINT8  CnlPchLpChipsetInitTable_Dx[5072];
> +extern UINT8  CnlPchLpChipsetInitTable_eDBC_Dx[4612];
> +#endif //_CNL_PCH_LP_HSIO_DX_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h
> new file mode 100644
> index 00..5569da670d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h
> @@ -0,0 +1,273 @@
> +/** @file
> +  The GUID definition for PchConfigHob
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_CONFIG_HOB_H_
> +#define _PCH_CONFIG_HOB_H_
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +extern EFI_GUID gPchConfigHobGuid;
> +
> +#pragma pack (push,1)
> +
> +///
> +/// This structure contains the HOB which are related to PCH general config.
> +///
> +typedef struct {
> +  /**
> +This member describes whether or not the Compatibility Revision ID (CRID)
> feature
> +of PCH should be enabled. 0: Disable; 1: Enable
> +  **/
> +  UINT32Crid:  1;
> +  UINT32RsvdBits0   : 31;   ///< Reserved bits
> +  ///
> +  ///
> +} GENERAL_HOB;
> +
> +///
> +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP
> capable devices in the platform.
> +///
> +typedef struct {
> +  UINT8   RsvdBytes[3];
> +  UINT8   NumRsvdSmbusAddresses;///< The number of elements in
> the RsvdSmbusAddressTable.
> +  /**
> +Array of addresses reserved for non-ARP-capable SMBus devices.
> +  **/
> +  UINT8
> RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
> +} SMBUS_HOB;
> +
> +///
> +/// The INTERRUPT describes interrupt settings for PCH HOB.
> +///
> +typedef struct {
> +  UINT8NumOfDevIntConfig;
>///<
> Number of entries in DevIntConfig table
> +  UINT8GpioIrqRoute; 
>///<
> Interrupt routing for GPIO. Default is 14.
> +  UINT8Rsvd0[2]; 
>///<
> Reserved bytes, align to multiple 4.
> +  PCH_DEVICE_INTERRUPT_CONFIG
> DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG];   ///< Array which
> stores PCH devices interrupts settings
> +  UINT8PxRcConfig[PCH_MAX_PXRC_CONFIG];
> ///< PCI interrupt routing for 8259 PIC controller
> +} INTERRUPT_HOB;
> +
> +///
> +/// The CNVI_HOB block describes CNVi device.
> +///
> +typedef struct {
> +  UINT32 Mode  :  1; ///< 0: Disabled, 1: 
> Auto
> +  UINT32 RsvdBits0 : 31;
> +} CNVI_HOB;
> +
> +/**
> +  The SERIAL_IO block provides the configurations to set the Serial IO
> controllers
> +**/
> +typedef struct {
> +  /**
> +   0: Disabled;
> +  - Device is placed in D3
> +   

Re: [edk2-devel] [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add
> Private/Library include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds the following header files:
>  * Pch/Include/Private/Library
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNh
> lt.h   |  134 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHelpersLi
> b.h  |   97 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioNameBuf
> ferLib.h   |   25 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPrivateLi
> b.h  | 1061 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMasterCo
> mmonLib.h  |  288 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmiLib.h
> |  344 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHdaLib.h
> |   56 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchInitComm
> onLib.h|  100 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPciExpress
> HelpersLib.h |  371 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsfPrivate
> Lib.h|  578 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmbusCo
> mmonLib.h   |   98 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiComm
> onLib.h |  366 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPchDmiLib.
> h|   25 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPrivateLib
> .h   |  706 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiScheduleRes
> etLib.h  |   48 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPchPrivat
> eLib.h|   28 +
>  16 files changed, 4325 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHda
> Nhlt.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHda
> Nhlt.h
> new file mode 100644
> index 00..9d8e34eb0d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHda
> Nhlt.h
> @@ -0,0 +1,134 @@
> +/** @file
> +  Header file for DxePchHdaLib - NHLT structure definitions.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DXE_PCH_HDA_NHLT_H_
> +#define _DXE_PCH_HDA_NHLT_H_
> +
> +#include 
> +
> +//
> +// ACPI support protocol instance signature definition.
> +//
> +#define NHLT_ACPI_TABLE_SIGNATURE  SIGNATURE_32 ('N', 'H', 'L', 'T')
> +
> +// MSFT defined structures
> +#define SPEAKER_FRONT_LEFT  0x1
> +#define SPEAKER_FRONT_RIGHT 0x2
> +#define SPEAKER_FRONT_CENTER0x4
> +#define SPEAKER_BACK_LEFT   0x10
> +#define SPEAKER_BACK_RIGHT  0x20
> +
> +#define KSAUDIO_SPEAKER_MONO   (SPEAKER_FRONT_CENTER)
> +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT |
> SPEAKER_FRONT_RIGHT)
> +#define KSAUDIO_SPEAKER_QUAD   (SPEAKER_FRONT_LEFT |
> SPEAKER_FRONT_RIGHT | SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)
> +
> +#define WAVE_FORMAT_EXTENSIBLE0xFFFE /* Microsoft */
> +#define KSDATAFORMAT_SUBTYPE_PCM \
> +{0x0001, 0x, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 
> 0x9b,
> 0x71}}
> +
> +#pragma pack (push, 1)
> +
> +typedef struct {
> +  UINT16  wFormatTag;
> +  UINT16  nChannels;
> +  UINT32  nSamplesPerSec;
> +  UINT32  nAvgBytesPerSec;
> +  UINT16  nBlockAlign;
> +  UINT16  wBitsPerSample;
> +  UINT16  cbSize;
> +} WAVEFORMATEX;
> +
> +typedef struct {
> +  WAVEFORMATEX Format;
> +  union {
> +UINT16 wValidBitsPerSample;
> +UINT16 wSamplesPerBlock;
> +UINT16 wReserved;
> +  } Samples;
> +  UINT32   dwChannelMask;
> +  GUID SubFormat;
> +} WAVEFORMATEXTENSIBLE;
> +
> +//
> +// List of supported link type.
> +//
> +enum NHLT_LINK_TYPE
> +{
> +  HdaNhltLinkHd   = 0,
> +  HdaNhltLinkDsp  = 1,
> +  HdaNhltLinkDmic = 2,
> +  HdaNhltLinkSsp  = 3,
> +  HdaNhltLinkInvalid
> +};
> +
> +//
> +// List of supported device type.
> +//
> +enum NHLT_DEVICE_TYPE
> +{
> +  HdaNhltDeviceBt   = 0,
> +  HdaNhltDeviceDmic = 1,
> +  HdaNhltDeviceI2s  = 4,
> +  HdaNhltDeviceInvalid
> +};
> +
> +typedef struct {
> +  UINT32CapabilitiesSize;
> +  UINT8 Capabilities[1];
> +} SPECIFIC_CONFIG;
> +
> +

Re: [edk2-devel] [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add
> Library include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds the following header files:
>  * Pch/Include/library
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h 
> |
> 27 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h 
> |
> 24 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h
> |  58 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h
> | 265 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h 
> |
> 788 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h
> | 166 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h
> |
> 33 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.
> h | 371 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h  
> |
> 141 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h   
> |
> 36 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h  
> |
> 109 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h  
> |
> 407 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h
> | 105 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h   
> |
> 226 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h   
> |
> 45 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h
> |
> 114 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h 
> |
> 24 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h
> | 116 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h  
> |
> 240 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h
> | 111 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h
> |  23 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h
> | 121 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h  
> |
> 207 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h 
> |
> 76 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h   
> |
> 22 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h
> |  98 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h  
> |
> 23 +
>  27 files changed, 3976 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
> new file mode 100644
> index 00..ee77334ecb
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
> @@ -0,0 +1,27 @@
> +/** @file
> +  Header file for BiosLockLib.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _BIOSLOCK_LIB_H_
> +#define _BIOSLOCK_LIB_H_
> +
> +/**
> +  Enable BIOS lock. This will set the LE (Lock Enable) and EISS (Enable In
> SMM.STS).
> +  When this is set, attempts to write the WPD (Write Protect Disable) bit in
> PCH
> +  will cause a SMI which will allow the BIOS to verify that the write is 
> from a
> valid source.
> +
> +  Bios should always enable LockDownConfig.BiosLock policy to set Bios Lock
> bit in FRC.
> +  If capsule udpate is enabled, it's expected to not do BiosLock by setting
> BiosLock policy disable
> +  so it can udpate BIOS region.
> +  After flash update, it should utilize this lib to do BiosLock for security.
> +**/
> +VOID
> +BiosLockEnable (
> +  VOID
> +  );
> +
> +#endif // _BIOSLOCK_LIB_H_
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
> new file mode 100644
> index 00..f406e0d929
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
> @@ -0,0 +1,24 @@
> +/** @file
> +  Header file for CnviLib.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _CNVI_LIB_H_
> +

Re: [edk2-devel] [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add
> Private/Protocol include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds the following header files:
>  * Pch/Include/Private/Protocol
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.
> h | 31 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h
> | 37 
>  2 files changed, 68 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsAr
> ea.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsAr
> ea.h
> new file mode 100644
> index 00..75003c82ad
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc
> +++ hNvsArea.h
> @@ -0,0 +1,31 @@
> +/** @file
> +  This file defines the PCH NVS Area Protocol.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#ifndef _PCH_NVS_AREA_H_
> +#define _PCH_NVS_AREA_H_
> +
> +//
> +// PCH NVS Area definition
> +//
> +#include 
> +
> +//
> +// Extern the GUID for protocol users.
> +//
> +extern EFI_GUID gPchNvsAreaProtocolGuid;
> +
> +/**
> +  This protocol is used to sync PCH information from POST to runtime ASL.
> +  This protocol exposes the pointer of PCH NVS Area only. Please refer
> +to
> +  ASL definition for PCH NVS AREA.
> +**/
> +typedef struct {
> +  PCH_NVS_AREA  *Area;
> +} PCH_NVS_AREA_PROTOCOL;
> +
> +#endif // _PCH_NVS_AREA_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap
> .h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap
> .h
> new file mode 100644
> index 00..2cd6b85d29
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc
> +++ ieIoTrap.h
> @@ -0,0 +1,37 @@
> +/** @file
> +  This file defines the PCH PCIE IoTrap Protocol.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#ifndef _PCH_PCIE_IOTRAP_H_
> +#define _PCH_PCIE_IOTRAP_H_
> +
> +//
> +// Extern the GUID for protocol users.
> +//
> +extern EFI_GUID   gPchPcieIoTrapProtocolGuid;
> +
> +//
> +// Forward reference for ANSI C compatibility // typedef struct
> +_PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL;
> +
> +///
> +/// Pcie Trap valid types
> +///
> +typedef enum {
> +  PciePmTrap,
> +  PcieTrapTypeMaximum
> +} PCH_PCIE_TRAP_TYPE;
> +
> +/**
> + This protocol is used to provide the IoTrap address to trigger PCH
> +PCIE call back events **/ struct _PCH_PCIE_IOTRAP_PROTOCOL {
> +  UINT16  PcieTrapAddress;
> +};
> +
> +#endif
> --
> 2.16.2.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add
> ConfigBlock headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds header files to Pch/Include/ConfigBlock.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
> |  69 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h
> |  56 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h
> |  43 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h
> |  40 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionC
> onfig.h |  54 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevConfig.h
> |  39 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
> | 178 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
> |  57 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h
> |  58 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h
> |  66 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.
> h   |  58 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h
> |  68 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h
> |  57 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h
> |  35 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.
> h|  70 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h
> |  34 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h
> |  49 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfi
> g.h  |  71 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHubCon
> fig.h |  36 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h
> | 429 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h
> | 311 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h
> | 230 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h
> |  63 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h
> |  96 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h
> |  43 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h
> |  52 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h
> | 139 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.
> h|  33 ++
>  28 files changed, 2534 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
> new file mode 100644
> index 00..35fa125ba3
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
> @@ -0,0 +1,69 @@
> +/** @file
> +  CNVI policy
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _CNVI_CONFIG_H_
> +#define _CNVI_CONFIG_H_
> +
> +#define CNVI_CONFIG_REVISION 2
> +extern EFI_GUID gCnviConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> +  CNVi Mode options
> +**/
> +typedef enum {
> +  CnviModeDisabled = 0,
> +  CnviModeAuto
> +} CNVI_MODE;
> +
> +/**
> +  CNVi MfUart1 connection options
> +**/
> +typedef enum {
> +  CnviMfUart1Ish = 0,
> +  CnviMfUart1SerialIo,
> +  CnviBtUart1ExtPads,
> +  CnviBtUart1NotConnected
> +} CNVI_MFUART1_TYPE;
> +
> +
> +/**
> +  Revision 1:
> +  - Initial version.
> +  Revision 2:
> +  - Remove BtInterface and BtUartType.
> +
> +**/
> +typedef struct {
> +  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
> +  /**
> +This option allows for automatic detection of Connectivity Solution.
> +Auto Detection assumes that CNVi will be enabled when available;
> +Disable allows for disabling CNVi.
> +CnviModeDisabled = Disabled,
> +CnviModeAuto = Auto Detection
> +  **/
> +  UINT32 Mode  :  1;
> +  /**
> +(Test) This option configures Uart type which connects to MfUart1
> +For production configuration ISH is the default, for tests SerialIO 
> Uart0 or
> external pads can be

Re: [edk2-devel] [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI
> and Protocol include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds the following header files:
>  * Pch/Include/Ppi
>  * Pch/Include/Protocol
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h
> |  42 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h
> |  27 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h
> |  28 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h
> | 186 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch
> .h | 136 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h
> |  68 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.
> h | 146 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.
> h | 132 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h
> |  42 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h
> |  42 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h
> | 134 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapContr
> ol.h|  67 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTim
> erControl.h |  67 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.
> h  | 152 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h
> |  15 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h
> | 295 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h
> | 113 
>  17 files changed, 1692 insertions(+)
> 
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h
> new file mode 100644
> index 00..840a2355f1
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h
> @@ -0,0 +1,42 @@
> +/** @file
> +  PCH Reset PPI
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_RESET_PPI_H_
> +#define _PCH_RESET_PPI_H_
> +
> +//
> +// Member functions
> +//
> +/**
> +  Execute call back function for Pch Reset.
> +
> +  @param[in] ResetTypeReset Types which includes GlobalReset.
> +  @param[in] ResetTypeGuidPointer to an EFI_GUID, which is the Reset
> Type Guid.
> +
> +  @retval EFI_SUCCESS The callback function has been done
> successfully
> +  @retval EFI_NOT_FOUND   Failed to find Pch Reset Callback ppi. Or,
> none of
> +  callback ppi is installed.
> +  @retval Others  Do not do any reset from PCH
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PCH_RESET_CALLBACK) (
> +  IN  EFI_RESET_TYPEResetType,
> +  IN  EFI_GUID  *ResetTypeGuid
> +  );
> +
> +/**
> +  This ppi is used to execute PCH Reset from the host controller.
> +  If drivers need to run their callback function right before issuing the PCH
> Reset,
> +  they can install PCH Reset Callback PPI before PCH Reset PEI driver to
> achieve that.
> +**/
> +typedef struct {
> +  PCH_RESET_CALLBACK  ResetCallback;
> +} PCH_RESET_CALLBACK_PPI;
> +
> +#endif
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h
> new file mode 100644
> index 00..d3ff152742
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h
> @@ -0,0 +1,27 @@
> +/** @file
> +  This file defines the PCH SPI PPI which implements the
> +  Intel(R) PCH SPI Host Controller Compatibility Interface.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_SPI_PPI_H_
> +#define _PCH_SPI_PPI_H_
> +
> +#include 
> +
> +//
> +// Extern the GUID for PPI users.
> +//
> +extern EFI_GUID   gPchSpiPpiGuid;
> +
> +/**
> +  Reuse the PCH_SPI_PROTOCOL definitions
> +  This is possible becaues the PPI implementation does not rely on a
> PeiService pointer,
> +  as it uses EDKII Glue Lib to do IO accesses
> +**/
> +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI;
> +
> +#endif
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h

Re: [edk2-devel] [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add
> include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds Pch/Include headers.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h   |
> 135 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h   | 
> 326
> +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h |
> 381 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h|
> 340 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h |
> 241 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h|
> 200 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h|  
> 54
> +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h   |  
> 38
> ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h   |
> 80 
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h|  
> 53
> +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h
> |  47 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h  |
> 47 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h
> |  59 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResources.h
> |  53 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h |
> 23 ++
>  15 files changed, 2077 insertions(+)
> 
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h
> new file mode 100644
> index 00..91222fd54d
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h
> @@ -0,0 +1,135 @@
> +/** @file
> +  Header file for DxePchHdaNhltLib - NHLT structure definitions.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DXE_HDA_NHLT_H_
> +#define _DXE_HDA_NHLT_H_
> +
> +#include 
> +
> +//
> +// ACPI support protocol instance signature definition.
> +//
> +#define NHLT_ACPI_TABLE_SIGNATURE  SIGNATURE_32 ('N', 'H', 'L', 'T')
> +
> +// MSFT defined structures
> +#define SPEAKER_FRONT_LEFT  0x1
> +#define SPEAKER_FRONT_RIGHT 0x2
> +#define SPEAKER_FRONT_CENTER0x4
> +#define SPEAKER_BACK_LEFT   0x10
> +#define SPEAKER_BACK_RIGHT  0x20
> +
> +#define KSAUDIO_SPEAKER_MONO   (SPEAKER_FRONT_CENTER)
> +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT |
> SPEAKER_FRONT_RIGHT)
> +#define KSAUDIO_SPEAKER_QUAD   (SPEAKER_FRONT_LEFT |
> SPEAKER_FRONT_RIGHT | SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)
> +
> +#define WAVE_FORMAT_EXTENSIBLE0xFFFE
> +#define KSDATAFORMAT_SUBTYPE_PCM \
> +{0x0001, 0x, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 
> 0x9b,
> 0x71}}
> +
> +#pragma pack (push, 1)
> +
> +typedef struct {
> +  UINT16  wFormatTag;
> +  UINT16  nChannels;
> +  UINT32  nSamplesPerSec;
> +  UINT32  nAvgBytesPerSec;
> +  UINT16  nBlockAlign;
> +  UINT16  wBitsPerSample;
> +  UINT16  cbSize;
> +} WAVEFORMATEX;
> +
> +typedef struct {
> +  WAVEFORMATEX Format;
> +  union {
> +UINT16 wValidBitsPerSample;
> +UINT16 wSamplesPerBlock;
> +UINT16 wReserved;
> +  } Samples;
> +  UINT32   dwChannelMask;
> +  GUID SubFormat;
> +} WAVEFORMATEXTENSIBLE;
> +
> +//
> +// List of supported link type.
> +//
> +enum NHLT_LINK_TYPE
> +{
> +  HdaNhltLinkHd   = 0,
> +  HdaNhltLinkDsp  = 1,
> +  HdaNhltLinkDmic = 2,
> +  HdaNhltLinkSsp  = 3,
> +  HdaNhltLinkInvalid
> +};
> +
> +//
> +// List of supported device type.
> +//
> +enum NHLT_DEVICE_TYPE
> +{
> +  HdaNhltDeviceBt   = 0,
> +  HdaNhltDeviceDmic = 1,
> +  HdaNhltDeviceI2s  = 4,
> +  HdaNhltDeviceInvalid
> +};
> +
> +typedef struct {
> +  UINT32CapabilitiesSize;
> +  UINT8 Capabilities[1];
> +} SPECIFIC_CONFIG;
> +
> +typedef struct {
> +  WAVEFORMATEXTENSIBLE Format;
> +  SPECIFIC_CONFIG  FormatConfiguration;
> +} FORMAT_CONFIG;
> +
> +typedef struct {
> +  UINT8   FormatsCount;
> +  FORMAT_CONFIG   FormatsConfiguration[1];
> +} FORMATS_CONFIG;
> +
> +typedef struct {
> +  UINT8   DeviceId[16];
> +  UINT8   DeviceInstanceId;
> +  UINT8   DevicePortId;
> +} DEVICE_INFO;
> +
> +typedef struct {
> +  UINT8   DeviceInfoCount;
> +  DEVICE_INFO

Re: [edk2-devel] [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add Include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:15 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add
> Include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds header files common to ME modules.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h |
> 124 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyLib.h  |
> 59 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyLib.h  |
> 87 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h   | 172
> 
>  Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h |  17
> ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h|  19
> +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h   |
> 41 +
>  7 files changed, 519 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h
> new file mode 100644
> index 00..102fb43bd1
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiCon
> +++ fig.h
> @@ -0,0 +1,124 @@
> +/** @file
> +  ME config block for PEI phase
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent **/
> +
> +#ifndef _ME_PEI_CONFIG_H_
> +#define _ME_PEI_CONFIG_H_
> +
> +#include 
> +
> +#define ME_PEI_PREMEM_CONFIG_REVISION 2 extern EFI_GUID
> +gMePeiPreMemConfigGuid;
> +
> +#ifndef PLATFORM_POR
> +#define PLATFORM_POR  0
> +#endif
> +#ifndef FORCE_ENABLE
> +#define FORCE_ENABLE  1
> +#endif
> +#ifndef FORCE_DISABLE
> +#define FORCE_DISABLE 2
> +#endif
> +
> +#pragma pack (push,1)
> +
> +/**
> +  ME Pei Pre-Memory Configuration Structure.
> +
> +  Revision 1:
> +  - Initial version.
> +  Revision 2:
> +  - Change DidInitStat bit width.
> +**/
> +typedef struct {
> +  CONFIG_BLOCK_HEADER   Header; ///< Config Block Header
> +  UINT32 HeciTimeouts : 1;  ///< 0: Disable; 1: 
> Enable
> - HECI Send/Receive Timeouts.
> +  /**
> +(Test)
> +0: Disabled
> +   1: ME DID init stat 0 - Success
> +   2: ME DID init stat 1 - No Memory in Channels
> +   3: ME DID init stat 2 - Memory Init Error
> +  **/
> +  UINT32 DidInitStat  : 2;
> +  /**
> +(Test)
> +0: Set to 0 to enable polling for CPU replacement
> +   1: Set to 1 will disable polling for CPU replacement
> +  **/
> +  UINT32 DisableCpuReplacedPolling: 1;
> +  UINT32 SendDidMsg   : 1;  ///< (Test) 0: 
> Disable;
> 1: Enable - Enable/Disable to send DID message.
> +  /**
> +(Test)
> +0: Set to 0 to enable retry mechanism for HECI APIs
> +   1: Set to 1 will disable retry mechanism for HECI APIs
> +  **/
> +  UINT32 DisableHeciRetry : 1;
> +  /**
> +(Test)
> +0: ME BIOS will check each messages before sending
> +   1: ME BIOS always sends messages without checking
> +  **/
> +  UINT32 DisableMessageCheck  : 1;
> +  /**
> +(Test)
> +The SkipMbpHob policy determines whether ME BIOS Payload data will be
> requested during boot
> +in a MBP message. If set to 1, BIOS will send the MBP message with
> SkipMbp flag
> +set causing CSME to respond with MKHI header only and no MBP data
> +0: ME BIOS will keep MBP and create HOB for MBP data
> +   1: ME BIOS will skip MBP data
> +  **/
> +  UINT32 SkipMbpHob   : 1;
> +  UINT32 HeciCommunication2   : 1;  ///< (Test) 0:
> Disable; 1: Enable - Enable/Disable HECI2.
> +  UINT32 KtDeviceEnable   : 1;  ///< (Test) 0: 
> Disable;
> 1: Enable - Enable/Disable Kt Device.
> +  UINT32 RsvdBits : 22; ///< Reserved for future use 
> &
> Config block alignment
> +  UINT32 Heci1BarAddress;   ///< HECI1 BAR address.
> +  UINT32 Heci2BarAddress;   ///< HECI2 BAR address.
> +  UINT32 Heci3BarAddress;   ///< HECI3 BAR address.
> +} ME_PEI_PREMEM_CONFIG;
> +#pragma pack (pop)
> +
> +
> +#define ME_PEI_CONFIG_REVISION 2
> +extern EFI_GUID gMePeiConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> +  ME Pei Post-Memory Configuration Structure.
> +
> +  Revision 1:
> +  - Initial version.
> +  Revision 2:
> +  - Add MctpBroadcastCycle test setting.
> +**/
> +typedef struct {
> +  CONFIG_BLOCK_HEADER   Header; 

Re: [edk2-devel] [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:15 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add
> Include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds header files common to CPU modules.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
> |  45 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPre
> MemConfig.h | 106 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclocking
> Config.h| 141 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfi
> g.h |  54 
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmt
> BasicConfig.h  | 179 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmt
> CustomConfig.h |  78 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmt
> TestConfig.h   | 149 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h
> |  66 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h
> |  16 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> | 113 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h
> |  88 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h
> |  23 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h
> | 100 
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> | 261 
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h
> |  90 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h
> | 118 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h
> |  84 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h
> | 123 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPolicyProtocol.h
> |  50 
>  19 files changed, 1884 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
> new file mode 100644
> index 00..47a98131d0
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
> @@ -0,0 +1,45 @@
> +/** @file
> +  CPU Config Block.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _CPU_CONFIG_H_
> +#define _CPU_CONFIG_H_
> +
> +#define CPU_CONFIG_REVISION 3
> +
> +extern EFI_GUID gCpuConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> +  CPU Configuration Structure.
> +
> +  Revision 1:
> +  - Initial version.
> +  Revision 2:
> +  - Deprecate and move SkipMpInit to CpuConfigLibPreMemConfig.
> +  Revision 3:
> +  - Move DebugInterfaceEnable from CPU_TEST_CONFIG.
> +**/
> +typedef struct {
> +  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
> +  /**
> +Enable or Disable Advanced Encryption Standard (AES) feature.
> +For some countries, this should be disabled for legal reasons.
> +-0: Disable
> +- 1: Enable
> +  **/
> +  UINT32 AesEnable: 1;
> +  UINT32 SkipMpInit   : 1;///< @deprecated since 
> revision 2.
> For Fsp only, Silicon Initialization will skip MP Initialization (including 
> BSP) if
> enabled. For non-FSP, this should always be 0.
> +  UINT32 DebugInterfaceEnable : 1;///< Enable or Disable
> processor debug features; 0: Disable; 1: Enable.
> +  UINT32 RsvdBits : 28;   ///< Reserved for future 
> use
> +  EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to
> microcode patch that is suitable for this processor.
> +} CPU_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _CPU_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibP
> reMemConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibP
> reMemConfig.h
> new file mode 100644
> index 00..ce965a7510
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibP
> reMemConfig.h
> @@ -0,0 +1,106 @@
> +/** @file
> +  CPU Security PreMemory Config Block.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
> +#define _CPU_CON

Re: [edk2-devel] [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 

> -Original Message-
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:15 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Kinney, Michael D ; Sinha, Ankit
> 
> Subject: [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package
> and Include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Create the CoffeelakeSiliconPkg to provide an initial package for
> silicon initialization code for Coffee Lake (CFL) and Whiskey Lake
> (WHL) generation products.
> 
> * Major areas of functionality are categorized into CPU, Management
>   Engine (ME), Platform Controller Hub (PCH), and System Agent
>   subdirectories.
> * Common libraries and headers are kept at the root of the package.
> 
> Cc: Sai Chaganty 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ankit Sinha 
> Signed-off-by: Michael Kubacki 
> ---
>  Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec  | 
> 714
> 
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h  |  
> 53
> ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h |
> 89 +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h|
> 291 
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h |
> 157 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h   |
> 64 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h |  
> 28
> +
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h |
> 123 
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h |
> 58 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h  | 
> 110
> +++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h  |  
> 22
> +
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h   |  
> 34
> +
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h | 
> 319
> +
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h |  
> 29 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h  |
> 26 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h   |
> 71 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h|
> 60 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h |  
> 55
> ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h  |  
> 19 +
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h   |  
> 65
> ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h
> |  23 +
>  21 files changed, 2410 insertions(+)
> 
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
> b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
> new file mode 100644
> index 00..fa8c11e93d
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
> @@ -0,0 +1,714 @@
> +## @file
> +# Component description file for the Silicon Reference Code.
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. 
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +DEC_SPECIFICATION = 0x00010017
> +PACKAGE_NAME  = SiPkg
> +PACKAGE_VERSION   = 0.1
> +PACKAGE_GUID  = F245E276-44A0-46b3-AEB5-9898BBCF008D
> +
> +[Includes]
> +  Include
> +  SampleCode/Include
> +  SampleCode/MdeModulePkg/Include
> +  SampleCode/IntelFrameworkPkg/Include
> +  #
> +  # SystemAgent
> +  #
> +  SystemAgent/Include
> +  SystemAgent/MemoryInit/Include
> +  SystemAgent/AcpiTables
> +  #
> +  # Cpu
> +  #
> +  Cpu/Include
> +  #
> +  # Me
> +  #
> +  Me/Include
> +  #
> +  # Pch
> +  #
> +  Pch/Include
> +
> +[Guids.common.Private]
> +  #
> +  # PCH
> +  #
> +  gPchDeviceTableHobGuid   = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66,
> 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}
> +  gPchConfigHobGuid= { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd9,
> 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}
> +  gGpioLibUnlockHobGuid= { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6,
> 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
> +  gSiScheduleResetHobGuid  = { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC1,
> 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }}
> +
> +[Guids]
> +##
> +## MdeModulePkg
> +##
> +gEfiMemoryTypeInformationGuid  =  {0x4c19049f, 0x4137, 0x4dd3, {0x9c,
> 0x10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}}
> +gEfiCapsuleVendorGuid  =  {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36,
> 0xec, 0xbd, 0x3c, 0x8b, 0xe2}}
> +gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0x0,
> 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
> +
> +##
> +## IntelFrameworkPkg
> +##
> +gEfiSmmPeiSmramMemoryReserveGuid =  {0x6dadf1d1, 0xd4cc, 0x4910,
> {0xbb, 0x6e, 0x82, 0

Re: [edk2-devel] Patch List for 201908 stable tag

[Michael D Kinney]

Liming,

I would like to include the following bug fixes to EmulatorPkg in the stable 
tag:

https://edk2.groups.io/g/devel/message/45953  [edk2-devel] [Patch V5 00/11] 
EmulatorPkg: Fix VS20xx IA32 boot and simplify build config

The first set of patches were sent for review on 8/1.  Most of the EmulatorPkg 
combinations cannot build or boot without these fixes.  I am waiting for final 
reviews from the maintainers Ray and Jordan and approval from stewards before 
pushing this series.

Thanks,

Mike

From: Gao, Liming
Sent: Friday, August 16, 2019 1:01 AM
To: Gao, Liming ; Laszlo Ersek (ler...@redhat.com) 
; leif.lindh...@linaro.org; Kinney, Michael D 
; af...@apple.com; Cetola, Stephano 

Cc: devel@edk2.groups.io
Subject: RE: Patch List for 201908 stable tag


From: Gao, Liming [mailto:liming@intel.com]
Sent: Friday, August 16, 2019 3:59 PM
To: Laszlo Ersek (ler...@redhat.com) 
mailto:ler...@redhat.com>>; 
leif.lindh...@linaro.org; Kinney, Michael D 
mailto:michael.d.kin...@intel.com>>; 
af...@apple.com; Cetola, Stephano 
mailto:stephano.cet...@intel.com>>
Cc: edk2-de...@lists.01.org
Subject: Patch List for 201908 stable tag

Hi Stewards and all:
  I collect current patch lists in devel mail list. Those patch contributors 
request to add them for 201908 stable tag. Because the time is very close to 
Soft Feature Freeze, I want to collect your feedback for below patches.

Feature List (those all have pass code review):
https://edk2.groups.io/g/devel/message/45734 [PATCH v6 0/5] Build cache 
enhancement
https://edk2.groups.io/g/devel/message/45707 [PATCH] UefiCpuPkg: Adding a new 
TSC library by using CPUID(0x15) TSC leaf
https://edk2.groups.io/g/devel/message/45503 [PATCH v2 1/1] MdePkg: Add 
STATIC_ASSERT macro

Bug List:
https://edk2.groups.io/g/devel/message/45794  [PATCH 1/1] CryptoPkg: Fix coding 
style
https://edk2.groups.io/g/devel/message/45791 [PATCH v2 1/1] 
ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left
https://edk2.groups.io/g/devel/message/45793 [Patch 1/1] BaseTools: Fixed issue 
of incorrect Module Unique Name
https://edk2.groups.io/g/devel/message/45773 [Patch v4 0/6] Add "test then 
write" mechanism
https://edk2.groups.io/g/devel/message/45317 [Patch] MdeModulePkg DxeCore: Fix 
for missing MAT update

Thanks
Liming

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[edk2-devel] [Patch V5 11/11] BaseTools/tools_def.template: Add -gdwarf to XCODE5 X64

[Michael D Kinney]

From: Andrew Fish 

Add -gdwarf to XCODE5 X64 builds to generate symbols for
source level debug using lldb.

Cc: Jordan Justen 
Cc: Ray Ni 
Cc: Michael D Kinney 
Signed-off-by: Andrew Fish 
Reviewed-by: Michael D Kinney 
Tested-by: Andrew Fish 
---
 BaseTools/Conf/tools_def.template | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Conf/tools_def.template 
b/BaseTools/Conf/tools_def.template
index 26a2cf604f..8f0e6cb6c2 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -2593,8 +2593,8 @@ RELEASE_XCODE5_X64_ASM_FLAGS  = -arch x86_64
 *_XCODE5_*_PP_FLAGS = -E -x assembler-with-cpp -include 
$(DEST_DIR_DEBUG)/AutoGen.h
 *_XCODE5_*_VFRPP_FLAGS  = -x c -E -P -DVFRCOMPILE -include 
$(DEST_DIR_DEBUG)/$(MODULE_NAME)StrDefs.h
 
-  DEBUG_XCODE5_X64_CC_FLAGS   = -target x86_64-pc-win32-macho -c -g -Os   
-Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions 
-fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float 
-mms-bitfields -Wno-unused-parameter -Wno-missing-braces 
-Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare 
-Wno-varargs 
-ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D 
NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
-  NOOPT_XCODE5_X64_CC_FLAGS   = -target x86_64-pc-win32-macho -c -g -O0   
-Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions 
-fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float 
-mms-bitfields -Wno-unused-parameter -Wno-missing-braces 
-Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare 
-Wno-varargs 
-ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D 
NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
+  DEBUG_XCODE5_X64_CC_FLAGS   = -target x86_64-pc-win32-macho -c -g -gdwarf 
-Os   -Wall -Werror -Wextra -include AutoGen.h -funsigned-char 
-fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar 
-mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces 
-Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare 
-Wno-varargs 
-ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D 
NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
+  NOOPT_XCODE5_X64_CC_FLAGS   = -target x86_64-pc-win32-macho -c -g -gdwarf 
-O0   -Wall -Werror -Wextra -include AutoGen.h -funsigned-char 
-fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar 
-mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces 
-Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare 
-Wno-varargs 
-ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D 
NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
 RELEASE_XCODE5_X64_CC_FLAGS   = -target x86_64-pc-win32-macho -c-Os   
-Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions 
-fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float 
-mms-bitfields -Wno-unused-parameter -Wno-missing-braces 
-Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare 
-Wno-varargs -Wno-unused-const-variable 
-ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D 
NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
 
 

-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 05/11] EmulatorPkg/Unix/Host: Disable inline/optimizations

[Michael D Kinney]

From: Andrew Fish 

* Disable XCODE5 compiler optimizations fort Unix/Host.
* Disable inline of SecGdbScriptBreak() to improve
  compatibility with XCODE5
* For X64 XCODE5 builds place output Host application
  in $(BIN_DIR) to match all other EmulatorPkg Host
  application builds.

Cc: Jordan Justen 
Cc: Andrew Fish 
Cc: Ray Ni 
Signed-off-by: Michael D Kinney 
Reviewed-by: Michael D Kinney 
Tested-by: Andrew Fish 
---
 EmulatorPkg/Unix/Host/Host.c   | 3 +++
 EmulatorPkg/Unix/Host/Host.inf | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/EmulatorPkg/Unix/Host/Host.c b/EmulatorPkg/Unix/Host/Host.c
index febfb1f44c..b431a4c2ed 100644
--- a/EmulatorPkg/Unix/Host/Host.c
+++ b/EmulatorPkg/Unix/Host/Host.c
@@ -1113,6 +1113,9 @@ DlLoadImage (
 }
 
 
+#ifdef __APPLE__
+__attribute__((noinline))
+#endif
 VOID
 SecGdbScriptBreak (
   char*FileName,
diff --git a/EmulatorPkg/Unix/Host/Host.inf b/EmulatorPkg/Unix/Host/Host.inf
index ca4294249b..c479d2b7d0 100644
--- a/EmulatorPkg/Unix/Host/Host.inf
+++ b/EmulatorPkg/Unix/Host/Host.inf
@@ -137,6 +137,6 @@ [BuildOptions]
XCODE:*_*_IA32_ASM_FLAGS == -arch i386 -g
 
XCODE:*_*_X64_DLINK_PATH == gcc
-   XCODE:*_*_X64_DLINK_FLAGS == -L/usr/X11R6/lib -lXext -lX11 -framework 
Carbon -Wl,-no_pie
+   XCODE:*_*_X64_DLINK_FLAGS == -o $(BIN_DIR)/Host -L/usr/X11R6/lib -lXext 
-lX11 -framework Carbon -Wl,-no_pie
XCODE:*_*_X64_ASM_FLAGS == -g
-   XCODE:*_*_X64_CC_FLAGS = -target x86_64-apple-darwin 
-I$(WORKSPACE)/EmulatorPkg/Unix/Host/X11IncludeHack 
"-DEFIAPI=__attribute__((ms_abi))"
+   XCODE:*_*_X64_CC_FLAGS = -O0 -target x86_64-apple-darwin 
-I$(WORKSPACE)/EmulatorPkg/Unix/Host/X11IncludeHack 
"-DEFIAPI=__attribute__((ms_abi))"
-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 09/11] EmulatorPkg: Disable TftpDynamicCommand and LogoDxe for XCODE5

[Michael D Kinney]

From: Andrew Fish 

Disable TftpDynamicCommand for XCODE5 because this command
places HII content in an PE/COFF resource section that is not
supported by the XCODE5 tool chain, and the missing HII
content causes the load of this command to ASSERT().

Disable the LogoDxe module that places the logo bitmap in
a PE/COFF resource section that is not supported by the
XCODE5 tool chain, and the missing HII content causes
the load of this module to ASSERT().

Cc: Jordan Justen 
Cc: Ray Ni 
Cc: Michael D Kinney 
Signed-off-by: Andrew Fish 
Reviewed-by: Michael D Kinney 
Tested-by: Andrew Fish 
---
 EmulatorPkg/EmulatorPkg.dsc | 4 
 EmulatorPkg/EmulatorPkg.fdf | 4 
 2 files changed, 8 insertions(+)

diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc
index 0af2d1ff95..20f1187713 100644
--- a/EmulatorPkg/EmulatorPkg.dsc
+++ b/EmulatorPkg/EmulatorPkg.dsc
@@ -332,7 +332,9 @@ [Components]
 
   MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+!if "XCODE5" not in $(TOOL_CHAIN_TAG)
   MdeModulePkg/Logo/LogoDxe.inf
+!endif
   MdeModulePkg/Universal/LoadFileOnFv2/LoadFileOnFv2.inf
   MdeModulePkg/Application/UiApp/UiApp.inf {

@@ -375,10 +377,12 @@ [Components]
 
   FatPkg/EnhancedFatDxe/Fat.inf
 
+!if "XCODE5" not in $(TOOL_CHAIN_TAG)
   ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {
 
   gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
   }
+!endif
   ShellPkg/Application/Shell/Shell.inf {
 
   
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
diff --git a/EmulatorPkg/EmulatorPkg.fdf b/EmulatorPkg/EmulatorPkg.fdf
index ec411e82b4..295f6f1db8 100644
--- a/EmulatorPkg/EmulatorPkg.fdf
+++ b/EmulatorPkg/EmulatorPkg.fdf
@@ -178,7 +178,9 @@ [FV.FvRecovery]
 INF  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
 INF  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
 INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+!if "XCODE5" not in $(TOOL_CHAIN_TAG)
 INF  MdeModulePkg/Logo/LogoDxe.inf
+!endif
 INF  MdeModulePkg/Universal/LoadFileOnFv2/LoadFileOnFv2.inf
 INF  RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
 INF  MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
@@ -194,7 +196,9 @@ [FV.FvRecovery]
 
 INF FatPkg/EnhancedFatDxe/Fat.inf
 
+!if "XCODE5" not in $(TOOL_CHAIN_TAG)
 INF  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+!endif
 INF  ShellPkg/Application/Shell/Shell.inf
 
 [Rule.Common.SEC]
-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 07/11] EmulatorPkg/Unix/Host: Initialize field in BerkeleyPacketFilter.c

[Michael D Kinney]

From: Andrew Fish 

Initialize Private->ReadBuffer to NULL.

Cc: Jordan Justen 
Cc: Ray Ni 
Cc: Michael D Kinney 
Signed-off-by: Andrew Fish 
Reviewed-by: Michael D Kinney 
Tested-by: Andrew Fish 
---
 EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c 
b/EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c
index 8d0eb0d197..540340f25f 100644
--- a/EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c
+++ b/EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c
@@ -216,6 +216,7 @@ EmuSnpStart (
   }
 
   Status = EFI_SUCCESS;
+  Private->ReadBuffer = NULL;
   if (Private->BpfFd == 0) {
 Status = OpenBpfFileDescriptor (Private, &Private->BpfFd);
 if (EFI_ERROR (Status)) {
-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 03/11] EmulatorPkg: Add -D DISABLE_NEW_DEPRECATED_INTERFACES

[Michael D Kinney]

https://bugzilla.tianocore.org/show_bug.cgi?id=162

Update EmulatorPkg specific modules and libraries to use
safe string functions in BaseLib and safe PcdSetxx()
functions in PcdLib.  With these updates, the define
DISABLE_NEW_DEPRECATED_INTERFACES is enabled in the DSC
file.

Cc: Jordan Justen 
Cc: Andrew Fish 
Cc: Ray Ni 
Signed-off-by: Michael D Kinney 
Reviewed-by: Hao A Wu 
Acked-by: Jordan Justen 
Tested-by: Andrew Fish 
---
 EmulatorPkg/EmuBusDriverDxe/EmuBusDriverDxe.c |   9 +-
 EmulatorPkg/EmulatorPkg.dsc   |   6 +-
 EmulatorPkg/FlashMapPei/FlashMapPei.c |   8 +-
 EmulatorPkg/Library/SmbiosLib/SmbiosLib.c |   4 +-
 .../ThunkProtocolList/ThunkProtocolList.c |  11 +-
 EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c  |  10 +-
 EmulatorPkg/Unix/Host/PosixFileSystem.c   |  80 
 EmulatorPkg/Unix/Host/X11GraphicsWindow.c |   4 +-
 EmulatorPkg/Win/Host/WinFileSystem.c  | 116 --
 9 files changed, 172 insertions(+), 76 deletions(-)

diff --git a/EmulatorPkg/EmuBusDriverDxe/EmuBusDriverDxe.c 
b/EmulatorPkg/EmuBusDriverDxe/EmuBusDriverDxe.c
index 0bf6e723a1..d8380f2be9 100644
--- a/EmulatorPkg/EmuBusDriverDxe/EmuBusDriverDxe.c
+++ b/EmulatorPkg/EmuBusDriverDxe/EmuBusDriverDxe.c
@@ -1,7 +1,7 @@
 /** @file
  Emu Bus driver
 
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 Portions copyright (c) 2011, Apple Inc. All rights reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -256,7 +256,12 @@ EmuBusDriverBindingStart (
 
   EmuDevice->ControllerNameTable = NULL;
 
-  StrnCpy (ComponentName, EmuIoThunk->ConfigString, sizeof 
(ComponentName)/sizeof (CHAR16));
+  StrnCpyS (
+ComponentName,
+sizeof (ComponentName) / sizeof (CHAR16),
+EmuIoThunk->ConfigString,
+sizeof (ComponentName) / sizeof (CHAR16)
+);
 
   EmuDevice->DevicePath = EmuBusCreateDevicePath (
   ParentDevicePath,
diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc
index 153da464f1..529adfe1fa 100644
--- a/EmulatorPkg/EmulatorPkg.dsc
+++ b/EmulatorPkg/EmulatorPkg.dsc
@@ -408,10 +408,14 @@ [Components]
 !include NetworkPkg/Network.dsc.inc
 
 [BuildOptions]
+  #
+  # Disable deprecated APIs.
+  #
+  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
+
   MSFT:DEBUG_*_*_CC_FLAGS = /Od /Oy-
   MSFT:NOOPT_*_*_CC_FLAGS = /Od /Oy-
 
   MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 /FILEALIGN:4096 /SUBSYSTEM:CONSOLE
   MSFT:DEBUG_*_*_DLINK_FLAGS = /EXPORT:InitializeDriver=$(IMAGE_ENTRY_POINT) 
/BASE:0x1
   MSFT:NOOPT_*_*_DLINK_FLAGS = /EXPORT:InitializeDriver=$(IMAGE_ENTRY_POINT) 
/BASE:0x1
-
diff --git a/EmulatorPkg/FlashMapPei/FlashMapPei.c 
b/EmulatorPkg/FlashMapPei/FlashMapPei.c
index 2a468e43ac..7744065dd6 100644
--- a/EmulatorPkg/FlashMapPei/FlashMapPei.c
+++ b/EmulatorPkg/FlashMapPei/FlashMapPei.c
@@ -1,7 +1,7 @@
 /*++ @file
   PEIM to build GUIDed HOBs for platform specific flash map
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 Portions copyright (c) 2011, Apple Inc. All rights reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -69,9 +69,9 @@ Returns:
 return Status;
   }
 
-  PcdSet64 (PcdFlashNvStorageVariableBase64, PcdGet64 
(PcdEmuFlashNvStorageVariableBase) + FdFixUp);
-  PcdSet64 (PcdFlashNvStorageFtwWorkingBase64, PcdGet64 
(PcdEmuFlashNvStorageFtwWorkingBase) + FdFixUp);
-  PcdSet64 (PcdFlashNvStorageFtwSpareBase64, PcdGet64 
(PcdEmuFlashNvStorageFtwSpareBase) + FdFixUp);
+  PcdSet64S (PcdFlashNvStorageVariableBase64, PcdGet64 
(PcdEmuFlashNvStorageVariableBase) + FdFixUp);
+  PcdSet64S (PcdFlashNvStorageFtwWorkingBase64, PcdGet64 
(PcdEmuFlashNvStorageFtwWorkingBase) + FdFixUp);
+  PcdSet64S (PcdFlashNvStorageFtwSpareBase64, PcdGet64 
(PcdEmuFlashNvStorageFtwSpareBase) + FdFixUp);
 
   return EFI_SUCCESS;
 }
diff --git a/EmulatorPkg/Library/SmbiosLib/SmbiosLib.c 
b/EmulatorPkg/Library/SmbiosLib/SmbiosLib.c
index 331122e200..3acbb23644 100644
--- a/EmulatorPkg/Library/SmbiosLib/SmbiosLib.c
+++ b/EmulatorPkg/Library/SmbiosLib/SmbiosLib.c
@@ -4,7 +4,7 @@
 
 
 Copyright (c) 2012, Apple Inc. All rights reserved.
-Portitions Copyright (c) 2006 - 2012, Intel Corporation. All rights 
reserved.
+Portitions Copyright (c) 2006 - 2019, Intel Corporation. All rights 
reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -223,7 +223,7 @@ SmbiosLibUpdateUnicodeString (
   if (Ascii == NULL) {
 return EFI_OUT_OF_RESOURCES;
   }
-  UnicodeStrToAsciiStr (String, Ascii);
+  UnicodeStrToAsciiStrS (String, Ascii, StrSize (String));
 
   StringIndex = StringNumber;
   Status = gSmbios->UpdateString (gSmbios, &SmbiosHandle, &StringIndex, Ascii);
diff --git a/EmulatorPkg/Library/ThunkProtocolList/ThunkProtocolList.c 
b/EmulatorPkg/Library/ThunkProtocolList/ThunkProto

[edk2-devel] [Patch V5 01/11] EmulatorPkg: Fix VS20xx IA32 boot failure

[Michael D Kinney]

https://bugzilla.tianocore.org/show_bug.cgi?id=2056

The IA32 build of the EmulatorPkg for VS20xx does not boot
because the default value of PCD PcdPeiServicesTablePage
rarely succeeds to be mapped on IA32 Windows Host Environments.
Change the DEC default value for this PCD to a value that
is compatible with Windows and POSIX host environments for
IA32 and X64.  For IA32 builds, this 64-bit PCD is truncated
to a 32-bit value.

PcdPeiServicesTablePage is changed from 0x100300 to
0x101300.  With this new value, no boot failures are
observed.  However, the use of this hard coded value can
potentially cause a boot failure if this address specified
by the PCD is already allocated in the user process.

Cc: Jordan Justen 
Cc: Andrew Fish 
Cc: Ray Ni 
Signed-off-by: Michael D Kinney 
Reviewed-by: Hao A Wu 
Reviewed-by: Jordan Justen 
Tested-by: Andrew Fish 
---
 EmulatorPkg/EmulatorPkg.dec | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/EmulatorPkg/EmulatorPkg.dec b/EmulatorPkg/EmulatorPkg.dec
index c36f2c4186..99250d9fe5 100644
--- a/EmulatorPkg/EmulatorPkg.dec
+++ b/EmulatorPkg/EmulatorPkg.dec
@@ -2,7 +2,7 @@
 #
 # This is the Emu Emulation Environment Platform
 #
-# Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
 # Portions copyright (c) 2011, Apple Inc. All rights reserved.
 #
 #SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -66,7 +66,7 @@ [PcdsFixedAtBuild]
   gEmulatorPkgTokenSpaceGuid.PcdEmuApCount|L"0"|VOID*|0x1019
 
   ## Magic page to implement PEI Services Table Pointer Lib
-  
gEmulatorPkgTokenSpaceGuid.PcdPeiServicesTablePage|0x100300|UINT64|0x101b
+  
gEmulatorPkgTokenSpaceGuid.PcdPeiServicesTablePage|0x101300|UINT64|0x101b
 
   ## Size of the packet filter
   
gEmulatorPkgTokenSpaceGuid.PcdNetworkPacketFilterSize|524288|UINT32|0x101c
-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 08/11] EmulatorPkg/Unix/Host: Remove debug code from BerkeleyPacketFilter.c

[Michael D Kinney]

From: Andrew Fish 

Remove old debug code that generates an exception.

Cc: Jordan Justen 
Cc: Ray Ni 
Cc: Michael D Kinney 
Signed-off-by: Andrew Fish 
Reviewed-by: Michael D Kinney 
Tested-by: Andrew Fish 
---
 EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c 
b/EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c
index 540340f25f..3013bbc86b 100644
--- a/EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c
+++ b/EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c
@@ -767,10 +767,6 @@ EmuSnpGetStatus (
 
   Private = EMU_SNP_PRIVATE_DATA_FROM_THIS (This);
 
-  if (TxBuf != NULL) {
-*((UINT8 **)TxBuf) =  (UINT8 *)1;
-  }
-
   if ( InterruptStatus != NULL ) {
 *InterruptStatus = EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
   }
-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 10/11] EmulatorPkg/Sec: Change scope of PpiArray[10]

[Michael D Kinney]

From: Andrew Fish 

The local variable PpiArray[10] is declared in the middle
of the SEC module _ModuleEntryPoint() with its own scope.
However, PpiArray has a dangling reference to its location
on the stack after the scope is closed.  This causes issues
with some compilers (e.g. XCODE5).

The fix is to move the declaration of PpiArray[10] to
the beginning of the function, so it is scoped correctly
for all references to this local variable and references
to its location.

Cc: Jordan Justen 
Cc: Ray Ni 
Cc: Michael D Kinney 
Signed-off-by: Andrew Fish 
Reviewed-by: Michael D Kinney 
Tested-by: Andrew Fish 
---
 EmulatorPkg/Sec/Sec.c | 16 +++-
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/EmulatorPkg/Sec/Sec.c b/EmulatorPkg/Sec/Sec.c
index 701032233b..b734d2bb87 100644
--- a/EmulatorPkg/Sec/Sec.c
+++ b/EmulatorPkg/Sec/Sec.c
@@ -75,6 +75,7 @@ _ModuleEntryPoint (
   EFI_PEI_PPI_DESCRIPTOR*SecPpiList;
   UINTN SecReseveredMemorySize;
   UINTN Index;
+  EFI_PEI_PPI_DESCRIPTORPpiArray[10];
 
   EMU_MAGIC_PAGE()->PpiList = PpiList;
   ProcessLibraryConstructorList ();
@@ -104,16 +105,13 @@ _ModuleEntryPoint (
   SecCoreData->PeiTemporaryRamBase = (VOID 
*)((UINTN)SecCoreData->PeiTemporaryRamBase + SecReseveredMemorySize);
   SecCoreData->PeiTemporaryRamSize -= SecReseveredMemorySize;
 #else
-  {
-//
-// When I subtrack from SecCoreData->PeiTemporaryRamBase PEI Core crashes? 
Either there is a bug
-// or I don't understand temp RAM correctly?
-//
-EFI_PEI_PPI_DESCRIPTORPpiArray[10];
+  //
+  // When I subtrack from SecCoreData->PeiTemporaryRamBase PEI Core crashes? 
Either there is a bug
+  // or I don't understand temp RAM correctly?
+  //
 
-SecPpiList = &PpiArray[0];
-ASSERT (sizeof (PpiArray) >= SecReseveredMemorySize);
-  }
+  SecPpiList = &PpiArray[0];
+  ASSERT (sizeof (PpiArray) >= SecReseveredMemorySize);
 #endif
   // Copy existing list, and append our entries.
   CopyMem (SecPpiList, PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR) * Index);
-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 00/11] EmulatorPkg: Fix VS20xx IA32 boot and simplify build config

[Michael D Kinney]

New in V5
=
* Update author to be Andrew Fish for XCODE5 fixes
* Split patch #7 into two patches
* Break up long line in build.sh into multiple lines

New in V4 (Resolve XCODE5 issues)
==
* Disable inline if SecGdbScriptBreak() for XCODE5 issues
* Disable XCODE5 compiler optimizations of Unix/Host
* Fix Host output location for XCODE5 X64 builds
* Update lldb scripts for XCODE5 symbiolic debugging
* Clean up BrekelyPlacketFilter.c for uninitialized variable and old debug code.
* Remove TftpDynamicCommand and LogoDxe modules from XCODE5 builds.  These 
  modules use HII section in a PE/COFF resource sections that is not currently
  supported by XCODE5 builds.
* EmulatorPkg/Sec - Move declaration of PpiArray[10] to beginning of function
  so storage is for entire lifetime of the function.  Delaractrion in the 
  middle of the function in {} cause corruption and exceptions in XCODE5 builds.
* Add -gdwarf flag to tols_def.template for XCODE5 X64 for symbolic debug.

New in V3
==
* Fix size value used in call to AsciiStrCpyS() in PosixFileSystem.c
* Fix XCODE5 safe string function build failure in BerkleyPacketFilter.c
* Add NOOPT build target to DSC file.

New in V2
=
* Fix size values in safe string function calls.
* Update POSIX sources to use AsciiStrCpyS() and AsciiStrCatS().
* Verify that no exceptions occur if EMU_MAGIC_PAGE() can not be mapped.  An
  error message is generated and the host app exits normally.
* Update EmulatorPkg DEC file with a new PcdPeiServicesTablePage default value
  that works for Windows/POSIX hosts for both IA32 and X64.

https://bugzilla.tianocore.org/show_bug.cgi?id=162
https://bugzilla.tianocore.org/show_bug.cgi?id=2055
https://bugzilla.tianocore.org/show_bug.cgi?id=2056

* Fix VS20xx IA32 boot failure
* Remove UNIX_SEC_BUILD/WIN_SEC_BUILD
* Add -D DISABLE_NEW_DEPRECATED_INTERFACES

Cc: Jordan Justen 
Cc: Andrew Fish 
Cc: Ray Ni 
Signed-off-by: Michael D Kinney 

Andrew Fish (7):
  EmulatorPkg/Unix/Host: Disable inline/optimizations
  EmulatorPkg: Fix XCODE5 lldb issues
  EmulatorPkg/Unix/Host: Initialize field in BerkeleyPacketFilter.c
  EmulatorPkg/Unix/Host: Remove debug code from BerkeleyPacketFilter.c
  EmulatorPkg: Disable TftpDynamicCommand and LogoDxe for XCODE5
  EmulatorPkg/Sec: Change scope of PpiArray[10]
  BaseTools/tools_def.template: Add -gdwarf to XCODE5 X64

Michael D Kinney (4):
  EmulatorPkg: Fix VS20xx IA32 boot failure
  EmulatorPkg: Remove UNIX_SEC_BUILD/WIN_SEC_BUILD
  EmulatorPkg: Add -D DISABLE_NEW_DEPRECATED_INTERFACES
  EmulatorPkg: Add support for NOOPT target

 BaseTools/Conf/tools_def.template |   4 +-
 EmulatorPkg/EmuBusDriverDxe/EmuBusDriverDxe.c |   9 +-
 EmulatorPkg/EmulatorPkg.dec   |   4 +-
 EmulatorPkg/EmulatorPkg.dsc   |  38 +++---
 EmulatorPkg/EmulatorPkg.fdf   |   4 +
 EmulatorPkg/FlashMapPei/FlashMapPei.c |   8 +-
 EmulatorPkg/Library/SmbiosLib/SmbiosLib.c |   4 +-
 .../ThunkProtocolList/ThunkProtocolList.c |  11 +-
 EmulatorPkg/Readme.md |   8 +-
 EmulatorPkg/Sec/Sec.c |  16 ++-
 EmulatorPkg/Unix/Host/BerkeleyPacketFilter.c  |  15 +--
 EmulatorPkg/Unix/Host/Host.c  |   3 +
 EmulatorPkg/Unix/Host/Host.inf|   4 +-
 EmulatorPkg/Unix/Host/PosixFileSystem.c   |  80 
 EmulatorPkg/Unix/Host/X11GraphicsWindow.c |   4 +-
 EmulatorPkg/Unix/lldbefi.py   |   8 +-
 EmulatorPkg/Win/Host/WinFileSystem.c  | 116 --
 EmulatorPkg/Win/VS2017/BuildVS.bat|   2 +-
 EmulatorPkg/build.sh  |  29 ++---
 19 files changed, 231 insertions(+), 136 deletions(-)

-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 04/11] EmulatorPkg: Add support for NOOPT target

[Michael D Kinney]

Add NOOPT to BUILD_TARGETS in DSC file.

Cc: Jordan Justen 
Cc: Andrew Fish 
Cc: Ray Ni 
Signed-off-by: Michael D Kinney 
Reviewed-by: Hao A Wu 
Reviewed-by: Jordan Justen 
Tested-by: Andrew Fish 
---
 EmulatorPkg/EmulatorPkg.dsc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc
index 529adfe1fa..0af2d1ff95 100644
--- a/EmulatorPkg/EmulatorPkg.dsc
+++ b/EmulatorPkg/EmulatorPkg.dsc
@@ -19,7 +19,7 @@ [Defines]
   OUTPUT_DIRECTORY   = Build/Emulator$(ARCH)
 
   SUPPORTED_ARCHITECTURES= X64|IA32
-  BUILD_TARGETS  = DEBUG|RELEASE
+  BUILD_TARGETS  = DEBUG|RELEASE|NOOPT
   SKUID_IDENTIFIER   = DEFAULT
   FLASH_DEFINITION   = EmulatorPkg/EmulatorPkg.fdf
 
-- 
2.21.0.windows.1


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[edk2-devel] [Patch V5 02/11] EmulatorPkg: Remove UNIX_SEC_BUILD/WIN_SEC_BUILD

[Michael D Kinney]

https://bugzilla.tianocore.org/show_bug.cgi?id=2055

Remove the use of the defines UNIX_SEC_BUILD and
WIN_SEC_BUILD.  This simplifies the build command
for the EmulatorPkg.  Instead, use !if statements
in the DSC file using $(ARCH) and $(FAMILY) to
determine if the build is for a Windows or POSIX
environment.

The Readme.md, BAT, and sh files are also updated
to remove the use of these defines.

Cc: Jordan Justen 
Cc: Andrew Fish 
Cc: Ray Ni 
Signed-off-by: Michael D Kinney 
Reviewed-by: Hao A Wu 
Reviewed-by: Jordan Justen 
Tested-by: Andrew Fish 
---
 EmulatorPkg/EmulatorPkg.dsc| 26 +-
 EmulatorPkg/Readme.md  |  8 
 EmulatorPkg/Win/VS2017/BuildVS.bat |  2 +-
 EmulatorPkg/build.sh   |  8 
 4 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc
index ea8b6ce76e..153da464f1 100644
--- a/EmulatorPkg/EmulatorPkg.dsc
+++ b/EmulatorPkg/EmulatorPkg.dsc
@@ -4,7 +4,7 @@
 # The Emulation Platform can be used to debug individual modules, prior to 
creating
 # a real platform. This also provides an example for how an DSC is created.
 #
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 # Portions copyright (c) 2010 - 2011, Apple Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -236,18 +236,18 @@ [PcdsDynamicHii.common.DEFAULT]
   
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
 
 [Components]
-!ifdef $(UNIX_SEC_BUILD)
-  ##
-  #  Emulator, OS POSIX application
-  ##
-  EmulatorPkg/Unix/Host/Host.inf
-!endif
-
-!ifdef $(WIN_SEC_BUILD)
-  ##
-  #  Emulator, OS WIN application
-  ##
-  EmulatorPkg/Win/Host/WinHost.inf
+!if "IA32" in $(ARCH) || "X64" in $(ARCH)
+  !if "MSFT" in $(FAMILY)
+##
+#  Emulator, OS WIN application
+##
+EmulatorPkg/Win/Host/WinHost.inf
+  !else
+##
+#  Emulator, OS POSIX application
+##
+EmulatorPkg/Unix/Host/Host.inf
+  !endif
 !endif
 
 !ifndef $(SKIP_MAIN_BUILD)
diff --git a/EmulatorPkg/Readme.md b/EmulatorPkg/Readme.md
index 461975e859..5ea61ca7ab 100644
--- a/EmulatorPkg/Readme.md
+++ b/EmulatorPkg/Readme.md
@@ -21,19 +21,19 @@ 
https://github.com/tianocore/tianocore.github.io/wiki/EmulatorPkg
 **You can use the following command to build.**
   * 32bit emulator in Windows:
 
-`build -p EmulatorPkg\EmulatorPkg.dsc -t VS2017 -D WIN_SEC_BUILD -a IA32`
+`build -p EmulatorPkg\EmulatorPkg.dsc -t VS2017 -a IA32`
 
   * 64bit emulator in Windows:
 
-`build -p EmulatorPkg\EmulatorPkg.dsc -t VS2017 -D WIN_SEC_BUILD -a X64`
+`build -p EmulatorPkg\EmulatorPkg.dsc -t VS2017 -a X64`
 
   * 32bit emulator in Linux:
 
-`build -p EmulatorPkg\EmulatorPkg.dsc -t GCC5 -D UNIX_SEC_BUILD -a IA32`
+`build -p EmulatorPkg\EmulatorPkg.dsc -t GCC5 -a IA32`
 
   * 64bit emulator in Linux:
 
-`build -p EmulatorPkg\EmulatorPkg.dsc -t GCC5 -D UNIX_SEC_BUILD -a X64`
+`build -p EmulatorPkg\EmulatorPkg.dsc -t GCC5 -a X64`
 
 **You can start/run the emulator using the following command:**
   * 32bit emulator in Windows:
diff --git a/EmulatorPkg/Win/VS2017/BuildVS.bat 
b/EmulatorPkg/Win/VS2017/BuildVS.bat
index 83aebc77dc..6fcf40cc0a 100644
--- a/EmulatorPkg/Win/VS2017/BuildVS.bat
+++ b/EmulatorPkg/Win/VS2017/BuildVS.bat
@@ -1,3 +1,3 @@
 cd ../../../
 @call edksetup.bat
-build -p EmulatorPkg\EmulatorPkg.dsc -t VS2017 -D WIN_SEC_BUILD %*
+build -p EmulatorPkg\EmulatorPkg.dsc -t VS2017 %*
diff --git a/EmulatorPkg/build.sh b/EmulatorPkg/build.sh
index 2dab035ed5..60056e1b6c 100755
--- a/EmulatorPkg/build.sh
+++ b/EmulatorPkg/build.sh
@@ -233,13 +233,13 @@ fi
 
 case $CLEAN_TYPE in
   clean)
-build -p $WORKSPACE/EmulatorPkg/EmulatorPkg.dsc -a $PROCESSOR -b 
$BUILDTARGET -t $HOST_TOOLS -D UNIX_SEC_BUILD -n 3 clean
+build -p $WORKSPACE/EmulatorPkg/EmulatorPkg.dsc -a $PROCESSOR -b 
$BUILDTARGET -t $HOST_TOOLS -n 3 clean
 build -p $WORKSPACE/EmulatorPkg/EmulatorPkg.dsc -a $PROCESSOR -b 
$BUILDTARGET -t $TARGET_TOOLS -n 3 clean
 exit $?
 ;;
   cleanall)
 make -C $WORKSPACE/BaseTools clean
-build -p $WORKSPACE/EmulatorPkg/EmulatorPkg.dsc -a $PROCESSOR -b 
$BUILDTARGET -t $HOST_TOOLS -D UNIX_SEC_BUILD -n 3 clean
+build -p $WORKSPACE/EmulatorPkg/EmulatorPkg.dsc -a $PROCESSOR -b 
$BUILDTARGET -t $HOST_TOOLS -n 3 clean
 build -p $WORKSPACE/EmulatorPkg/EmulatorPkg.dsc -a $PROCESSOR -b 
$BUILDTARGET -t $TARGET_TOOLS -n 3 clean
 build -p $WORKSPACE/ShellPkg/ShellPkg.dsc -a IA32 -b $BUILDTARGET -t 
$TARGET_TOOLS -n 3 clean
 exit $?
@@ -251,9 +251,9 @@ esac
 # Build the edk2 EmulatorPkg
 #
 if [[ $HOST_TOOLS == $TARGET_TOOLS ]]; then
-  build -p $WORKSPACE/EmulatorPkg/EmulatorPkg.dsc $BUILD_OPTIONS -a $PROCESSOR 
-b $BUILDTARGET -t $TARGET_TOOLS -D BUILD_$ARCH_SIZE -D UNIX_SEC_BUILD 
$NETWORK_SUPPORT $BUILD_NEW_SHELL $BUILD_FAT -n 3
+  build

[edk2-devel] [Patch V5 06/11] EmulatorPkg: Fix XCODE5 lldb issues

[Michael D Kinney]

From: Andrew Fish 

Fix scripts to support lldb symbolic debugging when
using XCODE5 tool chain.

Cc: Jordan Justen 
Cc: Ray Ni 
Cc: Michael D Kinney 
Signed-off-by: Andrew Fish 
Reviewed-by: Michael D Kinney 
Tested-by: Andrew Fish 
---
 EmulatorPkg/Unix/lldbefi.py |  8 +---
 EmulatorPkg/build.sh| 21 ++---
 2 files changed, 11 insertions(+), 18 deletions(-)

diff --git a/EmulatorPkg/Unix/lldbefi.py b/EmulatorPkg/Unix/lldbefi.py
index 218326b8cb..099192d8b5 100755
--- a/EmulatorPkg/Unix/lldbefi.py
+++ b/EmulatorPkg/Unix/lldbefi.py
@@ -346,6 +346,7 @@ def TypePrintFormating(debugger):
 debugger.HandleCommand("type summary add CHAR8 --python-function 
lldbefi.CHAR8_TypeSummary")
 debugger.HandleCommand('type summary add --regex "CHAR8 \[[0-9]+\]" 
--python-function lldbefi.CHAR8_TypeSummary')
 
+debugger.HandleCommand('setting set frame-format "frame #${frame.index}: 
${frame.pc}{ 
${module.file.basename}{:${function.name}()${function.pc-offset}}}{ at 
${line.file.fullpath}:${line.number}}\n"')
 
 gEmulatorBreakWorkaroundNeeded = True
 
@@ -381,15 +382,16 @@ def LoadEmulatorEfiSymbols(frame, bp_loc , internal_dict):
 Error = lldb.SBError()
 FileNamePtr = frame.FindVariable ("FileName").GetValueAsUnsigned()
 FileNameLen = frame.FindVariable ("FileNameLength").GetValueAsUnsigned()
+
 FileName = frame.thread.process.ReadCStringFromMemory (FileNamePtr, 
FileNameLen, Error)
 if not Error.Success():
 print "!ReadCStringFromMemory() did not find a %d byte C string at %x" 
% (FileNameLen, FileNamePtr)
 # make breakpoint command contiue
-frame.GetThread().GetProcess().Continue()
+return False
 
 debugger = frame.thread.process.target.debugger
 if frame.FindVariable ("AddSymbolFlag").GetValueAsUnsigned() == 1:
-LoadAddress = frame.FindVariable ("LoadAddress").GetValueAsUnsigned()
+LoadAddress = frame.FindVariable ("LoadAddress").GetValueAsUnsigned() 
- 0x240
 
 debugger.HandleCommand ("target modules add  %s" % FileName)
 print "target modules load --slid 0x%x %s" % (LoadAddress, FileName)
@@ -405,7 +407,7 @@ def LoadEmulatorEfiSymbols(frame, bp_loc , internal_dict):
 print "!lldb.target.RemoveModule (%s) FAILED" % SBModule
 
 # make breakpoint command contiue
-frame.thread.process.Continue()
+return False
 
 def GuidToCStructStr (guid, Name=False):
   #
diff --git a/EmulatorPkg/build.sh b/EmulatorPkg/build.sh
index 60056e1b6c..76c22dfaf8 100755
--- a/EmulatorPkg/build.sh
+++ b/EmulatorPkg/build.sh
@@ -209,21 +209,12 @@ fi
 if [[ "$RUN_EMULATOR" == "yes" ]]; then
   case `uname` in
 Darwin*)
-  #
-  # On Darwin we can't use dlopen, so we have to load the real PE/COFF 
images.
-  # This .gdbinit script sets a breakpoint that loads symbols for the 
PE/COFFEE
-  # images that get loaded in Host
-  #
-  if [[ "$CLANG_VER" == *-ccc-host-triple* ]]
-  then
-  # only older versions of Xcode support -ccc-host-tripe, for newer 
versions
-  # it is -target
-cp $WORKSPACE/EmulatorPkg/Unix/lldbefi.py 
"$BUILD_OUTPUT_DIR/${BUILDTARGET}_$TARGET_TOOLS/$PROCESSOR"
-cd $BUILD_ROOT_ARCH; /usr/bin/lldb --source 
$WORKSPACE/EmulatorPkg/Unix/lldbinit Host
-exit $? 
-  else
-cp $WORKSPACE/EmulatorPkg/Unix/.gdbinit 
"$BUILD_OUTPUT_DIR/${BUILDTARGET}_$TARGET_TOOLS/$PROCESSOR"
-  fi
+  cd $BUILD_ROOT_ARCH
+  /usr/bin/lldb \
+-o "command script import $WORKSPACE/EmulatorPkg/Unix/lldbefi.py" \
+-o 'script lldb.debugger.SetAsync(True)' \
+-o "run" ./Host
+  exit $?
   ;;
   esac
 
-- 
2.21.0.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Gao, Liming ; Desimone, 
Nathaniel L ; Kinney, Michael D 
; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 36/37] 
WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083

Adds the DSC and build files necessary to build the
WhiskeylakeURvp board instance.

Key files
=
* build_config.cfg - Board-specific build configuration file.
* OpenBoardPkg.dsc - The WhiskeylakeURvp board description file.
* OpenBoardPkgConfig.dsc - Used for feature-related PCD
  customization.
* OpenBoardPkgPcd.dsc - Used for other PCD customization.
* OpenBoardPkg.fdf - The WhiskeylakeURvp board flash file.
* FlashMapInclude.fdf - The WhiskeylakeURvp board flash map.
* OpenBoardPkgBuildOption.dsc - Sets build options Based
  on PCD values.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Liming Gao 
Cc: Nate DeSimone 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
| 385 +++
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgBuildOption.dsc
 | 154 +
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgConfig.dsc  
| 128 
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc 
| 245 +++
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMapInclude.fdf
 |  49 ++
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
| 706 
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
|  33 +
 7 files changed, 1700 insertions(+)

diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
new file mode 100644
index 00..eea809140c
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
@@ -0,0 +1,385 @@
+## @file
+#  Platform description.
+#
+#
+#  Copyright (c) 2019, Intel Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  #
+  # Set platform specific package/folder name, same as passed from PREBUILD 
script.
+  # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package 
build folder
+  # DEFINE only takes effect at R9 DSC and FDF.
+  #
+  DEFINE  PLATFORM_PACKAGE  = MinPlatformPkg
+  DEFINE  PLATFORM_SI_PACKAGE   = CoffeelakeSiliconPkg
+  DEFINE  PLATFORM_SI_BIN_PACKAGE   = CoffeelakeSiliconBinPkg
+  DEFINE  PLATFORM_FSP_BIN_PACKAGE  = CoffeeLakeFspBinPkg
+  DEFINE  PLATFORM_BOARD_PACKAGE= WhiskeylakeOpenBoardPkg
+  DEFINE  BOARD = WhiskeylakeURvp
+  DEFINE  PROJECT   = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
+
+  #
+  # Platform On/Off features are defined here
+  #
+  !include OpenBoardPkgConfig.dsc
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME   = $(PLATFORM_PACKAGE)
+  PLATFORM_GUID   = 84D0F5BD-0EF3-4CC0-9B09-F2D0F2AA5C5E
+  PLATFORM_VERSION= 0.1
+  DSC_SPECIFICATION   = 0x00010005
+  OUTPUT_DIRECTORY= Build/$(PROJECT)
+  SUPPORTED_ARCHITECTURES = IA32|X64
+  BUILD_TARGETS   = DEBUG|RELEASE
+  SKUID_IDENTIFIER= ALL
+
+
+  FLASH_DEFINITION= $(PROJECT)/OpenBoardPkg.fdf
+
+  FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
+  DEFINE   TOP_MEMORY_ADDRESS = 0x0
+
+  #
+  # Default value for OpenBoardPkg.fdf use
+  #
+  DEFINE BIOS_SIZE_OPTION = SIZE_70
+
+
+#
+# SKU Identification section - list of all SKU IDs supported by this
+#  Platform.
+#
+
+[SkuIds]
+  0|DEFAULT  # The entry: 0|DEFAULT is reserved and always 
required.
+  0x60|WhiskeylakeURvp
+
+
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+
+
+  !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+  !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+  !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses.com

Re: [edk2-devel] [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Gao, Liming ; Desimone, 
Nathaniel L ; Kinney, Michael D 
; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global 
build config and documentation

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083

* Adds the WhiskeylakeURvp board as a build option in build.cfg so it
  it is listed as a valid build target.
* Updates relevant Readme.md files to include instructions for
  WhiskeylakeOpenBoardPkg.
* Adds the maintainers for WhiskeylakeOpenBoardPkg to maintainers.txt.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Liming Gao 
Cc: Nate DeSimone 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Maintainers.txt  |  5 +++
 Platform/Intel/Readme.md | 44 +---  Platform/Intel/build.cfg | 
 4 +-
 Readme.md|  1 +
 4 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt index bc8cbd6458..b16432bf87 
100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -98,6 +98,11 @@ M: Shifei A Lu 
 M: Xiaohu Zhou 
 M: Isaac W Oram 
 
+Platform/Intel/WhiskeylakeOpenBoardPkg
+M: Chasel Chiu 
+M: Michael Kubacki 
+M: Nate DeSimone 
+
 Platform/Intel/Tools
 M: Bob Feng 
 M: Liming Gao 
diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 
00f42985a2..aaf6ef4d3e 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -53,9 +53,10 @@ A UEFI firmware implementation using MinPlatformPkg is 
constructed using the fol
 
 
 ## Board Support
+* The `ClevoOpenBoardPkg` contains board implementations for Clevo systems.
 * The `KabylakeOpenBoardPkg` contains board implementations for Kaby Lake 
systems.
 * The `PurleyOpenBoardPkg` contains board implementations for Purley systems.
-* The `ClevoOpenBoardPkg` contains board implementations for Clevo systems.
+* The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey 
Lake systems.
 
 ## Board Package Organization
 The board package follows the standard EDK II package structure with the 
following additional elements and guidelines:
@@ -189,7 +190,12 @@ return back to the minimum platform caller.
   |   |||---build_config.cfg: 
BoardMtOlympus specific
   |   ||| build 
settings, environment variables.
   |   |||---build_board.py: Optional 
board-specific pre-build,
-  |   |||   build, 
post-build and clean functions.
+  |   ||build, 
post-build and clean functions.
+  |   ||
+  |   ||--WhiskeylakeOpenBoardPkg
+  |   |||--WhiskeylakeURvp
+  |   |||---build_config.cfg: 
WhiskeylakeURvp specific build
+  |   ||  settings 
environment variables.
   |--FSP
   
 
@@ -222,19 +228,6 @@ Users can also flash the UEFI firmware image to the 
highest area of the flash re
 
 ### **Known limitations**
 
-**KabylakeOpenBoardPkg**
-1. This firmware project has only been tested on the Intel KabylakeRvp3 board.
-2. This firmware project has only been tested booting to Microsoft Windows 10 
x64 with AHCI mode and Integrated Graphic
-  Device.
-3. The Windows build was tested on Windows 10 with Microsoft Visual Studio 
2015.
-4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
-5. The build was tested with NASM version 2.11.08.
-
-**PurleyOpenBoardPkg**
-1. This firmware project has only been tested on the Microsoft MtOlympus board.
-2. This firmware project has only been tested booting to Microsoft Windows 
Server 2016 with NVME on M.2 slot.
-3. This firmware project build has only been tested using the Microsoft Visual 
Studio 2015 compiler.
-
 **ClevoOpenBoardPkg**
 1. Currently, support is only being added for the N1xxWU series of boards.
 2. The Windows build was tested on Windows 10 with Microsoft Visual Studio 
2015 compiler.
@@ -244,6 +237,27 @@ Users can also flash the UEFI firmware image to the 
highest area of the flash re  6. The firmware project applies to all Clevo 
supported board configurations but is only being tested on System 76 Galago
   Pro devices.
 
+**KabylakeOpenBoardPkg**
+1. This firmware project has only been tested on the Intel KabylakeRvp3 board.
+2. This firmware project has only been tested booting to Microsoft 
+Windows 10 x64 with AHCI mode and Integrated Graphic
+  Device.
+3. The Windows build was tested on Windows 10 with Microsoft Visual Studio 
2015.
+4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
+5. The build was tested with NASM version 2.1

Re: [edk2-devel] [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Gao, Liming ; Desimone, 
Nathaniel L ; Kinney, Michael D 
; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 32/37] 
WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083

Header files for the WhiskeylakeURvp board instance.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Liming Gao 
Cc: Nate DeSimone 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h
  | 131 
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h 
 |  40 ++
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
 | 105 
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformInfo.h  
  |  44 +++
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
   |  12 ++
 5 files changed, 332 insertions(+)

diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h
new file mode 100644
index 00..bd849b9ee2
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Pei
+++ PlatformHookLib.h
@@ -0,0 +1,131 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_PLATFORM_HOOK_LIB_H_
+#define _PEI_PLATFORM_HOOK_LIB_H_
+
+#include 
+#include 
+#include 
+
+
+//EC Command to provide one byte of debug indication #define 
+BSSB_DEBUG_INDICATION 0xAE
+/**
+  Configure EC for specific devices
+
+  @param[in] PchLan   - The PchLan of PCH_SETUP variable.
+  @param[in] BootMode - The current boot mode.
+**/
+VOID
+EcInit (
+  IN UINT8PchLan,
+  IN EFI_BOOT_MODEBootMode
+  );
+
+/**
+  Checks if Premium PMIC present
+
+  @retval  TRUE  if present
+  @retval  FALSE it discrete/other PMIC **/ BOOLEAN 
+IsPremiumPmicPresent (
+  VOID
+  );
+
+/**
+  Pmic Programming to supprort LPAL Feature
+
+  @retval NONE
+**/
+VOID
+PremiumPmicDisableSlpS0Voltage (
+  VOID
+  );
+
+/**
+Pmic Programming to supprort LPAL Feature
+  @retval NONE
+**/
+VOID
+PremiumPmicEnableSlpS0Voltage(
+  VOID
+  );
+
+/**
+  Do platform specific programming pre-memory. For example, EC init, 
+Chipset programming
+
+  @retval  Status
+**/
+EFI_STATUS
+PlatformSpecificInitPreMem (
+  VOID
+  );
+
+/**
+  Do platform specific programming post-memory.
+
+  @retval  Status
+**/
+EFI_STATUS
+PlatformSpecificInit (
+  VOID
+  );
+
+/**
+  Configure GPIO and SIO Before Memory is ready.
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+  VOID
+  );
+
+/**
+  Configure GPIO and SIO
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInit (
+  VOID
+  );
+
+/**
+Voltage Margining Routine
+
+@retval  EFI_SUCCESS   Operation success
+**/
+EFI_STATUS
+VoltageMarginingRoutine(
+  VOID
+  );
+
+/**
+  Detect recovery mode
+
+  @retval  EFI_SUCCESS   System in Recovery Mode
+  @retval  EFI_UNSUPPORTED   System doesn't support Recovery Mode
+  @retval  EFI_NOT_FOUND System is not in Recovery Mode
+**/
+EFI_STATUS
+IsRecoveryMode (
+  VOID
+  );
+
+/**
+  Early board Configuration before Memory is ready.
+
+  @retval  EFI_SUCCESS  Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+  VOID
+  );
+#endif
+
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h
new file mode 100644
index 00..d65586dbb9
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Pei
+++ PlatformLib.h
@@ -0,0 +1,40 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED  1
+
+typedef struct {
+  UINT8   Register;
+  UINT32  Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+  PCH_GPIO_DEV Use_Sel;
+  PCH_GPIO_DEV Use_Sel2;
+  PCH_GPIO_DEV Use_Sel3;
+  PCH_GPIO_DEV Io_Sel;
+  PCH_GPIO_DEV Io_Sel2;
+  PCH_GPIO_DEV Io_Sel3;
+  PCH_GPIO_DEV Lvl;
+  PCH_GPIO_DEV Lvl2;
+  PCH_GPIO_DEV Lvl3;
+  PCH_GPIO_DEV Inv;
+  PCH_GPIO_DEV Blink;
+  PCH_GPIO_DEV Rst_Sel;
+  PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
+
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
new f

Re: [edk2-devel] [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC 
files

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 215 

 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc | 130 
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc   |  69 +++
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc |  33 +++
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc  |  37 
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc |  21 ++
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc  |  44 
 7 files changed, 549 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc 
b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
new file mode 100644
index 00..37c77d8f63
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
@@ -0,0 +1,215 @@
+## @file
+#  Component description file for the Coffee Lake silicon package DSC file.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[PcdsFeatureFlag]
+gSiPkgTokenSpaceGuid.PcdTraceHubEnable   |FALSE
+gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdAtaEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdSiCsmEnable  |FALSE
+gSiPkgTokenSpaceGuid.PcdUseHpetTimer |TRUE
+gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE
+gSiPkgTokenSpaceGuid.PcdAcpiEnable   |FALSE
+gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdJhiEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE
+gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE
+gSiPkgTokenSpaceGuid.PcdOverclockEnable  |FALSE
+gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable   |FALSE
+gSiPkgTokenSpaceGuid.PcdBdatEnable   |TRUE
+gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdSaDmiEnable  |TRUE
+gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdSaOcEnable   |TRUE
+gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable   |TRUE
+gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE
+gSiPkgTokenSpaceGuid.PcdCflCpuEnable |FALSE
+gSiPkgTokenSpaceGuid.PcdOcWdtEnable  |TRUE
+gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable   |TRUE
+gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
+
+[PcdsFixedAtBuild.common]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress   |0xE000
+gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x1000
+
+  gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin|10
+  gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax|18
+
+[PcdsDynamicDefault.common]
+gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength  |0x1000
+
+## Specifies the AP wait loop state during POST phase.
+#  The value is defined as below.
+#  1: Place AP in the Hlt-Loop state.
+#  2: Place AP in the Mwait-Loop state.
+#  3: Place AP in the Run-Loop state.
+# @Prompt The AP wait loop state.
+gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+## Specifies the AP target C-state for Mwait during POST phase.
+#  The default value 0 means C1 state.
+#  The value is defined as below. # @Prompt The specified AP 
+target C-state for Mwait.
+gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
+
+[Defines]
+  PLATFORM_NAME = CoffeelakeSiliconPkg
+  PLATFORM_GUID = A45CA44C-AB04-4932-A77C-5A7179F66A22
+  PLATFORM_VERSION = 0.4
+  DSC_SPECIFICATION = 0x00010005
+  OUTPUT_DIRECTORY = Build/CoffeelakeSiliconPkg
+  SUPPORTED_ARCHITECTURES = IA32|X64
+  BUILD_TARGETS = DEBUG|RELEASE
+  SKUID_IDENTIFIER = DEFAULT
+
+  DEFINE   PLATFORM_SI_PACKAGE= CoffeelakeSiliconPkg
+
+  #
+  # Definition for Build Flag
+  #
+  !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
+
+[LibraryClasses.common]
+  #
+  # Entry point
+  #
+
+PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.in
+f
+  PeimE

Re: [edk2-devel] [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D 
Subject: [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add 
CoffeelakeSiliconPkg maintainers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Signed-off-by: Michael Kubacki 
---
 Maintainers.txt | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Maintainers.txt b/Maintainers.txt index 876ae5612a..bc8cbd6458 
100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -125,9 +125,14 @@ Silicon/Intel/Vlv2DeviceRefCodePkg
 M: Zailiang Sun 
 M: Yi Qian 
 
+Silicon/Intel/CoffeelakeSiliconPkg
+M: Chasel Chiu 
+M: Michael Kubacki 
+M: Sai Chaganty 
+
 Silicon/Intel/KabylakeSiliconPkg
 M: Chasel Chiu 
-M: Michael A Kubacki 
+M: Michael Kubacki 
 M: Sai Chaganty 
 
 Silicon/Intel/LewisburgPkg
--
2.16.2.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM 
library instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH SMM library class instances.

* SmmSpiFlashCommonLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
 |  51 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
 | 196 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
   |  54 ++
 3 files changed, 301 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
new file mode 100644
index 00..abc919867c
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLi
+++ b/SmmSpiFlashCommonLib.inf
@@ -0,0 +1,51 @@
+## @file
+# SMM Library instance of Spi Flash Common Library Class # # Copyright 
+(c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+  INF_VERSION= 0x00010017
+  BASE_NAME  = SmmSpiFlashCommonLib
+  FILE_GUID  = 9632D96E-E849-4217-9217-DC500B8AAE47
+  VERSION_STRING = 1.0
+  MODULE_TYPE= DXE_SMM_DRIVER
+  LIBRARY_CLASS  = SpiFlashCommonLib|DXE_SMM_DRIVER
+  CONSTRUCTOR= SmmSpiFlashCommonLibConstructor
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+  PciLib
+  IoLib
+  MemoryAllocationLib
+  BaseLib
+  UefiLib
+  SmmServicesTableLib
+  BaseMemoryLib
+  DebugLib
+  MmPciLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+  gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress  ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+
+[Sources]
+  SpiFlashCommonSmmLib.c
+  SpiFlashCommon.c
+
+[Protocols]
+  gPchSmmSpiProtocolGuid## CONSUMES
+
+[Depex.X64.DXE_SMM_DRIVER]
+  gPchSmmSpiProtocolGuid
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
new file mode 100644
index 00..53711db632
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLi
+++ b/SpiFlashCommon.c
@@ -0,0 +1,196 @@
+/** @file
+  Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
+  for module use.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+PCH_SPI_PROTOCOL   *mSpiProtocol;
+
+//
+// FlashAreaBaseAddress and Size for boottime and runtime usage.
+//
+UINTN mFlashAreaBaseAddress = 0;
+UINTN mFlashAreaSize= 0;
+
+/**
+  Enable block protection on the Serial Flash device.
+
+  @retval EFI_SUCCESS   Opertion is successful.
+  @retval EFI_DEVICE_ERROR  If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Read NumBytes bytes of data from the address specified by
+  PAddress into Buffer.
+
+  @param[in]  Address   The starting physical address of the read.
+  @param[in,out]  NumBytes  On input, the number of bytes to read. On 
output, the number
+of bytes actually read.
+  @param[out] BufferThe destination data buffer for the read.
+
+  @retval EFI_SUCCESS   Opertion is successful.
+  @retval EFI_DEVICE_ERROR  If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+  IN UINTNAddress,
+  IN OUT UINT32   *NumBytes,
+ OUT UINT8*Buffer
+  )
+{
+  ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+  if ((NumBytes == NULL) || (Buffer == NULL)) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // This function is implemented specifically for those platforms  // 
+ at which the SPI device is memory mapped for read. So this  // 
+ function just do a memory copy for Spi Flash Read.
+  //
+  CopyMem (Buffer, (VOID *) Address, *NumBytes);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Write NumBytes bytes of data from Buffer to the address specified by
+ 

Re: [edk2-devel] [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM private library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM 
private library instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH SMM private library class instances.

* SmmPchPrivateLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.inf
 | 32 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.c
   | 58 
 2 files changed, 90 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.inf
new file mode 100644
index 00..5cbad21fa5
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPriva
+++ teLib/SmmPchPrivateLib.inf
@@ -0,0 +1,32 @@
+## @file
+#  PCH SMM private lib.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = SmmPchPrivateLib
+FILE_GUID = FE6495FB-7AA9-4A24-BF3E-4698F7BCE0EE
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_SMM_DRIVER
+LIBRARY_CLASS = SmmPchPrivateLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+CpuPlatformLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+SmmPchPrivateLib.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.c
new file mode 100644
index 00..85a3086874
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPriva
+++ teLib/SmmPchPrivateLib.c
@@ -0,0 +1,58 @@
+/** @file
+  PCH SMM private lib.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Set InSmm.Sts bit
+**/
+VOID
+PchSetInSmmSts (
+  VOID
+  )
+{
+  UINT32  Data32;
+
+  ///
+  /// Read memory location FED30880h OR with 0001h, place the 
+result in EAX,
+  /// and write data to lower 32 bits of MSR 1FEh (sample code 
+available)
+  ///
+  Data32 = MmioRead32 (0xFED30880);
+  AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE_ADDR, Data32 | BIT0);
+  ///
+  /// Read FED30880h back to ensure the setting went through.
+  ///
+  Data32 = MmioRead32 (0xFED30880);
+}
+
+/**
+  Clear InSmm.Sts bit
+**/
+VOID
+PchClearInSmmSts (
+  VOID
+  )
+{
+  UINT32  Data32;
+
+  ///
+  /// Read memory location FED30880h AND with FFFEh, place the 
+result in EAX,
+  /// and write data to lower 32 bits of MSR 1FEh (sample code 
+available)
+  ///
+  Data32 = MmioRead32 (0xFED30880);
+  AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE_ADDR, Data32 & (UINT32) 
+(~BIT0));
+  ///
+  /// Read FED30880h back to ensure the setting went through.
+  ///
+  Data32 = MmioRead32 (0xFED30880);
+}
--
2.16.2.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add 
Private/Library include headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/Private/Library

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNhlt.h 
  |  134 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHelpersLib.h 
 |   97 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioNameBufferLib.h
   |   25 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPrivateLib.h 
 | 1061 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMasterCommonLib.h
  |  288 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmiLib.h 
  |  344 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHdaLib.h 
  |   56 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchInitCommonLib.h
|  100 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPciExpressHelpersLib.h
 |  371 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsfPrivateLib.h
|  578 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmbusCommonLib.h
   |   98 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiCommonLib.h
 |  366 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPchDmiLib.h  
  |   25 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPrivateLib.h 
  |  706 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiScheduleResetLib.h
  |   48 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPchPrivateLib.h
|   28 +
 16 files changed, 4325 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNhlt.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNhlt.h
new file mode 100644
index 00..9d8e34eb0d
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNhlt.h
@@ -0,0 +1,134 @@
+/** @file
+  Header file for DxePchHdaLib - NHLT structure definitions.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_PCH_HDA_NHLT_H_
+#define _DXE_PCH_HDA_NHLT_H_
+
+#include 
+
+//
+// ACPI support protocol instance signature definition.
+//
+#define NHLT_ACPI_TABLE_SIGNATURE  SIGNATURE_32 ('N', 'H', 'L', 'T')
+
+// MSFT defined structures
+#define SPEAKER_FRONT_LEFT  0x1
+#define SPEAKER_FRONT_RIGHT 0x2
+#define SPEAKER_FRONT_CENTER0x4
+#define SPEAKER_BACK_LEFT   0x10
+#define SPEAKER_BACK_RIGHT  0x20
+
+#define KSAUDIO_SPEAKER_MONO   (SPEAKER_FRONT_CENTER)
+#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT)
+#define KSAUDIO_SPEAKER_QUAD   (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT | 
SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)
+
+#define WAVE_FORMAT_EXTENSIBLE0xFFFE /* Microsoft */
+#define KSDATAFORMAT_SUBTYPE_PCM \
+{0x0001, 0x, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 
0x9b, 0x71}}
+
+#pragma pack (push, 1)
+
+typedef struct {
+  UINT16  wFormatTag;
+  UINT16  nChannels;
+  UINT32  nSamplesPerSec;
+  UINT32  nAvgBytesPerSec;
+  UINT16  nBlockAlign;
+  UINT16  wBitsPerSample;
+  UINT16  cbSize;
+} WAVEFORMATEX;
+
+typedef struct {
+  WAVEFORMATEX Format;
+  union {
+UINT16 wValidBitsPerSample;
+UINT16 wSamplesPerBlock;
+UINT16 wReserved;
+  } Samples;
+  UINT32   dwChannelMask;
+  GUID SubFormat;
+} WAVEFORMATEXTENSIBLE;
+
+//
+// List of supported link type.
+//
+enum NHLT_LINK_TYPE
+{
+  HdaNhltLinkHd   = 0,
+  HdaNhltLinkDsp  = 1,
+  HdaNhltLinkDmic = 2,
+  HdaNhltLinkSsp  = 3,
+  HdaNhltLinkInvalid
+};
+
+//
+// List of supported device type.
+//
+enum NHLT_DEVICE_TYPE
+{
+  HdaNhltDeviceBt   = 0,
+  HdaNhltDeviceDmic = 1,
+  HdaNhltDeviceI2s  = 4,
+  HdaNhltDeviceInvalid
+};
+
+typedef struct {
+  UINT32CapabilitiesSize;
+  UINT8 Capabilities[1];
+} SPECIFIC_CONFIG;
+
+typedef struct {
+  WAVEFORMATEXTENSIBLE Format;
+  SPECIFIC_CONFIG  FormatConfiguration;
+} FORMAT_CONFIG;
+
+typedef struct {
+  UINT8   FormatsCount;
+  FORMAT_CONFIG   FormatsConfiguration[1];
+} FORMATS_CONFIG;
+
+typedef struct {
+  UINT8   DeviceId[16];
+  UINT8   Dev

Re: [edk2-devel] [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: Add library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: Add library 
instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds ME library class instances.

* PeiMePolicyLib - PEI ME policy configuration services.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.inf 
  |  44 
 
Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLibrary.h
 |  25 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c  
   | 251 
 3 files changed, 320 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.inf
new file mode 100644
index 00..85a227f950
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMe
+++ PolicyLib.inf
@@ -0,0 +1,44 @@
+## @file
+# Component description file for the PeiMePolicyLib libbrary.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiMePolicyLib
+FILE_GUID = 2655FA94-4559-F393-B0B1-85A8E79C1532
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = PeiMePolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiMePolicyLib.c
+PeiMePolicyLibrary.h
+
+
+[Ppis]
+gSiPolicyPpiGuid   ## PRODUCES
+gSiPreMemPolicyPpiGuid ## PRODUCES
+
+
+[Guids]
+gMePeiPreMemConfigGuid
+gMePeiConfigGuid
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLibrary.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLibrary.h
new file mode 100644
index 00..3ac6a639e9
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMe
+++ PolicyLibrary.h
@@ -0,0 +1,25 @@
+/** @file
+  Header file for the PeiMePolicy library.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_ME_POLICY_LIBRARY_H_
+#define _PEI_ME_POLICY_LIBRARY_H_
+
+#include 
+#include 
+#include 
+#include 
+#include  #include  
+#include  #include  #include 
+ #include  
+#include  #include 
+
+#endif // _PEI_ME_POLICY_LIBRARY_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
new file mode 100644
index 00..6f3d70b841
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMe
+++ PolicyLib.c
@@ -0,0 +1,251 @@
+/** @file
+  This file is PeiMePolicy library.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include "PeiMePolicyLibrary.h"
+
+/**
+  Load default settings for ME config block in pre-mem phase.
+
+  @param[in] ConfigBlockPointer The pointer to the config block
+**/
+VOID
+LoadMePeiPreMemDefault (
+  IN VOID   *ConfigBlockPointer
+  );
+
+/**
+  Load default settings for ME config block in PEI phase.
+
+  @param[in] ConfigBlockPointer The pointer to the config block
+**/
+VOID
+LoadMePeiDefault (
+  IN VOID   *ConfigBlockPointer
+  );
+
+STATIC COMPONENT_BLOCK_ENTRY  mMeCompontBlockPreMemBlocks [] = {
+  {&gMePeiPreMemConfigGuid, sizeof (ME_PEI_PREMEM_CONFIG),
+ME_PEI_PREMEM_CONFIG_REVISION,  LoadMePeiPreMemDefault} };
+
+STATIC COMPONENT_BLOCK_ENTRY  mMeCompontBlockBlocks [] = {
+  {&gMePeiConfigGuid,   sizeof (ME_PEI_CONFIG), 
ME_PEI_CONFIG_REVISION, LoadMePeiDefault}
+};
+
+/**
+  Load default settings for ME config block in pre-mem phase.
+
+  @param[in] ConfigBlockPointer The pointer to the config block
+**/
+VOID
+LoadMePeiPreMemDefault (
+  IN VOID   *ConfigBlockPointer
+  )
+{
+  ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig;
+  MePeiPreMemConfig = ConfigBlockPointer;
+
+  MePeiPreMemConfig->HeciTimeouts  = 1;
+
+  MePeiPreMemConfig->Heci1BarAddress   = 0xFED1A000;
+  MePeiPreMemConfig->Heci2BarAddress   = 0xFED1B000;
+  MePeiPreMemConfig->Heci3BarAddress   = 0xFED1C000;
+
+  //
+  // Test policies
+  //
+  MePeiPreMemConfig->SendDidMsg= 1;
+
+  MePeiPreMemConfig->KtDeviceEnable

Re: [edk2-devel] [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add library 
instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds CPU library class instances.

* BaseCpuMailboxLibNull - Generic CPU mailbox interaction services.
* PeiCpuPolicyLib - CPU policy configuration services.
* PeiCpuPolicyLibPreMem - CPU policy pre-memory configuration services.
* PeiDxeSmmCpuPlatformLib - CPU platform services.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf
 |  22 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf
 |  65 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibPreMem.inf
   |  43 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
 |  39 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h
   |  30 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h
|  28 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.c
   |  90 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPolicy.c 
   | 293 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPolicyPreMem.c
  | 108 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
   | 434 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibPreMem.c
 | 160 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
| 415 +++
 12 files changed, 1727 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf
new file mode 100644
index 00..4fcfca4670
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf
@@ -0,0 +1,22 @@
+## @file
+# Component description file for Cpu Mailbox Null Lib
+#
+# Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseCpuMailboxLibNull
+FILE_GUID = 74F470BC-1769-4732-B9C0-EE9AB0B12411
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuMailboxLib
+
+[Packages]
+MdePkg/MdePkg.dec
+
+[Sources]
+BaseCpuMailboxLibNull.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf
new file mode 100644
index 00..c986e35360
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf
@@ -0,0 +1,65 @@
+## @file
+# Component description file for the PeiCpuPolicyLib library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiCpuPolicyLib
+FILE_GUID = 5baafc8f-25c6-4d19-b141-585757509372
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = CpuPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+CpuPlatformLib
+PciSegmentLib
+SaPlatformLib
+SiConfigBlockLib
+PostCodeLib
+PcdLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiCpuPolicyLib.c
+PeiCpuPolicyLibrary.h
+CpuPrintPolicy.c
+PeiCpuPolicyLibPreMem.c
+CpuPrintPolicyPreMem.c
+
+[Ppis]
+gSiPolicyPpiGuid## CONSUMES
+gSiPreMemPolicyPpiGuid  ## CONSUMES
+
+[FixedPcd]
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+
+[Pcd]
+gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode  ## Produces
+
+[Guids]
+gCpuConfigGuid  ## PRODUCES
+gCpuSgxConfigGuid   ## PRODUCES
+gCpuPowerMgmtBasicConfigGuid## PRODUCES
+gCpuPowerMgmtCustomConfigGuid   ## PRODUCES
+gCpuTestConfigGuid  ## PRODUCES
+gCpuPidTestConfigGuid   ## PRODUCES
+gCpuPowerMgmtTestConfigGuid ## PRODUCES
+gCpuConfigLibPreMemConfigGuid   ## PRODUCES
+gCpuSecurityPreMemConfigGuid## PRODUCES
+gCpuOverclock

Re: [edk2-devel] [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE 
private library instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH DXE private library class instances.

* DxeGpioNameBufferLib
* DxePchHdaLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
 |  32 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePchHdaLib.inf
 |  43 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c
  |  20 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaEndpoints.c
| 333 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaLib.c 
 | 886 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaNhltConfig.c
   | 439 ++
 6 files changed, 1753 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
new file mode 100644
index 00..0dc8f9749d
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Component description file for the DxeGpioMemLib
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeGpioNameBufferLib
+FILE_GUID = 16EC6AA8-81D5-4847-B6CB-662CDAB863F2
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+LIBRARY_CLASS = GpioNameBufferLib
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+BaseLib
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+GpioNameBufferDxe.c
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePchHdaLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePchHdaLib.inf
new file mode 100644
index 00..a8a3f60b53
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePchHdaLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Component information file for PCH HD Audio Library
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxePchHdaLib
+FILE_GUID = DA915B7F-EE08-4C1D-B3D0-DE7C52AB155A
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchHdaLib
+
+
+[LibraryClasses]
+BaseLib
+DebugLib
+MemoryAllocationLib
+BaseMemoryLib
+PchInfoLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+
+
+[Sources]
+PchHdaLib.c
+PchHdaEndpoints.c
+PchHdaNhltConfig.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c
new file mode 100644
index 00..af53387faf
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c
@@ -0,0 +1,20 @@
+/** @file
+  This file contains implementation of the GpioMemLib for DXE phase
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+
+STATIC CHAR8 mGpioNameBuffer[GPIO_NAME_LENGTH_MAX];
+
+CHAR8*
+GpioGetStaticNameBuffer (
+  VOID
+  )
+{
+  return mGpioNameBuffer;
+}
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaEndpoints.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaEndpoints.c
new file mode 100644
index 00..ea04512501
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaEndpoints.c
@@ -0,0 +1,333 @@
+/** @file
+  This file contains HD Audio NHLT Endpoints definitions
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+

Re: [edk2-devel] [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base 
library instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds Pch/Library/Private Base library class instances.

* BaseGpioHelpersLibNull
* BasePchSpiCommonlib
* BaseSiScheduleResetLib
* BaseSiScheduleResetLibFsp

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
 |   26 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
   |   28 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
 |   40 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibFsp.inf
  |   40 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
   |  108 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/SpiCommon.c
   | 1081 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
   |   70 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibCommon.c
 |  125 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibFsp.c
|   61 ++
 9 files changed, 1579 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
new file mode 100644
index 00..5502af824f
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
@@ -0,0 +1,26 @@
+## @file
+# Component description file for the NULL GpioHelpersLib
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseGpioHelpersLib
+FILE_GUID = AB282608-2A50-4AE3-9242-64064ECF40D4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioHelpersLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseGpioHelpersLibNull.c
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
new file mode 100644
index 00..ea23e628c8
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
@@ -0,0 +1,28 @@
+## @file
+#  Component description file for the PchSpiCommonLib
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = BasePchSpiCommonLib
+  FILE_GUID  = A37CB67E-7D85-45B3-B07E-BF65BDB603E8
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PchSpiCommonLib
+
+[Sources]
+  SpiCommon.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+  IoLib
+  DebugLib
+  PmcLib
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
new file mode 100644
index 00..de7f6eeb73
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
@@ -0,0 +1,40 @@
+## @file
+# Component description file for Si Reset Schedule Library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseSiScheduleResetLib
+FILE_GUID = E6F3D551-36C0-4737-80C7-47FC57593163
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SiScheduleResetLib
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+HobLib
+ResetSystemLib
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Guids]
+gSiScheduleResetHobGuid
+gPchConfigHobGuid
+
+[S

Re: [edk2-devel] [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE 
library instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH DXE library class instances.

* DxePchPolicyLib
* DxeResetSystemLib
* DxeRuntimeResetSystemLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf
   |  41 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.inf
   |  49 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
 |  52 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.c
 | 218 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.c
 | 310 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.c
   | 323 
 6 files changed, 993 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf
new file mode 100644
index 00..8845ab796c
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/Dxe
+++ PchPolicyLib.inf
@@ -0,0 +1,41 @@
+## @file
+# Component description file for the PeiPchPolicy library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxePchPolicyLib
+FILE_GUID = E2179D04-7026-48A5-9475-309CEA2F21A3
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxePchPolicyLib
+
+
+[LibraryClasses]
+BaseMemoryLib
+UefiBootServicesTableLib
+DebugLib
+ConfigBlockLib
+SiConfigBlockLib
+PchInfoLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+DxePchPolicyLib.c
+
+
+[Guids]
+gHdAudioDxeConfigGuid
+gGpioDxeConfigGuid
+
+[Protocols]
+gPchPolicyProtocolGuid ## PRODUCES
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.inf
new file mode 100644
index 00..0bb2d6e247
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/D
+++ xeResetSystemLib.inf
@@ -0,0 +1,49 @@
+## @file
+# Component description file for Intel Ich7 Reset System Library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeResetSystemLib
+FILE_GUID = 239383BC-499E-4DC5-8CDC-F85AF27B1BC4
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = ResetSystemLib
+CONSTRUCTOR = DxeResetSystemLibConstructor # # The following 
+information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+TimerLib
+BaseMemoryLib
+UefiBootServicesTableLib
+PmcLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+DxeResetSystemLib.c
+
+
+[Protocols]
+gPchResetCallbackProtocolGuid ## CONSUMES
+
+
+[Guids]
+gPchGlobalResetGuid
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
new file mode 100644
index 00..a1777293ab
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSyst
+++ emLib/DxeRuntimeResetSystemLib.inf
@@ -0,0 +1,52 @@
+## @file
+# Component description file for Intel Ich7 Reset System Library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeRuntimeResetSystemLib
+FILE_GUID = 1026813A-E46F-43D1-B709-FF1F996F2E72
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_RUNTIME_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = ResetSystemLib
+CONSTRUCTOR = DxeRuntimeResetSystemLibConstructor
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+TimerLib
+BaseMemoryLib
+UefiRuntimeLib
+DxeServicesTableLib
+UefiBootServicesTableLib
+PmcLib
+
+
+[Packages]
+MdePkg

Re: [edk2-devel] [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base 
library instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH Base library class instances.

* BaseResetSystemLib
* BaseSmbusLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
 |  38 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf   
  |  39 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c
   | 153 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.c 
  | 993 
 4 files changed, 1223 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
new file mode 100644
index 00..8d68f2dd83
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/
+++ BaseResetSystemLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Component description file for Intel Ich7 Reset System Library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseResetSystemLib
+FILE_GUID = D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = ResetSystemLib
+CONSTRUCTOR = BaseResetSystemLibConstructor # # The following 
+information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+IoLib
+DebugLib
+PmcLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseResetSystemLib.c
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf
new file mode 100644
index 00..f3388a2624
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSm
+++ busLib.inf
@@ -0,0 +1,39 @@
+## @file
+# Component description file for PCH Smbus Library.
+#
+# SMBUS Library that layers on top of the I/O Library to directly # 
+access a standard SMBUS host controller.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved.  # # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseSmbusLib
+FILE_GUID = 5C4D0430-F81B-42D3-BB88-4A6CD2796FF8
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SmbusLib
+CONSTRUCTOR = BaseSmbusLibConstructor
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC #
+
+[LibraryClasses]
+BaseLib
+DebugLib
+IoLib
+PciSegmentLib
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseSmbusLib.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c
new file mode 100644
index 00..a603f5e794
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/
+++ BaseResetSystemLib.c
@@ -0,0 +1,153 @@
+/** @file
+  System reset library services.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16   mBaseResetSystemABase;
+
+/**
+  Calling this function causes a system-wide reset. This sets
+  all circuitry within the system to its initial state. This type of 
+reset
+  is asynchronous to system operation and operates without regard to
+  cycle boundaries.
+
+  System reset should not return, if it returns, it means the system 
+does
+  not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+  VOID
+  )
+{
+  IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); }
+
+/**
+  Calling this function causes a system-wide initialization. The 
+processors
+  are set to their initial state, and pending cycles are not corrupted.
+
+  System reset should not return, if it returns, it means the system 
+does
+  not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+  VOID
+  )
+{
+  IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET); }
+
+/**
+  Calling this function causes the system to enter a power state 
+equivalent
+  to

Re: [edk2-devel] [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package 
common library instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds package-level library class instances.

* BaseConfigBlockLib - Library functions for config block management.
* BaseSiConfigBlockLib - Library functions for managing component
  config blocks.
* DxeAslUpdateLib - Services to update ACPI tables.
* PeiDxeSmmMmPciLib - Services to manage PCI Express addresses.
* PeiStallPpiLib - Installs an instance of EFI_PEI_STALL_PPI.
* PeiSiPolicyLib - Installs an instance of the Silicon Policy PPI.
  Prints the Silicon Policy PPI values when DEBUG prints are enabled.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
 |  29 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
 |  33 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf 
  |  40 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.inf
   |  30 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
   |  35 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiStallPpiLib.inf
  |  31 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf   
  |  51 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h 
  |  35 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
   | 146 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.c
   |  87 +
 Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.c   
  | 403 
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.c
 | 126 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
 |  32 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiStallPpiLib.c
|  78 
 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c 
  | 214 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
 | 122 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/SiPrintPolicy.c  
  |  36 ++
 17 files changed, 1528 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
new file mode 100644
index 00..a7def2481d
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
@@ -0,0 +1,29 @@
+## @file
+# Component INF file for the BaseConfigBlock library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseConfigBlockLib
+FILE_GUID = 1EC07EA8-7808-4e06-9D79-309AE331D2D5
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseConfigBlockLib.c
+
+[LibraryClasses]
+DebugLib
+BaseMemoryLib
+MemoryAllocationLib
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
new file mode 100644
index 00..b04dc3cfa4
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Component description file for the BaseSiConfigBlockLib library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseSiConfigBlockLib
+FILE_GUID = 6C068D0F-F48E-48CB-B369-433E507AF4A2
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SiConfigBlockLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseSiConfigBlockLib.c
+
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
new file mode 100644
index 00..658caccb43
--- /dev/null
+++ 
b/Silicon/Intel/Coffeelak

Re: [edk2-devel] [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private 
include headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/Private

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h |  
16 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h   | 
273 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoints.h| 
115 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h|  
92 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h  | 
269 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h  |  
58 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleResetHob.h |  
25 ++
 7 files changed, 848 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h
new file mode 100644
index 00..6c9d10e928
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h
@@ -0,0 +1,16 @@
+/** @file
+CnlPchLp Dx HSIO Header File
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CNL_PCH_LP_HSIO_DX_H_
+#define _CNL_PCH_LP_HSIO_DX_H_
+
+#define CNL_PCH_LP_HSIO_VER_DX   0x7
+
+
+extern UINT8  CnlPchLpChipsetInitTable_Dx[5072];
+extern UINT8  CnlPchLpChipsetInitTable_eDBC_Dx[4612];
+#endif //_CNL_PCH_LP_HSIO_DX_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h
new file mode 100644
index 00..5569da670d
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h
@@ -0,0 +1,273 @@
+/** @file
+  The GUID definition for PchConfigHob
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_CONFIG_HOB_H_
+#define _PCH_CONFIG_HOB_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+extern EFI_GUID gPchConfigHobGuid;
+
+#pragma pack (push,1)
+
+///
+/// This structure contains the HOB which are related to PCH general config.
+///
+typedef struct {
+  /**
+This member describes whether or not the Compatibility Revision ID (CRID) 
feature
+of PCH should be enabled. 0: Disable; 1: Enable
+  **/
+  UINT32Crid:  1;
+  UINT32RsvdBits0   : 31;   ///< Reserved bits
+  ///
+  ///
+} GENERAL_HOB;
+
+///
+/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable 
devices in the platform.
+///
+typedef struct {
+  UINT8   RsvdBytes[3];
+  UINT8   NumRsvdSmbusAddresses;///< The number of elements in the 
RsvdSmbusAddressTable.
+  /**
+Array of addresses reserved for non-ARP-capable SMBus devices.
+  **/
+  UINT8   RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
+} SMBUS_HOB;
+
+///
+/// The INTERRUPT describes interrupt settings for PCH HOB.
+///
+typedef struct {
+  UINT8NumOfDevIntConfig;  
 ///< Number of entries in DevIntConfig table
+  UINT8GpioIrqRoute;   
 ///< Interrupt routing for GPIO. Default is 14.
+  UINT8Rsvd0[2];   
 ///< Reserved bytes, align to multiple 4.
+  PCH_DEVICE_INTERRUPT_CONFIG  DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG];  
 ///< Array which stores PCH devices interrupts settings
+  UINT8PxRcConfig[PCH_MAX_PXRC_CONFIG];
 ///< PCI interrupt routing for 8259 PIC controller
+} INTERRUPT_HOB;
+
+///
+/// The CNVI_HOB block describes CNVi device.
+///
+typedef struct {
+  UINT32 Mode  :  1; ///< 0: Disabled, 1: 
Auto
+  UINT32 RsvdBits0 : 31;
+} CNVI_HOB;
+
+/**
+  The SERIAL_IO block provides the configurations to set the Serial IO 
controllers
+**/
+typedef struct {
+  /**
+   0: Disabled;
+  - Device is placed in D3
+  - Gpio configuration is skipped
+  - Device will be disabled in PSF
+  - !important! If given device is Function 0 and not all other LPSS 
functions on given device
+are disabled, then PSF disabling is skipped.
+  

Re: [edk2-devel] [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:15 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include 
headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files common to CPU modules.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h 
   |  45 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
 | 106 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclockingConfig.h
| 141 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h  
   |  54 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h
  | 179 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h
 |  78 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h
   | 149 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h 
   |  66 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h 
   |  16 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h 
   | 113 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h 
   |  88 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h   
   |  23 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h  
   | 100 
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h   
   | 261 
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h 
   |  90 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h
   | 118 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h  
   |  84 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h  
   | 123 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPolicyProtocol.h
   |  50 
 19 files changed, 1884 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
new file mode 100644
index 00..47a98131d0
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
@@ -0,0 +1,45 @@
+/** @file
+  CPU Config Block.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+#define CPU_CONFIG_REVISION 3
+
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  CPU Configuration Structure.
+
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Deprecate and move SkipMpInit to CpuConfigLibPreMemConfig.
+  Revision 3:
+  - Move DebugInterfaceEnable from CPU_TEST_CONFIG.
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
+  /**
+Enable or Disable Advanced Encryption Standard (AES) feature.
+For some countries, this should be disabled for legal reasons.
+-0: Disable
+- 1: Enable
+  **/
+  UINT32 AesEnable: 1;
+  UINT32 SkipMpInit   : 1;///< @deprecated since 
revision 2. For Fsp only, Silicon Initialization will skip MP Initialization 
(including BSP) if enabled. For non-FSP, this should always be 0.
+  UINT32 DebugInterfaceEnable : 1;///< Enable or Disable 
processor debug features; 0: Disable; 1: Enable.
+  UINT32 RsvdBits : 28;   ///< Reserved for future use
+  EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode 
patch that is suitable for this processor.
+} CPU_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_CONFIG_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
new file mode 100644
index 00..ce965a7510
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
@@ -0,0 +1,106 @@
+/** @file
+  CPU Security PreMemory Config Block.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+
+#define CP

Re: [edk2-devel] [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add 
Include headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files common to silicon Sample Code.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha >
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformLib.h 
|   82 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Guid/SmramMemoryReserve.h
  |   51 +
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Protocol/LegacyBios.h
  | 1513 
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Protocol/LegacyInterrupt.h
 |  118 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/AcpiS3Context.h
|   65 +
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/ConsoleOutDevice.h
 |   17 +
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/MemoryTypeInformation.h
|   30 +
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Library/ResetSystemLib.h
|   80 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/SmmAccess.h
 |  137 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/SmmControl.h
|   87 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Protocol/SmmVariable.h
  |   33 +
 11 files changed, 2213 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformLib.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformLib.h
new file mode 100644
index 00..829d1190fc
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformLib.h
@@ -0,0 +1,82 @@
+/** @file
+  Prototype of SEC Platform hook library.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef  _SEC_PLATFORM_LIB_H_
+#define  _SEC_PLATFORM_LIB_H_
+
+#include 
+#include 
+
+/**
+  A developer supplied function to perform platform specific operations.
+
+  It's a developer supplied function to perform any operations appropriate to a
+  given platform. It's invoked just before passing control to PEI core by SEC
+  core. Platform developer may modify the SecCoreData passed to PEI Core.
+  It returns a platform specific PPI list that platform wishes to pass to PEI 
core.
+  The Generic SEC core module will merge this list to join the final list 
passed to
+  PEI core.
+
+  @param  SecCoreData   The same parameter as passing to PEI core. It
+could be overridden by this function.
+
+  @return The platform specific PPI list to be passed to PEI core or
+  NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+  IN OUT   EFI_SEC_PEI_HAND_OFF*SecCoreData
+  );
+
+
+/**
+  This interface conveys state information out of the Security (SEC) phase 
into PEI.
+
+  @param  PeiServices   Pointer to the PEI Services Table.
+  @param  StructureSize Pointer to the variable describing size of 
the input buffer.
+  @param  PlatformInformationRecord Pointer to the 
EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+  @retval EFI_SUCCESS   The data was successfully returned.
+  @retval EFI_BUFFER_TOO_SMALL  The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+  IN CONST EFI_PEI_SERVICES **PeiServices,
+  IN OUT   UINT64   *StructureSize,
+ OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord
+  );
+
+/**
+  This interface conveys performance information out of the Security (SEC) 
phase into PEI.
+
+  This service is published by the SEC phase. The SEC phase handoff has an 
optional
+  EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed 
from SEC into the
+  PEI Foundation. As such, if the platform supports collecting performance 
data in SEC,
+  this information is encapsulated into the data structure abstracted by this 
service.
+  This information is collected for the boot-strap processor (BSP) on IA-32.
+
+  @param[in]  PeiServices  The pointer to the PEI Services Table.
+  @param[in]  This The pointer to this instance of the 
PEI_SEC_PERFORMANCE_PPI.
+  @param[out] Performance  The pointer to performance data collected in SEC 
phase.
+
+  @retval EFI_SUCCESS  The data was s

Re: [edk2-devel] [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and 
Protocol include headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/Ppi
 * Pch/Include/Protocol

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h  
  |  42 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h   
  |  27 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h   
  |  28 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h 
  | 186 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h   
  | 136 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h
  |  68 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h   
  | 146 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h   
  | 132 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h
  |  42 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h 
  |  42 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h   
  | 134 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h  
  |  67 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h
 |  67 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h
  | 152 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h 
  |  15 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h  
  | 295 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h  
  | 113 
 17 files changed, 1692 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h
new file mode 100644
index 00..840a2355f1
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h
@@ -0,0 +1,42 @@
+/** @file
+  PCH Reset PPI
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_RESET_PPI_H_
+#define _PCH_RESET_PPI_H_
+
+//
+// Member functions
+//
+/**
+  Execute call back function for Pch Reset.
+
+  @param[in] ResetTypeReset Types which includes GlobalReset.
+  @param[in] ResetTypeGuidPointer to an EFI_GUID, which is the Reset 
Type Guid.
+
+  @retval EFI_SUCCESS The callback function has been done 
successfully
+  @retval EFI_NOT_FOUND   Failed to find Pch Reset Callback ppi. Or, 
none of
+  callback ppi is installed.
+  @retval Others  Do not do any reset from PCH
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_RESET_CALLBACK) (
+  IN  EFI_RESET_TYPEResetType,
+  IN  EFI_GUID  *ResetTypeGuid
+  );
+
+/**
+  This ppi is used to execute PCH Reset from the host controller.
+  If drivers need to run their callback function right before issuing the PCH 
Reset,
+  they can install PCH Reset Callback PPI before PCH Reset PEI driver to 
achieve that.
+**/
+typedef struct {
+  PCH_RESET_CALLBACK  ResetCallback;
+} PCH_RESET_CALLBACK_PPI;
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h
new file mode 100644
index 00..d3ff152742
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h
@@ -0,0 +1,27 @@
+/** @file
+  This file defines the PCH SPI PPI which implements the
+  Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_SPI_PPI_H_
+#define _PCH_SPI_PPI_H_
+
+#include 
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID   gPchSpiPpiGuid;
+
+/**
+  Reuse the PCH_SPI_PROTOCOL definitions
+  This is possible becaues the PPI implementation does not rely on a 
PeiService pointer,
+  as it uses EDKII Glue Lib to do IO accesses
+**/
+typedef PCH_SPI_PROTOCOL PCH_SPI_PPI;
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h
new file mode 100644

Re: [edk2-devel] [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:15 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and 
Include headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Create the CoffeelakeSiliconPkg to provide an initial package for
silicon initialization code for Coffee Lake (CFL) and Whiskey Lake
(WHL) generation products.

* Major areas of functionality are categorized into CPU, Management
  Engine (ME), Platform Controller Hub (PCH), and System Agent
  subdirectories.
* Common libraries and headers are kept at the root of the package.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec  | 
714 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h  |  
53 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h |  
89 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h| 
291 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h | 
157 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h   |  
64 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h |  
28 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h | 
123 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h |  
58 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h  | 
110 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h  |  
22 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h   |  
34 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h | 
319 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h |  
29 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h  |  
26 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h   |  
71 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h|  
60 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h |  
55 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h  |  
19 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h   |  
65 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h |  
23 +
 21 files changed, 2410 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec 
b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
new file mode 100644
index 00..fa8c11e93d
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
@@ -0,0 +1,714 @@
+## @file
+# Component description file for the Silicon Reference Code.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME  = SiPkg
+PACKAGE_VERSION   = 0.1
+PACKAGE_GUID  = F245E276-44A0-46b3-AEB5-9898BBCF008D
+
+[Includes]
+  Include
+  SampleCode/Include
+  SampleCode/MdeModulePkg/Include
+  SampleCode/IntelFrameworkPkg/Include
+  #
+  # SystemAgent
+  #
+  SystemAgent/Include
+  SystemAgent/MemoryInit/Include
+  SystemAgent/AcpiTables
+  #
+  # Cpu
+  #
+  Cpu/Include
+  #
+  # Me
+  #
+  Me/Include
+  #
+  # Pch
+  #
+  Pch/Include
+
+[Guids.common.Private]
+  #
+  # PCH
+  #
+  gPchDeviceTableHobGuid   = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66, 
0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}
+  gPchConfigHobGuid= { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd9, 
0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}
+  gGpioLibUnlockHobGuid= { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6, 
0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
+  gSiScheduleResetHobGuid  = { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC1, 
0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }}
+
+[Guids]
+##
+## MdeModulePkg
+##
+gEfiMemoryTypeInformationGuid  =  {0x4c19049f, 0x4137, 0x4dd3, {0x9c, 0x10, 
0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}}
+gEfiCapsuleVendorGuid  =  {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36, 
0xec, 0xbd, 0x3c, 0x8b, 0xe2}}
+gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0x0, 
0x90, 0x27, 0x3f, 0xc1, 0x4d}}
+
+##
+## IntelFrameworkPkg
+##
+gEfiSmmPeiSmramMemoryReserveGuid =  {0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 
0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}}
+
+##
+## Common
+##
+## Include/ConfigBlock/SiConfig.h
+gSiConfigGuid = {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97, 
0x38, 0x59, 0xd8 }}
+gSiPkgTokenSpaceGuid  =  {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43, 0x66, 
0x99, 0xcb, 0xe4, 

Re: [edk2-devel] [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add Include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:15 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add Include 
headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files common to ME modules.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h | 124 
++  
Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyLib.h  |  59 
+++  Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyLib.h 
 |  87 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h   | 172 

 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h |  17 
++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h|  19 
+++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h   |  41 
+
 7 files changed, 519 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h
new file mode 100644
index 00..102fb43bd1
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiCon
+++ fig.h
@@ -0,0 +1,124 @@
+/** @file
+  ME config block for PEI phase
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _ME_PEI_CONFIG_H_
+#define _ME_PEI_CONFIG_H_
+
+#include 
+
+#define ME_PEI_PREMEM_CONFIG_REVISION 2 extern EFI_GUID 
+gMePeiPreMemConfigGuid;
+
+#ifndef PLATFORM_POR
+#define PLATFORM_POR  0
+#endif
+#ifndef FORCE_ENABLE
+#define FORCE_ENABLE  1
+#endif
+#ifndef FORCE_DISABLE
+#define FORCE_DISABLE 2
+#endif
+
+#pragma pack (push,1)
+
+/**
+  ME Pei Pre-Memory Configuration Structure.
+
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Change DidInitStat bit width.
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header; ///< Config Block Header
+  UINT32 HeciTimeouts : 1;  ///< 0: Disable; 1: 
Enable - HECI Send/Receive Timeouts.
+  /**
+(Test)
+0: Disabled
+   1: ME DID init stat 0 - Success
+   2: ME DID init stat 1 - No Memory in Channels
+   3: ME DID init stat 2 - Memory Init Error
+  **/
+  UINT32 DidInitStat  : 2;
+  /**
+(Test)
+0: Set to 0 to enable polling for CPU replacement
+   1: Set to 1 will disable polling for CPU replacement
+  **/
+  UINT32 DisableCpuReplacedPolling: 1;
+  UINT32 SendDidMsg   : 1;  ///< (Test) 0: Disable; 
1: Enable - Enable/Disable to send DID message.
+  /**
+(Test)
+0: Set to 0 to enable retry mechanism for HECI APIs
+   1: Set to 1 will disable retry mechanism for HECI APIs
+  **/
+  UINT32 DisableHeciRetry : 1;
+  /**
+(Test)
+0: ME BIOS will check each messages before sending
+   1: ME BIOS always sends messages without checking
+  **/
+  UINT32 DisableMessageCheck  : 1;
+  /**
+(Test)
+The SkipMbpHob policy determines whether ME BIOS Payload data will be 
requested during boot
+in a MBP message. If set to 1, BIOS will send the MBP message with SkipMbp 
flag
+set causing CSME to respond with MKHI header only and no MBP data
+0: ME BIOS will keep MBP and create HOB for MBP data
+   1: ME BIOS will skip MBP data
+  **/
+  UINT32 SkipMbpHob   : 1;
+  UINT32 HeciCommunication2   : 1;  ///< (Test) 0: 
Disable; 1: Enable - Enable/Disable HECI2.
+  UINT32 KtDeviceEnable   : 1;  ///< (Test) 0: Disable; 
1: Enable - Enable/Disable Kt Device.
+  UINT32 RsvdBits : 22; ///< Reserved for future use & 
Config block alignment
+  UINT32 Heci1BarAddress;   ///< HECI1 BAR address.
+  UINT32 Heci2BarAddress;   ///< HECI2 BAR address.
+  UINT32 Heci3BarAddress;   ///< HECI3 BAR address.
+} ME_PEI_PREMEM_CONFIG;
+#pragma pack (pop)
+
+
+#define ME_PEI_CONFIG_REVISION 2
+extern EFI_GUID gMePeiConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  ME Pei Post-Memory Configuration Structure.
+
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Add MctpBroadcastCycle test setting.
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header; ///< Config Block Header
+
+  UINT32 EndOfPostMessage : 2;  ///< 0: Disabled; 1: Send in 
PEI; 2: Send in DXE - Send EOP at specific phase.
+  /**
+HECI3 state from Mbp for reference in S3 path only
+0: Disabled; 1: Enabled
+  **/
+  UINT32 Heci3Enabled  

Re: [edk2-devel] [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add 
Private/Protocol include headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/Private/Protocol

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h | 
31   
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h | 
37 
 2 files changed, 68 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h
new file mode 100644
index 00..75003c82ad
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc
+++ hNvsArea.h
@@ -0,0 +1,31 @@
+/** @file
+  This file defines the PCH NVS Area Protocol.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_NVS_AREA_H_
+#define _PCH_NVS_AREA_H_
+
+//
+// PCH NVS Area definition
+//
+#include 
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchNvsAreaProtocolGuid;
+
+/**
+  This protocol is used to sync PCH information from POST to runtime ASL.
+  This protocol exposes the pointer of PCH NVS Area only. Please refer 
+to
+  ASL definition for PCH NVS AREA.
+**/
+typedef struct {
+  PCH_NVS_AREA  *Area;
+} PCH_NVS_AREA_PROTOCOL;
+
+#endif // _PCH_NVS_AREA_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h
new file mode 100644
index 00..2cd6b85d29
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc
+++ ieIoTrap.h
@@ -0,0 +1,37 @@
+/** @file
+  This file defines the PCH PCIE IoTrap Protocol.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PCIE_IOTRAP_H_
+#define _PCH_PCIE_IOTRAP_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID   gPchPcieIoTrapProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility // typedef struct 
+_PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL;
+
+///
+/// Pcie Trap valid types
+///
+typedef enum {
+  PciePmTrap,
+  PcieTrapTypeMaximum
+} PCH_PCIE_TRAP_TYPE;
+
+/**
+ This protocol is used to provide the IoTrap address to trigger PCH 
+PCIE call back events **/ struct _PCH_PCIE_IOTRAP_PROTOCOL {
+  UINT16  PcieTrapAddress;
+};
+
+#endif
--
2.16.2.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add 
ConfigBlock headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files to Pch/Include/ConfigBlock.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
|  69 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h 
|  56 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h 
|  43 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h
|  40 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h
 |  54 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevConfig.h 
|  39 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h 
| 178 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
|  57 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h
|  58 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h
|  66 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h   
|  58 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h  
|  68 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h 
|  57 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h 
|  35 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h
|  70 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h 
|  34 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h
|  49 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h  
|  71 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHubConfig.h 
|  36 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h  
| 429 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h  
| 311 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h
| 230 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h 
|  63 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h
|  96 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h   
|  43 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h   
|  52 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h 
| 139 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h
|  33 ++
 28 files changed, 2534 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
new file mode 100644
index 00..35fa125ba3
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
@@ -0,0 +1,69 @@
+/** @file
+  CNVI policy
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CNVI_CONFIG_H_
+#define _CNVI_CONFIG_H_
+
+#define CNVI_CONFIG_REVISION 2
+extern EFI_GUID gCnviConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  CNVi Mode options
+**/
+typedef enum {
+  CnviModeDisabled = 0,
+  CnviModeAuto
+} CNVI_MODE;
+
+/**
+  CNVi MfUart1 connection options
+**/
+typedef enum {
+  CnviMfUart1Ish = 0,
+  CnviMfUart1SerialIo,
+  CnviBtUart1ExtPads,
+  CnviBtUart1NotConnected
+} CNVI_MFUART1_TYPE;
+
+
+/**
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Remove BtInterface and BtUartType.
+
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
+  /**
+This option allows for automatic detection of Connectivity Solution.
+Auto Detection assumes that CNVi will be enabled when available;
+Disable allows for disabling CNVi.
+CnviModeDisabled = Disabled,
+CnviModeAuto = Auto Detection
+  **/
+  UINT32 Mode  :  1;
+  /**
+(Test) This option configures Uart type which connects to MfUart1
+For production configuration ISH is the default, for tests SerialIO Uart0 
or external pads can be used
+Use CNVI_MFUART1_TYPE enum for selection
+CnviMfUart1Is

Re: [edk2-devel] [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include 
headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds Pch/Include headers.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h   | 
135 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h   | 
326 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h | 
381 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h| 
340 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h | 
241 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h| 
200 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h|  
54 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h   |  
38 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h   |  
80 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h|  
53 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h  |  
47 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h  |  
47 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h|  
59 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResources.h |  
53 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h |  
23 ++
 15 files changed, 2077 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h
new file mode 100644
index 00..91222fd54d
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h
@@ -0,0 +1,135 @@
+/** @file
+  Header file for DxePchHdaNhltLib - NHLT structure definitions.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_HDA_NHLT_H_
+#define _DXE_HDA_NHLT_H_
+
+#include 
+
+//
+// ACPI support protocol instance signature definition.
+//
+#define NHLT_ACPI_TABLE_SIGNATURE  SIGNATURE_32 ('N', 'H', 'L', 'T')
+
+// MSFT defined structures
+#define SPEAKER_FRONT_LEFT  0x1
+#define SPEAKER_FRONT_RIGHT 0x2
+#define SPEAKER_FRONT_CENTER0x4
+#define SPEAKER_BACK_LEFT   0x10
+#define SPEAKER_BACK_RIGHT  0x20
+
+#define KSAUDIO_SPEAKER_MONO   (SPEAKER_FRONT_CENTER)
+#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT)
+#define KSAUDIO_SPEAKER_QUAD   (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT | 
SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)
+
+#define WAVE_FORMAT_EXTENSIBLE0xFFFE
+#define KSDATAFORMAT_SUBTYPE_PCM \
+{0x0001, 0x, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 
0x9b, 0x71}}
+
+#pragma pack (push, 1)
+
+typedef struct {
+  UINT16  wFormatTag;
+  UINT16  nChannels;
+  UINT32  nSamplesPerSec;
+  UINT32  nAvgBytesPerSec;
+  UINT16  nBlockAlign;
+  UINT16  wBitsPerSample;
+  UINT16  cbSize;
+} WAVEFORMATEX;
+
+typedef struct {
+  WAVEFORMATEX Format;
+  union {
+UINT16 wValidBitsPerSample;
+UINT16 wSamplesPerBlock;
+UINT16 wReserved;
+  } Samples;
+  UINT32   dwChannelMask;
+  GUID SubFormat;
+} WAVEFORMATEXTENSIBLE;
+
+//
+// List of supported link type.
+//
+enum NHLT_LINK_TYPE
+{
+  HdaNhltLinkHd   = 0,
+  HdaNhltLinkDsp  = 1,
+  HdaNhltLinkDmic = 2,
+  HdaNhltLinkSsp  = 3,
+  HdaNhltLinkInvalid
+};
+
+//
+// List of supported device type.
+//
+enum NHLT_DEVICE_TYPE
+{
+  HdaNhltDeviceBt   = 0,
+  HdaNhltDeviceDmic = 1,
+  HdaNhltDeviceI2s  = 4,
+  HdaNhltDeviceInvalid
+};
+
+typedef struct {
+  UINT32CapabilitiesSize;
+  UINT8 Capabilities[1];
+} SPECIFIC_CONFIG;
+
+typedef struct {
+  WAVEFORMATEXTENSIBLE Format;
+  SPECIFIC_CONFIG  FormatConfiguration;
+} FORMAT_CONFIG;
+
+typedef struct {
+  UINT8   FormatsCount;
+  FORMAT_CONFIG   FormatsConfiguration[1];
+} FORMATS_CONFIG;
+
+typedef struct {
+  UINT8   DeviceId[16];
+  UINT8   DeviceInstanceId;
+  UINT8   DevicePortId;
+} DEVICE_INFO;
+
+typedef struct {
+  UINT8   DeviceInfoCount;
+  DEVICE_INFO DeviceInformation[1];
+} DEVICES_INFO;
+
+typedef struct {
+  UINT32  EndpointDescriptorLength;
+  UINT8   LinkType;
+  UINT8   InstanceId;
+  UINT16  HwVendorId;
+  UINT16  HwDeviceId;
+  UINT16  HwRevisionId;
+  UINT32  HwSubsystemId;
+  UINT8   DeviceTyp

Re: [edk2-devel] [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Gao, Liming ; Kinney, 
Michael D ; Sinha, Ankit 
Subject: [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library 
include headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/library

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h | 
 27 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h | 
 24 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h | 
 58 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h   | 
265 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h | 
788 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h   | 
166 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h| 
 33 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h | 
371 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h  | 
141 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h   | 
 36 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h  | 
109 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h  | 
407 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h| 
105 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h   | 
226 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h   | 
 45 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h| 
114 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h | 
 24 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h | 
116 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h  | 
240 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h  | 
111 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h| 
 23 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h | 
121 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h  | 
207 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h | 
 76 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h   | 
 22 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h   | 
 98 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h  | 
 23 +
 27 files changed, 3976 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
new file mode 100644
index 00..ee77334ecb
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
@@ -0,0 +1,27 @@
+/** @file
+  Header file for BiosLockLib.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BIOSLOCK_LIB_H_
+#define _BIOSLOCK_LIB_H_
+
+/**
+  Enable BIOS lock. This will set the LE (Lock Enable) and EISS (Enable In 
SMM.STS).
+  When this is set, attempts to write the WPD (Write Protect Disable) bit in 
PCH
+  will cause a SMI which will allow the BIOS to verify that the write is from 
a valid source.
+
+  Bios should always enable LockDownConfig.BiosLock policy to set Bios Lock 
bit in FRC.
+  If capsule udpate is enabled, it's expected to not do BiosLock by setting 
BiosLock policy disable
+  so it can udpate BIOS region.
+  After flash update, it should utilize this lib to do BiosLock for security.
+**/
+VOID
+BiosLockEnable (
+  VOID
+  );
+
+#endif // _BIOSLOCK_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
new file mode 100644
index 00..f406e0d929
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
@@ -0,0 +1,24 @@
+/** @file
+  Header file for CnviLib.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CNVI_LIB_H_
+#define _CNVI_LIB_H_
+
+/**
+  Check if CNVi is present.
+
+  @retval TRUECNVi is enabled
+  @retval FALSE   CNVi is disabled
+
+**/
+BOOLEAN
+CnviIsPresent (
+  VOID
+  );
+
+#endif // _CNVI_LIB_H_
diff --git 
a/S

Re: [edk2-devel] CPU hotplug using SMM with QEMU+OVMF

[Yao, Jiewen]

> -Original Message-
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Saturday, August 17, 2019 6:20 AM
> To: Laszlo Ersek 
> Cc: Yao, Jiewen ; Paolo Bonzini
> ; devel@edk2.groups.io; edk2-rfc-groups-io
> ; qemu devel list ; Igor
> Mammedov ; Chen, Yingwen
> ; Nakajima, Jun ; Boris
> Ostrovsky ; Joao Marcal Lemos Martins
> ; Phillip Goerl 
> Subject: Re: [edk2-devel] CPU hotplug using SMM with QEMU+OVMF
> 
> On Fri, 16 Aug 2019 22:15:15 +0200
> Laszlo Ersek  wrote:
> 
> > +Alex (direct question at the bottom)
> >
> > On 08/16/19 09:49, Yao, Jiewen wrote:
> > > below
> > >
> > >> -Original Message-
> > >> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> > >> Sent: Friday, August 16, 2019 3:20 PM
> > >> To: Yao, Jiewen ; Laszlo Ersek
> > >> ; devel@edk2.groups.io
> > >> Cc: edk2-rfc-groups-io ; qemu devel list
> > >> ; Igor Mammedov
> ;
> > >> Chen, Yingwen ; Nakajima, Jun
> > >> ; Boris Ostrovsky
> ;
> > >> Joao Marcal Lemos Martins ; Phillip
> Goerl
> > >> 
> > >> Subject: Re: [edk2-devel] CPU hotplug using SMM with QEMU+OVMF
> > >>
> > >> On 16/08/19 04:46, Yao, Jiewen wrote:
> > >>> Comment below:
> > >>>
> > >>>
> >  -Original Message-
> >  From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> >  Sent: Friday, August 16, 2019 12:21 AM
> >  To: Laszlo Ersek ; devel@edk2.groups.io; Yao,
> > >> Jiewen
> >  
> >  Cc: edk2-rfc-groups-io ; qemu devel list
> >  ; Igor Mammedov
> > >> ;
> >  Chen, Yingwen ; Nakajima, Jun
> >  ; Boris Ostrovsky
> > >> ;
> >  Joao Marcal Lemos Martins ; Phillip
> Goerl
> >  
> >  Subject: Re: [edk2-devel] CPU hotplug using SMM with QEMU+OVMF
> > 
> >  On 15/08/19 17:00, Laszlo Ersek wrote:
> > > On 08/14/19 16:04, Paolo Bonzini wrote:
> > >> On 14/08/19 15:20, Yao, Jiewen wrote:
> >  - Does this part require a new branch somewhere in the OVMF
> SEC
> >  code?
> >    How do we determine whether the CPU executing SEC is BSP
> or
> >    hot-plugged AP?
> > >>> [Jiewen] I think this is blocked from hardware perspective, since
> the
> > >> first
> >  instruction.
> > >>> There are some hardware specific registers can be used to
> determine
> > >> if
> >  the CPU is new added.
> > >>> I don’t think this must be same as the real hardware.
> > >>> You are free to invent some registers in device model to be used
> in
> >  OVMF hot plug driver.
> > >>
> > >> Yes, this would be a new operation mode for QEMU, that only
> applies
> > >> to
> > >> hot-plugged CPUs.  In this mode the AP doesn't reply to INIT or
> SMI,
> > >> in
> > >> fact it doesn't reply to anything at all.
> > >>
> >  - How do we tell the hot-plugged AP where to start execution?
> (I.e.
> >  that
> >    it should execute code at a particular pflash location.)
> > >>> [Jiewen] Same real mode reset vector at :FFF0.
> > >>
> > >> You do not need a reset vector or INIT/SIPI/SIPI sequence at all in
> > >> QEMU.  The AP does not start execution at all when it is
> unplugged,
> > >> so
> > >> no cache-as-RAM etc.
> > >>
> > >> We only need to modify QEMU so that hot-plugged APIs do not
> reply
> > >> to
> > >> INIT/SIPI/SMI.
> > >>
> > >>> I don’t think there is problem for real hardware, who always has
> CAR.
> > >>> Can QEMU provide some CPU specific space, such as MMIO
> region?
> > >>
> > >> Why is a CPU-specific region needed if every other processor is in
> SMM
> > >> and thus trusted.
> > >
> > > I was going through the steps Jiewen and Yingwen recommended.
> > >
> > > In step (02), the new CPU is expected to set up RAM access. In step
> > > (03), the new CPU, executing code from flash, is expected to "send
> > >> board
> > > message to tell host CPU (GPIO->SCI) -- I am waiting for hot-add
> > > message." For that action, the new CPU may need a stack
> (minimally if
> > >> we
> > > want to use C function calls).
> > >
> > > Until step (03), there had been no word about any other (=
> pre-plugged)
> > > CPUs (more precisely, Jiewen even confirmed "No impact to other
> > > processors"), so I didn't assume that other CPUs had entered SMM.
> > >
> > > Paolo, I've attempted to read Jiewen's response, and yours, as
> carefully
> > > as I can. I'm still very confused. If you have a better understanding,
> > > could you please write up the 15-step process from the thread
> starter
> > > again, with all QEMU customizations applied? Such as, unnecessary
> > >> steps
> > > removed, and platform specifics filled in.
> > 
> >  Sure.
> > 
> >  (01a) QEMU: create new CPU.  The CPU already exists, but it does
> not
> >   start running code until unparked by the CPU hotplug
> controller.
> > 
> >  (01b) QEMU: trigger SCI
> > 
> >  (02-03) no equivalent
> > 
> >  (0

[edk2-devel] [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083

* Adds the WhiskeylakeURvp board as a build option in build.cfg so it
  it is listed as a valid build target.
* Updates relevant Readme.md files to include instructions for
  WhiskeylakeOpenBoardPkg.
* Adds the maintainers for WhiskeylakeOpenBoardPkg to maintainers.txt.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Liming Gao 
Cc: Nate DeSimone 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Maintainers.txt  |  5 +++
 Platform/Intel/Readme.md | 44 +---
 Platform/Intel/build.cfg |  4 +-
 Readme.md|  1 +
 4 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index bc8cbd6458..b16432bf87 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -98,6 +98,11 @@ M: Shifei A Lu 
 M: Xiaohu Zhou 
 M: Isaac W Oram 
 
+Platform/Intel/WhiskeylakeOpenBoardPkg
+M: Chasel Chiu 
+M: Michael Kubacki 
+M: Nate DeSimone 
+
 Platform/Intel/Tools
 M: Bob Feng 
 M: Liming Gao 
diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 00f42985a2..aaf6ef4d3e 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -53,9 +53,10 @@ A UEFI firmware implementation using MinPlatformPkg is 
constructed using the fol
 
 
 ## Board Support
+* The `ClevoOpenBoardPkg` contains board implementations for Clevo systems.
 * The `KabylakeOpenBoardPkg` contains board implementations for Kaby Lake 
systems.
 * The `PurleyOpenBoardPkg` contains board implementations for Purley systems.
-* The `ClevoOpenBoardPkg` contains board implementations for Clevo systems.
+* The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey 
Lake systems.
 
 ## Board Package Organization
 The board package follows the standard EDK II package structure with the 
following additional elements and guidelines:
@@ -189,7 +190,12 @@ return back to the minimum platform caller.
   |   |||---build_config.cfg: 
BoardMtOlympus specific
   |   ||| build 
settings, environment variables.
   |   |||---build_board.py: Optional 
board-specific pre-build,
-  |   |||   build, 
post-build and clean functions.
+  |   ||build, 
post-build and clean functions.
+  |   ||
+  |   ||--WhiskeylakeOpenBoardPkg
+  |   |||--WhiskeylakeURvp
+  |   |||---build_config.cfg: 
WhiskeylakeURvp specific build
+  |   ||  settings 
environment variables.
   |--FSP
   
 
@@ -222,19 +228,6 @@ Users can also flash the UEFI firmware image to the 
highest area of the flash re
 
 ### **Known limitations**
 
-**KabylakeOpenBoardPkg**
-1. This firmware project has only been tested on the Intel KabylakeRvp3 board.
-2. This firmware project has only been tested booting to Microsoft Windows 10 
x64 with AHCI mode and Integrated Graphic
-  Device.
-3. The Windows build was tested on Windows 10 with Microsoft Visual Studio 
2015.
-4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
-5. The build was tested with NASM version 2.11.08.
-
-**PurleyOpenBoardPkg**
-1. This firmware project has only been tested on the Microsoft MtOlympus board.
-2. This firmware project has only been tested booting to Microsoft Windows 
Server 2016 with NVME on M.2 slot.
-3. This firmware project build has only been tested using the Microsoft Visual 
Studio 2015 compiler.
-
 **ClevoOpenBoardPkg**
 1. Currently, support is only being added for the N1xxWU series of boards.
 2. The Windows build was tested on Windows 10 with Microsoft Visual Studio 
2015 compiler.
@@ -244,6 +237,27 @@ Users can also flash the UEFI firmware image to the 
highest area of the flash re
 6. The firmware project applies to all Clevo supported board configurations 
but is only being tested on System 76 Galago
   Pro devices.
 
+**KabylakeOpenBoardPkg**
+1. This firmware project has only been tested on the Intel KabylakeRvp3 board.
+2. This firmware project has only been tested booting to Microsoft Windows 10 
x64 with AHCI mode and Integrated Graphic
+  Device.
+3. The Windows build was tested on Windows 10 with Microsoft Visual Studio 
2015.
+4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
+5. The build was tested with NASM version 2.11.08.
+
+**PurleyOpenBoardPkg**
+1. This firmware project has only been tested on the Microsoft MtOlympus board.
+2. This firmware project has only been tested booting to Microsoft Windows 
Server 2016 with NVME on M.2 slot.
+3. This firmware project build has only been tested using the Microsoft Visual 
Studio 2015 compiler.
+
+**WhiskeylakeOpenBoardPkg**
+1. This firmware pr

[edk2-devel] [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Signed-off-by: Michael Kubacki 
---
 Maintainers.txt | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index 876ae5612a..bc8cbd6458 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -125,9 +125,14 @@ Silicon/Intel/Vlv2DeviceRefCodePkg
 M: Zailiang Sun 
 M: Yi Qian 
 
+Silicon/Intel/CoffeelakeSiliconPkg
+M: Chasel Chiu 
+M: Michael Kubacki 
+M: Sai Chaganty 
+
 Silicon/Intel/KabylakeSiliconPkg
 M: Chasel Chiu 
-M: Michael A Kubacki 
+M: Michael Kubacki 
 M: Sai Chaganty 
 
 Silicon/Intel/LewisburgPkg
-- 
2.16.2.windows.1


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[edk2-devel] [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH DXE library class instances.

* DxePchPolicyLib
* DxeResetSystemLib
* DxeRuntimeResetSystemLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf
   |  41 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.inf
   |  49 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
 |  52 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.c
 | 218 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.c
 | 310 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.c
   | 323 
 6 files changed, 993 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf
new file mode 100644
index 00..8845ab796c
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.inf
@@ -0,0 +1,41 @@
+## @file
+# Component description file for the PeiPchPolicy library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxePchPolicyLib
+FILE_GUID = E2179D04-7026-48A5-9475-309CEA2F21A3
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxePchPolicyLib
+
+
+[LibraryClasses]
+BaseMemoryLib
+UefiBootServicesTableLib
+DebugLib
+ConfigBlockLib
+SiConfigBlockLib
+PchInfoLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+DxePchPolicyLib.c
+
+
+[Guids]
+gHdAudioDxeConfigGuid
+gGpioDxeConfigGuid
+
+[Protocols]
+gPchPolicyProtocolGuid ## PRODUCES
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.inf
new file mode 100644
index 00..0bb2d6e247
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetSystemLib.inf
@@ -0,0 +1,49 @@
+## @file
+# Component description file for Intel Ich7 Reset System Library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeResetSystemLib
+FILE_GUID = 239383BC-499E-4DC5-8CDC-F85AF27B1BC4
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = ResetSystemLib
+CONSTRUCTOR = DxeResetSystemLibConstructor
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+TimerLib
+BaseMemoryLib
+UefiBootServicesTableLib
+PmcLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+DxeResetSystemLib.c
+
+
+[Protocols]
+gPchResetCallbackProtocolGuid ## CONSUMES
+
+
+[Guids]
+gPchGlobalResetGuid
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
new file mode 100644
index 00..a1777293ab
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
@@ -0,0 +1,52 @@
+## @file
+# Component description file for Intel Ich7 Reset System Library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeRuntimeResetSystemLib
+FILE_GUID = 1026813A-E46F-43D1-B709-FF1F996F2E72
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_RUNTIME_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = ResetSystemLib
+CONSTRUCTOR = DxeRuntimeResetSystemLibConstructor
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+TimerLib
+BaseMemoryLib
+UefiRuntimeLib
+DxeServicesTableLib
+UefiBootServicesTableLib
+PmcLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+DxeRuntimeResetSystemLib.c
+
+
+[Protocols]
+gPchResetCallbackProtocolGuid ## CONSUMES
+
+
+[Guids]
+gPchGlobalResetGuid
+gEfiEventVirtualAddressChangeGuid
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicyLib.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/D

[edk2-devel] [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM private library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH SMM private library class instances.

* SmmPchPrivateLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.inf
 | 32 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.c
   | 58 
 2 files changed, 90 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.inf
new file mode 100644
index 00..5cbad21fa5
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.inf
@@ -0,0 +1,32 @@
+## @file
+#  PCH SMM private lib.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = SmmPchPrivateLib
+FILE_GUID = FE6495FB-7AA9-4A24-BF3E-4698F7BCE0EE
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_SMM_DRIVER
+LIBRARY_CLASS = SmmPchPrivateLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+CpuPlatformLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+SmmPchPrivateLib.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.c
new file mode 100644
index 00..85a3086874
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/SmmPchPrivateLib.c
@@ -0,0 +1,58 @@
+/** @file
+  PCH SMM private lib.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Set InSmm.Sts bit
+**/
+VOID
+PchSetInSmmSts (
+  VOID
+  )
+{
+  UINT32  Data32;
+
+  ///
+  /// Read memory location FED30880h OR with 0001h, place the result in 
EAX,
+  /// and write data to lower 32 bits of MSR 1FEh (sample code available)
+  ///
+  Data32 = MmioRead32 (0xFED30880);
+  AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE_ADDR, Data32 | BIT0);
+  ///
+  /// Read FED30880h back to ensure the setting went through.
+  ///
+  Data32 = MmioRead32 (0xFED30880);
+}
+
+/**
+  Clear InSmm.Sts bit
+**/
+VOID
+PchClearInSmmSts (
+  VOID
+  )
+{
+  UINT32  Data32;
+
+  ///
+  /// Read memory location FED30880h AND with FFFEh, place the result in 
EAX,
+  /// and write data to lower 32 bits of MSR 1FEh (sample code available)
+  ///
+  Data32 = MmioRead32 (0xFED30880);
+  AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE_ADDR, Data32 & (UINT32) (~BIT0));
+  ///
+  /// Read FED30880h back to ensure the setting went through.
+  ///
+  Data32 = MmioRead32 (0xFED30880);
+}
-- 
2.16.2.windows.1


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[edk2-devel] [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083

Header files for the WhiskeylakeURvp board instance.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Liming Gao 
Cc: Nate DeSimone 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h
  | 131 
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h 
 |  40 ++
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
 | 105 
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformInfo.h  
  |  44 +++
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
   |  12 ++
 5 files changed, 332 insertions(+)

diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h
new file mode 100644
index 00..bd849b9ee2
--- /dev/null
+++ 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h
@@ -0,0 +1,131 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_HOOK_LIB_H_
+#define _PEI_PLATFORM_HOOK_LIB_H_
+
+#include 
+#include 
+#include 
+
+
+//EC Command to provide one byte of debug indication
+#define BSSB_DEBUG_INDICATION 0xAE
+/**
+  Configure EC for specific devices
+
+  @param[in] PchLan   - The PchLan of PCH_SETUP variable.
+  @param[in] BootMode - The current boot mode.
+**/
+VOID
+EcInit (
+  IN UINT8PchLan,
+  IN EFI_BOOT_MODEBootMode
+  );
+
+/**
+  Checks if Premium PMIC present
+
+  @retval  TRUE  if present
+  @retval  FALSE it discrete/other PMIC
+**/
+BOOLEAN
+IsPremiumPmicPresent (
+  VOID
+  );
+
+/**
+  Pmic Programming to supprort LPAL Feature
+
+  @retval NONE
+**/
+VOID
+PremiumPmicDisableSlpS0Voltage (
+  VOID
+  );
+
+/**
+Pmic Programming to supprort LPAL Feature
+  @retval NONE
+**/
+VOID
+PremiumPmicEnableSlpS0Voltage(
+  VOID
+  );
+
+/**
+  Do platform specific programming pre-memory. For example, EC init, Chipset 
programming
+
+  @retval  Status
+**/
+EFI_STATUS
+PlatformSpecificInitPreMem (
+  VOID
+  );
+
+/**
+  Do platform specific programming post-memory.
+
+  @retval  Status
+**/
+EFI_STATUS
+PlatformSpecificInit (
+  VOID
+  );
+
+/**
+  Configure GPIO and SIO Before Memory is ready.
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+  VOID
+  );
+
+/**
+  Configure GPIO and SIO
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInit (
+  VOID
+  );
+
+/**
+Voltage Margining Routine
+
+@retval  EFI_SUCCESS   Operation success
+**/
+EFI_STATUS
+VoltageMarginingRoutine(
+  VOID
+  );
+
+/**
+  Detect recovery mode
+
+  @retval  EFI_SUCCESS   System in Recovery Mode
+  @retval  EFI_UNSUPPORTED   System doesn't support Recovery Mode
+  @retval  EFI_NOT_FOUND System is not in Recovery Mode
+**/
+EFI_STATUS
+IsRecoveryMode (
+  VOID
+  );
+
+/**
+  Early board Configuration before Memory is ready.
+
+  @retval  EFI_SUCCESS  Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+  VOID
+  );
+#endif
+
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h
new file mode 100644
index 00..d65586dbb9
--- /dev/null
+++ 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h
@@ -0,0 +1,40 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED  1
+
+typedef struct {
+  UINT8   Register;
+  UINT32  Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+  PCH_GPIO_DEV Use_Sel;
+  PCH_GPIO_DEV Use_Sel2;
+  PCH_GPIO_DEV Use_Sel3;
+  PCH_GPIO_DEV Io_Sel;
+  PCH_GPIO_DEV Io_Sel2;
+  PCH_GPIO_DEV Io_Sel3;
+  PCH_GPIO_DEV Lvl;
+  PCH_GPIO_DEV Lvl2;
+  PCH_GPIO_DEV Lvl3;
+  PCH_GPIO_DEV Inv;
+  PCH_GPIO_DEV Blink;
+  PCH_GPIO_DEV Rst_Sel;
+  PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
+
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
new file mode 100644
index 00..44b4059f8e
--- /dev/null
+++ 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
@@ -0,0 +1,105 @@
+/** @file
+  Header file for Platform Boards Configurations.
+
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLA

[edk2-devel] [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/Private/Protocol

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h | 
31 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h | 
37 
 2 files changed, 68 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h
new file mode 100644
index 00..75003c82ad
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h
@@ -0,0 +1,31 @@
+/** @file
+  This file defines the PCH NVS Area Protocol.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_NVS_AREA_H_
+#define _PCH_NVS_AREA_H_
+
+//
+// PCH NVS Area definition
+//
+#include 
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchNvsAreaProtocolGuid;
+
+/**
+  This protocol is used to sync PCH information from POST to runtime ASL.
+  This protocol exposes the pointer of PCH NVS Area only. Please refer to
+  ASL definition for PCH NVS AREA.
+**/
+typedef struct {
+  PCH_NVS_AREA  *Area;
+} PCH_NVS_AREA_PROTOCOL;
+
+#endif // _PCH_NVS_AREA_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h
new file mode 100644
index 00..2cd6b85d29
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h
@@ -0,0 +1,37 @@
+/** @file
+  This file defines the PCH PCIE IoTrap Protocol.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_PCIE_IOTRAP_H_
+#define _PCH_PCIE_IOTRAP_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID   gPchPcieIoTrapProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL;
+
+///
+/// Pcie Trap valid types
+///
+typedef enum {
+  PciePmTrap,
+  PcieTrapTypeMaximum
+} PCH_PCIE_TRAP_TYPE;
+
+/**
+ This protocol is used to provide the IoTrap address to trigger PCH PCIE call 
back events
+**/
+struct _PCH_PCIE_IOTRAP_PROTOCOL {
+  UINT16  PcieTrapAddress;
+};
+
+#endif
-- 
2.16.2.windows.1


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[edk2-devel] [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083

Adds the DSC and build files necessary to build the
WhiskeylakeURvp board instance.

Key files
=
* build_config.cfg - Board-specific build configuration file.
* OpenBoardPkg.dsc - The WhiskeylakeURvp board description file.
* OpenBoardPkgConfig.dsc - Used for feature-related PCD
  customization.
* OpenBoardPkgPcd.dsc - Used for other PCD customization.
* OpenBoardPkg.fdf - The WhiskeylakeURvp board flash file.
* FlashMapInclude.fdf - The WhiskeylakeURvp board flash map.
* OpenBoardPkgBuildOption.dsc - Sets build options Based
  on PCD values.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Liming Gao 
Cc: Nate DeSimone 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
| 385 +++
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgBuildOption.dsc
 | 154 +
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgConfig.dsc  
| 128 
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc 
| 245 +++
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMapInclude.fdf
 |  49 ++
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
| 706 
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
|  33 +
 7 files changed, 1700 insertions(+)

diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
new file mode 100644
index 00..eea809140c
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
@@ -0,0 +1,385 @@
+## @file
+#  Platform description.
+#
+#
+#  Copyright (c) 2019, Intel Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  #
+  # Set platform specific package/folder name, same as passed from PREBUILD 
script.
+  # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package 
build folder
+  # DEFINE only takes effect at R9 DSC and FDF.
+  #
+  DEFINE  PLATFORM_PACKAGE  = MinPlatformPkg
+  DEFINE  PLATFORM_SI_PACKAGE   = CoffeelakeSiliconPkg
+  DEFINE  PLATFORM_SI_BIN_PACKAGE   = CoffeelakeSiliconBinPkg
+  DEFINE  PLATFORM_FSP_BIN_PACKAGE  = CoffeeLakeFspBinPkg
+  DEFINE  PLATFORM_BOARD_PACKAGE= WhiskeylakeOpenBoardPkg
+  DEFINE  BOARD = WhiskeylakeURvp
+  DEFINE  PROJECT   = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
+
+  #
+  # Platform On/Off features are defined here
+  #
+  !include OpenBoardPkgConfig.dsc
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME   = $(PLATFORM_PACKAGE)
+  PLATFORM_GUID   = 84D0F5BD-0EF3-4CC0-9B09-F2D0F2AA5C5E
+  PLATFORM_VERSION= 0.1
+  DSC_SPECIFICATION   = 0x00010005
+  OUTPUT_DIRECTORY= Build/$(PROJECT)
+  SUPPORTED_ARCHITECTURES = IA32|X64
+  BUILD_TARGETS   = DEBUG|RELEASE
+  SKUID_IDENTIFIER= ALL
+
+
+  FLASH_DEFINITION= $(PROJECT)/OpenBoardPkg.fdf
+
+  FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
+  DEFINE   TOP_MEMORY_ADDRESS = 0x0
+
+  #
+  # Default value for OpenBoardPkg.fdf use
+  #
+  DEFINE BIOS_SIZE_OPTION = SIZE_70
+
+
+#
+# SKU Identification section - list of all SKU IDs supported by this
+#  Platform.
+#
+
+[SkuIds]
+  0|DEFAULT  # The entry: 0|DEFAULT is reserved and always 
required.
+  0x60|WhiskeylakeURvp
+
+
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+
+
+  !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+  !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+  !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses.common]
+
+  PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
+  
ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf
+
+  
PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf
+  
PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+  
Pl

[edk2-devel] [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files common to silicon Sample Code.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha >
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformLib.h 
|   82 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Guid/SmramMemoryReserve.h
  |   51 +
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Protocol/LegacyBios.h
  | 1513 
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Protocol/LegacyInterrupt.h
 |  118 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/AcpiS3Context.h
|   65 +
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/ConsoleOutDevice.h
 |   17 +
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/MemoryTypeInformation.h
|   30 +
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Library/ResetSystemLib.h
|   80 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/SmmAccess.h
 |  137 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/SmmControl.h
|   87 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Protocol/SmmVariable.h
  |   33 +
 11 files changed, 2213 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformLib.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformLib.h
new file mode 100644
index 00..829d1190fc
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformLib.h
@@ -0,0 +1,82 @@
+/** @file
+  Prototype of SEC Platform hook library.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef  _SEC_PLATFORM_LIB_H_
+#define  _SEC_PLATFORM_LIB_H_
+
+#include 
+#include 
+
+/**
+  A developer supplied function to perform platform specific operations.
+
+  It's a developer supplied function to perform any operations appropriate to a
+  given platform. It's invoked just before passing control to PEI core by SEC
+  core. Platform developer may modify the SecCoreData passed to PEI Core.
+  It returns a platform specific PPI list that platform wishes to pass to PEI 
core.
+  The Generic SEC core module will merge this list to join the final list 
passed to
+  PEI core.
+
+  @param  SecCoreData   The same parameter as passing to PEI core. It
+could be overridden by this function.
+
+  @return The platform specific PPI list to be passed to PEI core or
+  NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+  IN OUT   EFI_SEC_PEI_HAND_OFF*SecCoreData
+  );
+
+
+/**
+  This interface conveys state information out of the Security (SEC) phase 
into PEI.
+
+  @param  PeiServices   Pointer to the PEI Services Table.
+  @param  StructureSize Pointer to the variable describing size of 
the input buffer.
+  @param  PlatformInformationRecord Pointer to the 
EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+  @retval EFI_SUCCESS   The data was successfully returned.
+  @retval EFI_BUFFER_TOO_SMALL  The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+  IN CONST EFI_PEI_SERVICES **PeiServices,
+  IN OUT   UINT64   *StructureSize,
+ OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord
+  );
+
+/**
+  This interface conveys performance information out of the Security (SEC) 
phase into PEI.
+
+  This service is published by the SEC phase. The SEC phase handoff has an 
optional
+  EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed 
from SEC into the
+  PEI Foundation. As such, if the platform supports collecting performance 
data in SEC,
+  this information is encapsulated into the data structure abstracted by this 
service.
+  This information is collected for the boot-strap processor (BSP) on IA-32.
+
+  @param[in]  PeiServices  The pointer to the PEI Services Table.
+  @param[in]  This The pointer to this instance of the 
PEI_SEC_PERFORMANCE_PPI.
+  @param[out] Performance  The pointer to performance data collected in SEC 
phase.
+
+  @retval EFI_SUCCESS  The data was successfully returned.
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+  IN CONST EFI_PEI_SERVICES  **PeiServices,
+  IN   PEI_SEC_PERFORMANCE_PPI   *This,
+  OUT  FIRMWARE_SEC_PERFORMANCE  *Performance
+  );
+
+#endif
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Guid/SmramMemoryReserve.h
 
b/Silicon/

[edk2-devel] [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: Add library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds ME library class instances.

* PeiMePolicyLib - PEI ME policy configuration services.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.inf 
  |  44 
 
Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLibrary.h
 |  25 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c  
   | 251 
 3 files changed, 320 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.inf
new file mode 100644
index 00..85a227f950
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.inf
@@ -0,0 +1,44 @@
+## @file
+# Component description file for the PeiMePolicyLib libbrary.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiMePolicyLib
+FILE_GUID = 2655FA94-4559-F393-B0B1-85A8E79C1532
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = PeiMePolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiMePolicyLib.c
+PeiMePolicyLibrary.h
+
+
+[Ppis]
+gSiPolicyPpiGuid   ## PRODUCES
+gSiPreMemPolicyPpiGuid ## PRODUCES
+
+
+[Guids]
+gMePeiPreMemConfigGuid
+gMePeiConfigGuid
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLibrary.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLibrary.h
new file mode 100644
index 00..3ac6a639e9
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLibrary.h
@@ -0,0 +1,25 @@
+/** @file
+  Header file for the PeiMePolicy library.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_ME_POLICY_LIBRARY_H_
+#define _PEI_ME_POLICY_LIBRARY_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#endif // _PEI_ME_POLICY_LIBRARY_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
new file mode 100644
index 00..6f3d70b841
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
@@ -0,0 +1,251 @@
+/** @file
+  This file is PeiMePolicy library.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiMePolicyLibrary.h"
+
+/**
+  Load default settings for ME config block in pre-mem phase.
+
+  @param[in] ConfigBlockPointer The pointer to the config block
+**/
+VOID
+LoadMePeiPreMemDefault (
+  IN VOID   *ConfigBlockPointer
+  );
+
+/**
+  Load default settings for ME config block in PEI phase.
+
+  @param[in] ConfigBlockPointer The pointer to the config block
+**/
+VOID
+LoadMePeiDefault (
+  IN VOID   *ConfigBlockPointer
+  );
+
+STATIC COMPONENT_BLOCK_ENTRY  mMeCompontBlockPreMemBlocks [] = {
+  {&gMePeiPreMemConfigGuid, sizeof (ME_PEI_PREMEM_CONFIG),  
ME_PEI_PREMEM_CONFIG_REVISION,  LoadMePeiPreMemDefault}
+};
+
+STATIC COMPONENT_BLOCK_ENTRY  mMeCompontBlockBlocks [] = {
+  {&gMePeiConfigGuid,   sizeof (ME_PEI_CONFIG), 
ME_PEI_CONFIG_REVISION, LoadMePeiDefault}
+};
+
+/**
+  Load default settings for ME config block in pre-mem phase.
+
+  @param[in] ConfigBlockPointer The pointer to the config block
+**/
+VOID
+LoadMePeiPreMemDefault (
+  IN VOID   *ConfigBlockPointer
+  )
+{
+  ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig;
+  MePeiPreMemConfig = ConfigBlockPointer;
+
+  MePeiPreMemConfig->HeciTimeouts  = 1;
+
+  MePeiPreMemConfig->Heci1BarAddress   = 0xFED1A000;
+  MePeiPreMemConfig->Heci2BarAddress   = 0xFED1B000;
+  MePeiPreMemConfig->Heci3BarAddress   = 0xFED1C000;
+
+  //
+  // Test policies
+  //
+  MePeiPreMemConfig->SendDidMsg= 1;
+
+  MePeiPreMemConfig->KtDeviceEnable= 1;
+}
+
+/**
+  Load default settings for ME config block in PEI phase.
+
+  @param[in] ConfigBlockPointer The pointer to the config block
+**/
+VOID
+LoadMePeiDefault (
+  IN VOID   *ConfigBlockPointer
+  )
+{
+  ME_PEI_CONFIG *MePeiConfig;
+  MePeiConfig = ConfigBlockPointer;
+
+  MePeiConfig->End

[edk2-devel] [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add Include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files common to ME modules.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h | 124 
++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyLib.h  |  59 
+++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyLib.h  |  87 
++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h   | 172 

 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h |  17 
++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h|  19 
+++
 Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h   |  41 
+
 7 files changed, 519 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h
new file mode 100644
index 00..102fb43bd1
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h
@@ -0,0 +1,124 @@
+/** @file
+  ME config block for PEI phase
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ME_PEI_CONFIG_H_
+#define _ME_PEI_CONFIG_H_
+
+#include 
+
+#define ME_PEI_PREMEM_CONFIG_REVISION 2
+extern EFI_GUID gMePeiPreMemConfigGuid;
+
+#ifndef PLATFORM_POR
+#define PLATFORM_POR  0
+#endif
+#ifndef FORCE_ENABLE
+#define FORCE_ENABLE  1
+#endif
+#ifndef FORCE_DISABLE
+#define FORCE_DISABLE 2
+#endif
+
+#pragma pack (push,1)
+
+/**
+  ME Pei Pre-Memory Configuration Structure.
+
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Change DidInitStat bit width.
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header; ///< Config Block Header
+  UINT32 HeciTimeouts : 1;  ///< 0: Disable; 1: 
Enable - HECI Send/Receive Timeouts.
+  /**
+(Test)
+0: Disabled
+   1: ME DID init stat 0 - Success
+   2: ME DID init stat 1 - No Memory in Channels
+   3: ME DID init stat 2 - Memory Init Error
+  **/
+  UINT32 DidInitStat  : 2;
+  /**
+(Test)
+0: Set to 0 to enable polling for CPU replacement
+   1: Set to 1 will disable polling for CPU replacement
+  **/
+  UINT32 DisableCpuReplacedPolling: 1;
+  UINT32 SendDidMsg   : 1;  ///< (Test) 0: Disable; 
1: Enable - Enable/Disable to send DID message.
+  /**
+(Test)
+0: Set to 0 to enable retry mechanism for HECI APIs
+   1: Set to 1 will disable retry mechanism for HECI APIs
+  **/
+  UINT32 DisableHeciRetry : 1;
+  /**
+(Test)
+0: ME BIOS will check each messages before sending
+   1: ME BIOS always sends messages without checking
+  **/
+  UINT32 DisableMessageCheck  : 1;
+  /**
+(Test)
+The SkipMbpHob policy determines whether ME BIOS Payload data will be 
requested during boot
+in a MBP message. If set to 1, BIOS will send the MBP message with SkipMbp 
flag
+set causing CSME to respond with MKHI header only and no MBP data
+0: ME BIOS will keep MBP and create HOB for MBP data
+   1: ME BIOS will skip MBP data
+  **/
+  UINT32 SkipMbpHob   : 1;
+  UINT32 HeciCommunication2   : 1;  ///< (Test) 0: 
Disable; 1: Enable - Enable/Disable HECI2.
+  UINT32 KtDeviceEnable   : 1;  ///< (Test) 0: Disable; 
1: Enable - Enable/Disable Kt Device.
+  UINT32 RsvdBits : 22; ///< Reserved for future use & 
Config block alignment
+  UINT32 Heci1BarAddress;   ///< HECI1 BAR address.
+  UINT32 Heci2BarAddress;   ///< HECI2 BAR address.
+  UINT32 Heci3BarAddress;   ///< HECI3 BAR address.
+} ME_PEI_PREMEM_CONFIG;
+#pragma pack (pop)
+
+
+#define ME_PEI_CONFIG_REVISION 2
+extern EFI_GUID gMePeiConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  ME Pei Post-Memory Configuration Structure.
+
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Add MctpBroadcastCycle test setting.
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header; ///< Config Block Header
+
+  UINT32 EndOfPostMessage : 2;  ///< 0: Disabled; 1: Send in 
PEI; 2: Send in DXE - Send EOP at specific phase.
+  /**
+HECI3 state from Mbp for reference in S3 path only
+0: Disabled; 1: Enabled
+  **/
+  UINT32 Heci3Enabled : 1;
+  UINT32 DisableD0I3SettingForHeci: 1;  ///< (Test) 0: 
Disable; 1: Enable - Enable/Disable D0i3 for HECI.
+  /**
+Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send 
MeUnconfigOnRtcClearDisable Msg with parameter 0.
+It will cause ME to unconfig if RTC is cleared.
+-0: Disable
+- 1: Enable
+-2

[edk2-devel] [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 215 

 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc | 130 
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc   |  69 +++
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc |  33 +++
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc  |  37 
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc |  21 ++
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc  |  44 
 7 files changed, 549 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc 
b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
new file mode 100644
index 00..37c77d8f63
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
@@ -0,0 +1,215 @@
+## @file
+#  Component description file for the Coffee Lake silicon package DSC file.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[PcdsFeatureFlag]
+gSiPkgTokenSpaceGuid.PcdTraceHubEnable   |FALSE
+gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdAtaEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdSiCsmEnable  |FALSE
+gSiPkgTokenSpaceGuid.PcdUseHpetTimer |TRUE
+gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE
+gSiPkgTokenSpaceGuid.PcdAcpiEnable   |FALSE
+gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdJhiEnable|FALSE
+gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE
+gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE
+gSiPkgTokenSpaceGuid.PcdOverclockEnable  |FALSE
+gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable   |FALSE
+gSiPkgTokenSpaceGuid.PcdBdatEnable   |TRUE
+gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdSaDmiEnable  |TRUE
+gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdSaOcEnable   |TRUE
+gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
+gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable   |TRUE
+gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE
+gSiPkgTokenSpaceGuid.PcdCflCpuEnable |FALSE
+gSiPkgTokenSpaceGuid.PcdOcWdtEnable  |TRUE
+gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable   |TRUE
+gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
+
+[PcdsFixedAtBuild.common]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress   |0xE000
+gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x1000
+
+  gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin|10
+  gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax|18
+
+[PcdsDynamicDefault.common]
+gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength  |0x1000
+
+## Specifies the AP wait loop state during POST phase.
+#  The value is defined as below.
+#  1: Place AP in the Hlt-Loop state.
+#  2: Place AP in the Mwait-Loop state.
+#  3: Place AP in the Run-Loop state.
+# @Prompt The AP wait loop state.
+gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+## Specifies the AP target C-state for Mwait during POST phase.
+#  The default value 0 means C1 state.
+#  The value is defined as below.
+# @Prompt The specified AP target C-state for Mwait.
+gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
+
+[Defines]
+  PLATFORM_NAME = CoffeelakeSiliconPkg
+  PLATFORM_GUID = A45CA44C-AB04-4932-A77C-5A7179F66A22
+  PLATFORM_VERSION = 0.4
+  DSC_SPECIFICATION = 0x00010005
+  OUTPUT_DIRECTORY = Build/CoffeelakeSiliconPkg
+  SUPPORTED_ARCHITECTURES = IA32|X64
+  BUILD_TARGETS = DEBUG|RELEASE
+  SKUID_IDENTIFIER = DEFAULT
+
+  DEFINE   PLATFORM_SI_PACKAGE= CoffeelakeSiliconPkg
+
+  #
+  # Definition for Build Flag
+  #
+  !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
+
+[LibraryClasses.common]
+  #
+  # Entry point
+  #
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  
PeCoffExtraActionLib|MdeP

[edk2-devel] [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH DXE private library class instances.

* DxeGpioNameBufferLib
* DxePchHdaLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
 |  32 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePchHdaLib.inf
 |  43 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c
  |  20 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaEndpoints.c
| 333 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaLib.c 
 | 886 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaNhltConfig.c
   | 439 ++
 6 files changed, 1753 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
new file mode 100644
index 00..0dc8f9749d
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Component description file for the DxeGpioMemLib
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeGpioNameBufferLib
+FILE_GUID = 16EC6AA8-81D5-4847-B6CB-662CDAB863F2
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+LIBRARY_CLASS = GpioNameBufferLib
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+BaseLib
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+GpioNameBufferDxe.c
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePchHdaLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePchHdaLib.inf
new file mode 100644
index 00..a8a3f60b53
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePchHdaLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Component information file for PCH HD Audio Library
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxePchHdaLib
+FILE_GUID = DA915B7F-EE08-4C1D-B3D0-DE7C52AB155A
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchHdaLib
+
+
+[LibraryClasses]
+BaseLib
+DebugLib
+MemoryAllocationLib
+BaseMemoryLib
+PchInfoLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+  gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+
+
+[Sources]
+PchHdaLib.c
+PchHdaEndpoints.c
+PchHdaNhltConfig.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c
new file mode 100644
index 00..af53387faf
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c
@@ -0,0 +1,20 @@
+/** @file
+  This file contains implementation of the GpioMemLib for DXE phase
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+
+STATIC CHAR8 mGpioNameBuffer[GPIO_NAME_LENGTH_MAX];
+
+CHAR8*
+GpioGetStaticNameBuffer (
+  VOID
+  )
+{
+  return mGpioNameBuffer;
+}
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaEndpoints.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaEndpoints.c
new file mode 100644
index 00..ea04512501
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHdaEndpoints.c
@@ -0,0 +1,333 @@
+/** @file
+  This file contains HD Audio NHLT Endpoints definitions
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CONST WAVEFORMATEXTENSIBLE Ch1_48kHz16bitFormat =
+{
+  {
+WAVE_FORMAT_EXTENSIBLE,
+1,
+48000,
+96000,
+2,
+16,
+sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX)
+  },
+  {16},
+  KSAUDIO_SPEAKER_MONO,
+  KSDATAFORMAT_SUBTYPE_PCM
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CONST WAVEFORMATEXTENSIBLE Ch2_48

[edk2-devel] [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files common to CPU modules.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h 
   |  45 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
 | 106 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclockingConfig.h
| 141 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h  
   |  54 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h
  | 179 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h
 |  78 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h
   | 149 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h 
   |  66 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h 
   |  16 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h 
   | 113 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h 
   |  88 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h   
   |  23 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h  
   | 100 
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h   
   | 261 
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h 
   |  90 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h
   | 118 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h  
   |  84 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h  
   | 123 +
 Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPolicyProtocol.h
   |  50 
 19 files changed, 1884 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
new file mode 100644
index 00..47a98131d0
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
@@ -0,0 +1,45 @@
+/** @file
+  CPU Config Block.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+#define CPU_CONFIG_REVISION 3
+
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  CPU Configuration Structure.
+
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Deprecate and move SkipMpInit to CpuConfigLibPreMemConfig.
+  Revision 3:
+  - Move DebugInterfaceEnable from CPU_TEST_CONFIG.
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
+  /**
+Enable or Disable Advanced Encryption Standard (AES) feature.
+For some countries, this should be disabled for legal reasons.
+-0: Disable
+- 1: Enable
+  **/
+  UINT32 AesEnable: 1;
+  UINT32 SkipMpInit   : 1;///< @deprecated since 
revision 2. For Fsp only, Silicon Initialization will skip MP Initialization 
(including BSP) if enabled. For non-FSP, this should always be 0.
+  UINT32 DebugInterfaceEnable : 1;///< Enable or Disable 
processor debug features; 0: Disable; 1: Enable.
+  UINT32 RsvdBits : 28;   ///< Reserved for future use
+  EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode 
patch that is suitable for this processor.
+} CPU_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_CONFIG_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
new file mode 100644
index 00..ce965a7510
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
@@ -0,0 +1,106 @@
+/** @file
+  CPU Security PreMemory Config Block.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+
+#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 5
+
+extern EFI_GUID gCpuConfigLibPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  CPU Config Library PreMemory Configuration Structure.
+
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Update for JTAG Power Gate comment.
+  Revision 3:
+  - Add PeciSxReset and PeciC10Reset
+  Revision 4:
+  - Add Ski

[edk2-devel] [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/Private

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h |  
16 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h   | 
273 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoints.h| 
115 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h|  
92 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h  | 
269 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h  |  
58 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleResetHob.h |  
25 ++
 7 files changed, 848 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h
new file mode 100644
index 00..6c9d10e928
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h
@@ -0,0 +1,16 @@
+/** @file
+CnlPchLp Dx HSIO Header File
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CNL_PCH_LP_HSIO_DX_H_
+#define _CNL_PCH_LP_HSIO_DX_H_
+
+#define CNL_PCH_LP_HSIO_VER_DX   0x7
+
+
+extern UINT8  CnlPchLpChipsetInitTable_Dx[5072];
+extern UINT8  CnlPchLpChipsetInitTable_eDBC_Dx[4612];
+#endif //_CNL_PCH_LP_HSIO_DX_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h
new file mode 100644
index 00..5569da670d
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h
@@ -0,0 +1,273 @@
+/** @file
+  The GUID definition for PchConfigHob
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_CONFIG_HOB_H_
+#define _PCH_CONFIG_HOB_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+extern EFI_GUID gPchConfigHobGuid;
+
+#pragma pack (push,1)
+
+///
+/// This structure contains the HOB which are related to PCH general config.
+///
+typedef struct {
+  /**
+This member describes whether or not the Compatibility Revision ID (CRID) 
feature
+of PCH should be enabled. 0: Disable; 1: Enable
+  **/
+  UINT32Crid:  1;
+  UINT32RsvdBits0   : 31;   ///< Reserved bits
+  ///
+  ///
+} GENERAL_HOB;
+
+///
+/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable 
devices in the platform.
+///
+typedef struct {
+  UINT8   RsvdBytes[3];
+  UINT8   NumRsvdSmbusAddresses;///< The number of elements in the 
RsvdSmbusAddressTable.
+  /**
+Array of addresses reserved for non-ARP-capable SMBus devices.
+  **/
+  UINT8   RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
+} SMBUS_HOB;
+
+///
+/// The INTERRUPT describes interrupt settings for PCH HOB.
+///
+typedef struct {
+  UINT8NumOfDevIntConfig;  
 ///< Number of entries in DevIntConfig table
+  UINT8GpioIrqRoute;   
 ///< Interrupt routing for GPIO. Default is 14.
+  UINT8Rsvd0[2];   
 ///< Reserved bytes, align to multiple 4.
+  PCH_DEVICE_INTERRUPT_CONFIG  DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG];  
 ///< Array which stores PCH devices interrupts settings
+  UINT8PxRcConfig[PCH_MAX_PXRC_CONFIG];
 ///< PCI interrupt routing for 8259 PIC controller
+} INTERRUPT_HOB;
+
+///
+/// The CNVI_HOB block describes CNVi device.
+///
+typedef struct {
+  UINT32 Mode  :  1; ///< 0: Disabled, 1: 
Auto
+  UINT32 RsvdBits0 : 31;
+} CNVI_HOB;
+
+/**
+  The SERIAL_IO block provides the configurations to set the Serial IO 
controllers
+**/
+typedef struct {
+  /**
+   0: Disabled;
+  - Device is placed in D3
+  - Gpio configuration is skipped
+  - Device will be disabled in PSF
+  - !important! If given device is Function 0 and not all other LPSS 
functions on given device
+are disabled, then PSF disabling is skipped.
+PSF default will remain and device PCI CFG Space will 
still be visible.
+This is needed to allow PCI enumerator access 
functions above 0 in a multifunction device.
+1: Pci;
+  - Gpio pin configuration in native mode for each assigned pin
+RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
+

[edk2-devel] [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH SMM library class instances.

* SmmSpiFlashCommonLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
 |  51 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
 | 196 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
   |  54 ++
 3 files changed, 301 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
new file mode 100644
index 00..abc919867c
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
@@ -0,0 +1,51 @@
+## @file
+# SMM Library instance of Spi Flash Common Library Class
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010017
+  BASE_NAME  = SmmSpiFlashCommonLib
+  FILE_GUID  = 9632D96E-E849-4217-9217-DC500B8AAE47
+  VERSION_STRING = 1.0
+  MODULE_TYPE= DXE_SMM_DRIVER
+  LIBRARY_CLASS  = SpiFlashCommonLib|DXE_SMM_DRIVER
+  CONSTRUCTOR= SmmSpiFlashCommonLibConstructor
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+  PciLib
+  IoLib
+  MemoryAllocationLib
+  BaseLib
+  UefiLib
+  SmmServicesTableLib
+  BaseMemoryLib
+  DebugLib
+  MmPciLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+  gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress  ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+
+[Sources]
+  SpiFlashCommonSmmLib.c
+  SpiFlashCommon.c
+
+[Protocols]
+  gPchSmmSpiProtocolGuid## CONSUMES
+
+[Depex.X64.DXE_SMM_DRIVER]
+  gPchSmmSpiProtocolGuid
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
new file mode 100644
index 00..53711db632
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
@@ -0,0 +1,196 @@
+/** @file
+  Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
+  for module use.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+PCH_SPI_PROTOCOL   *mSpiProtocol;
+
+//
+// FlashAreaBaseAddress and Size for boottime and runtime usage.
+//
+UINTN mFlashAreaBaseAddress = 0;
+UINTN mFlashAreaSize= 0;
+
+/**
+  Enable block protection on the Serial Flash device.
+
+  @retval EFI_SUCCESS   Opertion is successful.
+  @retval EFI_DEVICE_ERROR  If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Read NumBytes bytes of data from the address specified by
+  PAddress into Buffer.
+
+  @param[in]  Address   The starting physical address of the read.
+  @param[in,out]  NumBytes  On input, the number of bytes to read. On 
output, the number
+of bytes actually read.
+  @param[out] BufferThe destination data buffer for the read.
+
+  @retval EFI_SUCCESS   Opertion is successful.
+  @retval EFI_DEVICE_ERROR  If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+  IN UINTNAddress,
+  IN OUT UINT32   *NumBytes,
+ OUT UINT8*Buffer
+  )
+{
+  ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+  if ((NumBytes == NULL) || (Buffer == NULL)) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // This function is implemented specifically for those platforms
+  // at which the SPI device is memory mapped for read. So this
+  // function just do a memory copy for Spi Flash Read.
+  //
+  CopyMem (Buffer, (VOID *) Address, *NumBytes);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Write NumBytes bytes of data from Buffer to the address specified by
+  PAddresss.
+
+  @param[in]  Address The starting physical address of the write.
+  @param[in,out]  NumBytesOn input, the number of bytes to write. On 
output,
+  the actual number of bytes written.
+  @param[in]  Buffer  The source data buffer for the write.
+
+  @retval EFI_SUCCESS   Op

[edk2-devel] [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds PCH Base library class instances.

* BaseResetSystemLib
* BaseSmbusLib

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
 |  38 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf   
  |  39 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c
   | 153 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.c 
  | 993 
 4 files changed, 1223 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
new file mode 100644
index 00..8d68f2dd83
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Component description file for Intel Ich7 Reset System Library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseResetSystemLib
+FILE_GUID = D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = ResetSystemLib
+CONSTRUCTOR = BaseResetSystemLibConstructor
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+IoLib
+DebugLib
+PmcLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseResetSystemLib.c
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf
new file mode 100644
index 00..f3388a2624
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf
@@ -0,0 +1,39 @@
+## @file
+# Component description file for PCH Smbus Library.
+#
+# SMBUS Library that layers on top of the I/O Library to directly
+# access a standard SMBUS host controller.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseSmbusLib
+FILE_GUID = 5C4D0430-F81B-42D3-BB88-4A6CD2796FF8
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SmbusLib
+CONSTRUCTOR = BaseSmbusLibConstructor
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+BaseLib
+DebugLib
+IoLib
+PciSegmentLib
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseSmbusLib.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c
new file mode 100644
index 00..a603f5e794
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c
@@ -0,0 +1,153 @@
+/** @file
+  System reset library services.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16   mBaseResetSystemABase;
+
+/**
+  Calling this function causes a system-wide reset. This sets
+  all circuitry within the system to its initial state. This type of reset
+  is asynchronous to system operation and operates without regard to
+  cycle boundaries.
+
+  System reset should not return, if it returns, it means the system does
+  not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+  VOID
+  )
+{
+  IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET);
+}
+
+/**
+  Calling this function causes a system-wide initialization. The processors
+  are set to their initial state, and pending cycles are not corrupted.
+
+  System reset should not return, if it returns, it means the system does
+  not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+  VOID
+  )
+{
+  IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET);
+}
+
+/**
+  Calling this function causes the system to enter a power state equivalent
+  to the ACPI G2/S5 or G3 states.
+
+  System shutdown should not return, if it returns, it means the system does
+  not support shut down reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+  VOID
+  )
+{
+  UINT16 ABase;
+  UINT32 Data32;
+
+  ABase = mBaseResetSystemABase;
+  if (ABase == 0) {
+ABase = PmcGetAcpiBase ();
+  }
+  ///
+  /// Firstly, GPE0_EN sho

[edk2-devel] [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/Ppi
 * Pch/Include/Protocol

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h  
  |  42 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h   
  |  27 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h   
  |  28 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h 
  | 186 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h   
  | 136 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h
  |  68 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h   
  | 146 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h   
  | 132 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h
  |  42 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h 
  |  42 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h   
  | 134 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h  
  |  67 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h
 |  67 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h
  | 152 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h 
  |  15 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h  
  | 295 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h  
  | 113 
 17 files changed, 1692 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h
new file mode 100644
index 00..840a2355f1
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h
@@ -0,0 +1,42 @@
+/** @file
+  PCH Reset PPI
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_RESET_PPI_H_
+#define _PCH_RESET_PPI_H_
+
+//
+// Member functions
+//
+/**
+  Execute call back function for Pch Reset.
+
+  @param[in] ResetTypeReset Types which includes GlobalReset.
+  @param[in] ResetTypeGuidPointer to an EFI_GUID, which is the Reset 
Type Guid.
+
+  @retval EFI_SUCCESS The callback function has been done 
successfully
+  @retval EFI_NOT_FOUND   Failed to find Pch Reset Callback ppi. Or, 
none of
+  callback ppi is installed.
+  @retval Others  Do not do any reset from PCH
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_RESET_CALLBACK) (
+  IN  EFI_RESET_TYPEResetType,
+  IN  EFI_GUID  *ResetTypeGuid
+  );
+
+/**
+  This ppi is used to execute PCH Reset from the host controller.
+  If drivers need to run their callback function right before issuing the PCH 
Reset,
+  they can install PCH Reset Callback PPI before PCH Reset PEI driver to 
achieve that.
+**/
+typedef struct {
+  PCH_RESET_CALLBACK  ResetCallback;
+} PCH_RESET_CALLBACK_PPI;
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h
new file mode 100644
index 00..d3ff152742
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h
@@ -0,0 +1,27 @@
+/** @file
+  This file defines the PCH SPI PPI which implements the
+  Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_SPI_PPI_H_
+#define _PCH_SPI_PPI_H_
+
+#include 
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID   gPchSpiPpiGuid;
+
+/**
+  Reuse the PCH_SPI_PROTOCOL definitions
+  This is possible becaues the PPI implementation does not rely on a 
PeiService pointer,
+  as it uses EDKII Glue Lib to do IO accesses
+**/
+typedef PCH_SPI_PROTOCOL PCH_SPI_PPI;
+
+#endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h
new file mode 100644
index 00..59a9f0f251
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h
@@ -0,0 +1,28 @@
+/** @file
+  Watchdog Timer PPI
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_WDT_H_
+#define _PEI_WDT_H_
+
+#include 
+//
+// MRC takes a lot of time to 

[edk2-devel] [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds Pch/Include headers.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h   | 
135 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h   | 
326 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h | 
381 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h| 
340 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h | 
241 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h| 
200 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h|  
54 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h   |  
38 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h   |  
80 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h|  
53 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h  |  
47 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h  |  
47 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h|  
59 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResources.h |  
53 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h |  
23 ++
 15 files changed, 2077 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h
new file mode 100644
index 00..91222fd54d
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h
@@ -0,0 +1,135 @@
+/** @file
+  Header file for DxePchHdaNhltLib - NHLT structure definitions.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_HDA_NHLT_H_
+#define _DXE_HDA_NHLT_H_
+
+#include 
+
+//
+// ACPI support protocol instance signature definition.
+//
+#define NHLT_ACPI_TABLE_SIGNATURE  SIGNATURE_32 ('N', 'H', 'L', 'T')
+
+// MSFT defined structures
+#define SPEAKER_FRONT_LEFT  0x1
+#define SPEAKER_FRONT_RIGHT 0x2
+#define SPEAKER_FRONT_CENTER0x4
+#define SPEAKER_BACK_LEFT   0x10
+#define SPEAKER_BACK_RIGHT  0x20
+
+#define KSAUDIO_SPEAKER_MONO   (SPEAKER_FRONT_CENTER)
+#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT)
+#define KSAUDIO_SPEAKER_QUAD   (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT | 
SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)
+
+#define WAVE_FORMAT_EXTENSIBLE0xFFFE
+#define KSDATAFORMAT_SUBTYPE_PCM \
+{0x0001, 0x, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 
0x9b, 0x71}}
+
+#pragma pack (push, 1)
+
+typedef struct {
+  UINT16  wFormatTag;
+  UINT16  nChannels;
+  UINT32  nSamplesPerSec;
+  UINT32  nAvgBytesPerSec;
+  UINT16  nBlockAlign;
+  UINT16  wBitsPerSample;
+  UINT16  cbSize;
+} WAVEFORMATEX;
+
+typedef struct {
+  WAVEFORMATEX Format;
+  union {
+UINT16 wValidBitsPerSample;
+UINT16 wSamplesPerBlock;
+UINT16 wReserved;
+  } Samples;
+  UINT32   dwChannelMask;
+  GUID SubFormat;
+} WAVEFORMATEXTENSIBLE;
+
+//
+// List of supported link type.
+//
+enum NHLT_LINK_TYPE
+{
+  HdaNhltLinkHd   = 0,
+  HdaNhltLinkDsp  = 1,
+  HdaNhltLinkDmic = 2,
+  HdaNhltLinkSsp  = 3,
+  HdaNhltLinkInvalid
+};
+
+//
+// List of supported device type.
+//
+enum NHLT_DEVICE_TYPE
+{
+  HdaNhltDeviceBt   = 0,
+  HdaNhltDeviceDmic = 1,
+  HdaNhltDeviceI2s  = 4,
+  HdaNhltDeviceInvalid
+};
+
+typedef struct {
+  UINT32CapabilitiesSize;
+  UINT8 Capabilities[1];
+} SPECIFIC_CONFIG;
+
+typedef struct {
+  WAVEFORMATEXTENSIBLE Format;
+  SPECIFIC_CONFIG  FormatConfiguration;
+} FORMAT_CONFIG;
+
+typedef struct {
+  UINT8   FormatsCount;
+  FORMAT_CONFIG   FormatsConfiguration[1];
+} FORMATS_CONFIG;
+
+typedef struct {
+  UINT8   DeviceId[16];
+  UINT8   DeviceInstanceId;
+  UINT8   DevicePortId;
+} DEVICE_INFO;
+
+typedef struct {
+  UINT8   DeviceInfoCount;
+  DEVICE_INFO DeviceInformation[1];
+} DEVICES_INFO;
+
+typedef struct {
+  UINT32  EndpointDescriptorLength;
+  UINT8   LinkType;
+  UINT8   InstanceId;
+  UINT16  HwVendorId;
+  UINT16  HwDeviceId;
+  UINT16  HwRevisionId;
+  UINT32  HwSubsystemId;
+  UINT8   DeviceType;
+  UINT8   Direction;
+  UINT8   VirtualBusId;
+  SPECIFIC_CONFIG EndpointConfig;
+  FORMATS_CONFIG  FormatsConfig;
+  DEVICES_INFODevicesInformation;
+} ENDPOINT_DESCRIPTOR;
+
+//
+// High Level Table structure
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'}
+  UINT8   En

[edk2-devel] [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/library

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h | 
 27 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h | 
 24 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h | 
 58 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h   | 
265 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h | 
788 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h   | 
166 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h| 
 33 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h | 
371 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h  | 
141 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h   | 
 36 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h  | 
109 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h  | 
407 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h| 
105 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h   | 
226 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h   | 
 45 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h| 
114 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h | 
 24 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h | 
116 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h  | 
240 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h  | 
111 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h| 
 23 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h | 
121 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h  | 
207 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h | 
 76 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h   | 
 22 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h   | 
 98 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h  | 
 23 +
 27 files changed, 3976 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
new file mode 100644
index 00..ee77334ecb
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h
@@ -0,0 +1,27 @@
+/** @file
+  Header file for BiosLockLib.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BIOSLOCK_LIB_H_
+#define _BIOSLOCK_LIB_H_
+
+/**
+  Enable BIOS lock. This will set the LE (Lock Enable) and EISS (Enable In 
SMM.STS).
+  When this is set, attempts to write the WPD (Write Protect Disable) bit in 
PCH
+  will cause a SMI which will allow the BIOS to verify that the write is from 
a valid source.
+
+  Bios should always enable LockDownConfig.BiosLock policy to set Bios Lock 
bit in FRC.
+  If capsule udpate is enabled, it's expected to not do BiosLock by setting 
BiosLock policy disable
+  so it can udpate BIOS region.
+  After flash update, it should utilize this lib to do BiosLock for security.
+**/
+VOID
+BiosLockEnable (
+  VOID
+  );
+
+#endif // _BIOSLOCK_LIB_H_
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
new file mode 100644
index 00..f406e0d929
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h
@@ -0,0 +1,24 @@
+/** @file
+  Header file for CnviLib.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CNVI_LIB_H_
+#define _CNVI_LIB_H_
+
+/**
+  Check if CNVi is present.
+
+  @retval TRUECNVi is enabled
+  @retval FALSE   CNVi is disabled
+
+**/
+BOOLEAN
+CnviIsPresent (
+  VOID
+  );
+
+#endif // _CNVI_LIB_H_
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h
new file mode 100644
index 00..4d1ed91f7e
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h
@@ -0,0 +1,58 @@
+/** @file
+  Prototype of the DxePchPolicyLib libra

[edk2-devel] [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Create the CoffeelakeSiliconPkg to provide an initial package for
silicon initialization code for Coffee Lake (CFL) and Whiskey Lake
(WHL) generation products.

* Major areas of functionality are categorized into CPU, Management
  Engine (ME), Platform Controller Hub (PCH), and System Agent
  subdirectories.
* Common libraries and headers are kept at the root of the package.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec  | 
714 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h  |  
53 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h |  
89 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h| 
291 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h | 
157 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h   |  
64 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h |  
28 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h | 
123 
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h |  
58 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h  | 
110 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h  |  
22 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h   |  
34 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h | 
319 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h |  
29 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h  |  
26 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h   |  
71 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h|  
60 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h |  
55 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h  |  
19 +
 Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h   |  
65 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h |  
23 +
 21 files changed, 2410 insertions(+)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec 
b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
new file mode 100644
index 00..fa8c11e93d
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
@@ -0,0 +1,714 @@
+## @file
+# Component description file for the Silicon Reference Code.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME  = SiPkg
+PACKAGE_VERSION   = 0.1
+PACKAGE_GUID  = F245E276-44A0-46b3-AEB5-9898BBCF008D
+
+[Includes]
+  Include
+  SampleCode/Include
+  SampleCode/MdeModulePkg/Include
+  SampleCode/IntelFrameworkPkg/Include
+  #
+  # SystemAgent
+  #
+  SystemAgent/Include
+  SystemAgent/MemoryInit/Include
+  SystemAgent/AcpiTables
+  #
+  # Cpu
+  #
+  Cpu/Include
+  #
+  # Me
+  #
+  Me/Include
+  #
+  # Pch
+  #
+  Pch/Include
+
+[Guids.common.Private]
+  #
+  # PCH
+  #
+  gPchDeviceTableHobGuid   = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66, 
0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}
+  gPchConfigHobGuid= { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd9, 
0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}
+  gGpioLibUnlockHobGuid= { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6, 
0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
+  gSiScheduleResetHobGuid  = { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC1, 
0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }}
+
+[Guids]
+##
+## MdeModulePkg
+##
+gEfiMemoryTypeInformationGuid  =  {0x4c19049f, 0x4137, 0x4dd3, {0x9c, 0x10, 
0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}}
+gEfiCapsuleVendorGuid  =  {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36, 
0xec, 0xbd, 0x3c, 0x8b, 0xe2}}
+gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0x0, 
0x90, 0x27, 0x3f, 0xc1, 0x4d}}
+
+##
+## IntelFrameworkPkg
+##
+gEfiSmmPeiSmramMemoryReserveGuid =  {0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 
0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}}
+
+##
+## Common
+##
+## Include/ConfigBlock/SiConfig.h
+gSiConfigGuid = {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97, 
0x38, 0x59, 0xd8 }}
+gSiPkgTokenSpaceGuid  =  {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43, 0x66, 
0x99, 0xcb, 0xe4, 0x5b}}
+
+## Include/SiConfigHob.h
+gSiConfigHobGuid = {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0x5f, 0x8f, 
0xd7, 0x65, 0x4e}}
+
+##
+## System Agent
+##
+gSaAcpiTableStorageGuid  =  {0x3c0ed5e2, 0x91ea, 0x4b94, { 0x82, 0xd, 0x9d, 
0xaf, 0x9a, 0x3b, 0xb4, 0xa2}}
+gSaDataHobGuid  =  {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2, 0xc4, 
0x4a, 0x0e, 0

[edk2-devel] [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds Pch/Library/Private Base library class instances.

* BaseGpioHelpersLibNull
* BasePchSpiCommonlib
* BaseSiScheduleResetLib
* BaseSiScheduleResetLibFsp

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
 |   26 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
   |   28 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
 |   40 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibFsp.inf
  |   40 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
   |  108 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/SpiCommon.c
   | 1081 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c
   |   70 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibCommon.c
 |  125 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibFsp.c
|   61 ++
 9 files changed, 1579 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
new file mode 100644
index 00..5502af824f
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
@@ -0,0 +1,26 @@
+## @file
+# Component description file for the NULL GpioHelpersLib
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseGpioHelpersLib
+FILE_GUID = AB282608-2A50-4AE3-9242-64064ECF40D4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioHelpersLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseGpioHelpersLibNull.c
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
new file mode 100644
index 00..ea23e628c8
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
@@ -0,0 +1,28 @@
+## @file
+#  Component description file for the PchSpiCommonLib
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = BasePchSpiCommonLib
+  FILE_GUID  = A37CB67E-7D85-45B3-B07E-BF65BDB603E8
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PchSpiCommonLib
+
+[Sources]
+  SpiCommon.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+  IoLib
+  DebugLib
+  PmcLib
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
new file mode 100644
index 00..de7f6eeb73
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf
@@ -0,0 +1,40 @@
+## @file
+# Component description file for Si Reset Schedule Library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseSiScheduleResetLib
+FILE_GUID = E6F3D551-36C0-4737-80C7-47FC57593163
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SiScheduleResetLib
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+HobLib
+ResetSystemLib
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Guids]
+gSiScheduleResetHobGuid
+gPchConfigHobGuid
+
+[Sources]
+BaseSiScheduleResetLibCommon.c
+BaseSiScheduleResetLib.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibFsp.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibFsp.inf
new file mode 100644
index 00..c8fe9e6079
--- /dev/

[edk2-devel] [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds package-level library class instances.

* BaseConfigBlockLib - Library functions for config block management.
* BaseSiConfigBlockLib - Library functions for managing component
  config blocks.
* DxeAslUpdateLib - Services to update ACPI tables.
* PeiDxeSmmMmPciLib - Services to manage PCI Express addresses.
* PeiStallPpiLib - Installs an instance of EFI_PEI_STALL_PPI.
* PeiSiPolicyLib - Installs an instance of the Silicon Policy PPI.
  Prints the Silicon Policy PPI values when DEBUG prints are enabled.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
 |  29 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
 |  33 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf 
  |  40 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.inf
   |  30 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
   |  35 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiStallPpiLib.inf
  |  31 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf   
  |  51 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h 
  |  35 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
   | 146 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.c
   |  87 +
 Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.c   
  | 403 
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.c
 | 126 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c
 |  32 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiStallPpiLib.c
|  78 
 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c 
  | 214 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
 | 122 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/SiPrintPolicy.c  
  |  36 ++
 17 files changed, 1528 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
new file mode 100644
index 00..a7def2481d
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
@@ -0,0 +1,29 @@
+## @file
+# Component INF file for the BaseConfigBlock library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseConfigBlockLib
+FILE_GUID = 1EC07EA8-7808-4e06-9D79-309AE331D2D5
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseConfigBlockLib.c
+
+[LibraryClasses]
+DebugLib
+BaseMemoryLib
+MemoryAllocationLib
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
new file mode 100644
index 00..b04dc3cfa4
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Component description file for the BaseSiConfigBlockLib library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseSiConfigBlockLib
+FILE_GUID = 6C068D0F-F48E-48CB-B369-433E507AF4A2
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SiConfigBlockLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseSiConfigBlockLib.c
+
+
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
new file mode 100644
index 00..658caccb43
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
@@ -0,0 +1,40 @@
+## @file
+# Provides services to update ASL tables.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeAslUpdateLib
+FILE_GUID = 8621697D-4E3A-4bf2-ADB0-3E2FF06559

[edk2-devel] [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds header files to Pch/Include/ConfigBlock.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
|  69 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h 
|  56 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h 
|  43 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h
|  40 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h
 |  54 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevConfig.h 
|  39 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h 
| 178 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
|  57 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h
|  58 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h
|  66 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h   
|  58 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h  
|  68 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h 
|  57 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h 
|  35 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h
|  70 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h 
|  34 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h
|  49 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h  
|  71 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHubConfig.h 
|  36 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h  
| 429 
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h  
| 311 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h
| 230 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h 
|  63 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h
|  96 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h   
|  43 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h   
|  52 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h 
| 139 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h
|  33 ++
 28 files changed, 2534 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
new file mode 100644
index 00..35fa125ba3
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
@@ -0,0 +1,69 @@
+/** @file
+  CNVI policy
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CNVI_CONFIG_H_
+#define _CNVI_CONFIG_H_
+
+#define CNVI_CONFIG_REVISION 2
+extern EFI_GUID gCnviConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  CNVi Mode options
+**/
+typedef enum {
+  CnviModeDisabled = 0,
+  CnviModeAuto
+} CNVI_MODE;
+
+/**
+  CNVi MfUart1 connection options
+**/
+typedef enum {
+  CnviMfUart1Ish = 0,
+  CnviMfUart1SerialIo,
+  CnviBtUart1ExtPads,
+  CnviBtUart1NotConnected
+} CNVI_MFUART1_TYPE;
+
+
+/**
+  Revision 1:
+  - Initial version.
+  Revision 2:
+  - Remove BtInterface and BtUartType.
+
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
+  /**
+This option allows for automatic detection of Connectivity Solution.
+Auto Detection assumes that CNVi will be enabled when available;
+Disable allows for disabling CNVi.
+CnviModeDisabled = Disabled,
+CnviModeAuto = Auto Detection
+  **/
+  UINT32 Mode  :  1;
+  /**
+(Test) This option configures Uart type which connects to MfUart1
+For production configuration ISH is the default, for tests SerialIO Uart0 
or external pads can be used
+Use CNVI_MFUART1_TYPE enum for selection
+CnviMfUart1Ish = MfUart1 over ISH Uart0,
+CnviMfUart1SerialIo = MfUart1 over SerialIO Uart2,
+CnviBtUart1ExtPads = MfUart1 over exteranl pads,
+CnviBtUart1NotConnected = MfUart1 not connected
+  **/
+  UINT32 MfUart1Type   :  2;
+  UINT32 RsvdBits  : 29;
+} PCH_CNVI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CNVI_CONFIG_H_
+
diff --gi

[edk2-devel] [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add library instances

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds CPU library class instances.

* BaseCpuMailboxLibNull - Generic CPU mailbox interaction services.
* PeiCpuPolicyLib - CPU policy configuration services.
* PeiCpuPolicyLibPreMem - CPU policy pre-memory configuration services.
* PeiDxeSmmCpuPlatformLib - CPU platform services.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf
 |  22 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf
 |  65 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibPreMem.inf
   |  43 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
 |  39 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h
   |  30 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h
|  28 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.c
   |  90 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPolicy.c 
   | 293 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPolicyPreMem.c
  | 108 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
   | 434 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibPreMem.c
 | 160 
 
Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
| 415 +++
 12 files changed, 1727 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf
new file mode 100644
index 00..4fcfca4670
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf
@@ -0,0 +1,22 @@
+## @file
+# Component description file for Cpu Mailbox Null Lib
+#
+# Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseCpuMailboxLibNull
+FILE_GUID = 74F470BC-1769-4732-B9C0-EE9AB0B12411
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuMailboxLib
+
+[Packages]
+MdePkg/MdePkg.dec
+
+[Sources]
+BaseCpuMailboxLibNull.c
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf
new file mode 100644
index 00..c986e35360
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf
@@ -0,0 +1,65 @@
+## @file
+# Component description file for the PeiCpuPolicyLib library.
+#
+# Copyright (c) 2019 Intel Corporation. All rights reserved. 
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiCpuPolicyLib
+FILE_GUID = 5baafc8f-25c6-4d19-b141-585757509372
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = CpuPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+CpuPlatformLib
+PciSegmentLib
+SaPlatformLib
+SiConfigBlockLib
+PostCodeLib
+PcdLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiCpuPolicyLib.c
+PeiCpuPolicyLibrary.h
+CpuPrintPolicy.c
+PeiCpuPolicyLibPreMem.c
+CpuPrintPolicyPreMem.c
+
+[Ppis]
+gSiPolicyPpiGuid## CONSUMES
+gSiPreMemPolicyPpiGuid  ## CONSUMES
+
+[FixedPcd]
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+
+[Pcd]
+gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode  ## Produces
+
+[Guids]
+gCpuConfigGuid  ## PRODUCES
+gCpuSgxConfigGuid   ## PRODUCES
+gCpuPowerMgmtBasicConfigGuid## PRODUCES
+gCpuPowerMgmtCustomConfigGuid   ## PRODUCES
+gCpuTestConfigGuid  ## PRODUCES
+gCpuPidTestConfigGuid   ## PRODUCES
+gCpuPowerMgmtTestConfigGuid ## PRODUCES
+gCpuConfigLibPreMemConfigGuid   ## PRODUCES
+gCpuSecurityPreMemConfigGuid## PRODUCES
+gCpuOverclockingPreMemConfigGuid## CONSUMES
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibPreMem.inf
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibPreMem.inf
new file mode 100644
index 00..52dc989f74
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCp

[edk2-devel] [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library include headers

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082

Adds the following header files:
 * Pch/Include/Private/Library

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ankit Sinha 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNhlt.h 
  |  134 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHelpersLib.h 
 |   97 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioNameBufferLib.h
   |   25 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPrivateLib.h 
 | 1061 
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMasterCommonLib.h
  |  288 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmiLib.h 
  |  344 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHdaLib.h 
  |   56 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchInitCommonLib.h
|  100 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPciExpressHelpersLib.h
 |  371 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsfPrivateLib.h
|  578 +++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmbusCommonLib.h
   |   98 ++
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiCommonLib.h
 |  366 +++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPchDmiLib.h  
  |   25 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPrivateLib.h 
  |  706 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiScheduleResetLib.h
  |   48 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPchPrivateLib.h
|   28 +
 16 files changed, 4325 insertions(+)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNhlt.h
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNhlt.h
new file mode 100644
index 00..9d8e34eb0d
--- /dev/null
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNhlt.h
@@ -0,0 +1,134 @@
+/** @file
+  Header file for DxePchHdaLib - NHLT structure definitions.
+
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_PCH_HDA_NHLT_H_
+#define _DXE_PCH_HDA_NHLT_H_
+
+#include 
+
+//
+// ACPI support protocol instance signature definition.
+//
+#define NHLT_ACPI_TABLE_SIGNATURE  SIGNATURE_32 ('N', 'H', 'L', 'T')
+
+// MSFT defined structures
+#define SPEAKER_FRONT_LEFT  0x1
+#define SPEAKER_FRONT_RIGHT 0x2
+#define SPEAKER_FRONT_CENTER0x4
+#define SPEAKER_BACK_LEFT   0x10
+#define SPEAKER_BACK_RIGHT  0x20
+
+#define KSAUDIO_SPEAKER_MONO   (SPEAKER_FRONT_CENTER)
+#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT)
+#define KSAUDIO_SPEAKER_QUAD   (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT | 
SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)
+
+#define WAVE_FORMAT_EXTENSIBLE0xFFFE /* Microsoft */
+#define KSDATAFORMAT_SUBTYPE_PCM \
+{0x0001, 0x, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 
0x9b, 0x71}}
+
+#pragma pack (push, 1)
+
+typedef struct {
+  UINT16  wFormatTag;
+  UINT16  nChannels;
+  UINT32  nSamplesPerSec;
+  UINT32  nAvgBytesPerSec;
+  UINT16  nBlockAlign;
+  UINT16  wBitsPerSample;
+  UINT16  cbSize;
+} WAVEFORMATEX;
+
+typedef struct {
+  WAVEFORMATEX Format;
+  union {
+UINT16 wValidBitsPerSample;
+UINT16 wSamplesPerBlock;
+UINT16 wReserved;
+  } Samples;
+  UINT32   dwChannelMask;
+  GUID SubFormat;
+} WAVEFORMATEXTENSIBLE;
+
+//
+// List of supported link type.
+//
+enum NHLT_LINK_TYPE
+{
+  HdaNhltLinkHd   = 0,
+  HdaNhltLinkDsp  = 1,
+  HdaNhltLinkDmic = 2,
+  HdaNhltLinkSsp  = 3,
+  HdaNhltLinkInvalid
+};
+
+//
+// List of supported device type.
+//
+enum NHLT_DEVICE_TYPE
+{
+  HdaNhltDeviceBt   = 0,
+  HdaNhltDeviceDmic = 1,
+  HdaNhltDeviceI2s  = 4,
+  HdaNhltDeviceInvalid
+};
+
+typedef struct {
+  UINT32CapabilitiesSize;
+  UINT8 Capabilities[1];
+} SPECIFIC_CONFIG;
+
+typedef struct {
+  WAVEFORMATEXTENSIBLE Format;
+  SPECIFIC_CONFIG  FormatConfiguration;
+} FORMAT_CONFIG;
+
+typedef struct {
+  UINT8   FormatsCount;
+  FORMAT_CONFIG   FormatsConfiguration[1];
+} FORMATS_CONFIG;
+
+typedef struct {
+  UINT8   DeviceId[16];
+  UINT8   DeviceInstanceId;
+  UINT8   DevicePortId;
+} DEVICE_INFO;
+
+typedef struct {
+  UINT8   DeviceInfoCount;
+  DEVICE_INFO DeviceInformation[1];
+} DEVICES_INFO;
+
+typedef struct {
+  UINT32  EndpointDescriptorLength;
+  UINT8   LinkType;
+  UINT8   InstanceId;
+  UINT16  HwVendorId;
+  UINT16  HwDeviceId;
+  

Re: [edk2-devel] [PATCH v2 1/1] MdePkg: Add STATIC_ASSERT macro

[rebecca]

On 2019-08-16 18:03, Andrew Fish wrote:
> It is also interesting in the context of our CI as we could pick oldest and 
> newest version from every compiler family for the CI build test. 


Yes, that's going to be important. Given
https://docs.microsoft.com/en-us/cpp/porting/visual-cpp-change-history-2003-2015?view=vs-2019,
I suspect support for VS2008 might already have been broken, since it
reports that "static_assert" was introduced in Visual Studio 2010 - and
we use it in BaseTools/Source/C/Common/PcdValueCommon.h (the
_STATIC_ASSERT was added in September 2018):


#if defined(_MSC_EXTENSIONS)
#define __STATIC_ASSERT static_assert
#else
#define __STATIC_ASSERT _Static_assert
#endif


-- 
Rebecca Cran


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Re: [edk2-devel] [PATCH v2 1/1] MdePkg: Add STATIC_ASSERT macro

[Andrew Fish via Groups.Io]

> On Aug 16, 2019, at 5:01 PM, Rebecca Cran  wrote:
> 
> On 2019-08-16 16:58, Andrew Fish via Groups.Io wrote:
>> 
>> I'm all for modernization of the C code as long we are thoughtful
>> about compatibility. For example I still see that VS2008 is a
>> supported BaseTools/Conf/tools_def.template.
> 
> 
> It would be interesting to see who's using the older toolchains against
> current/newer revisions of the edk2.
> 
> For example at work we build a UEFI driver using VS2012, but it's
> against the UDK2014.SP1 branch, and being for a legacy product we'll
> never migrate to a newer UDK release or master tag.
> 

Rebecca,

It is also interesting in the context of our CI as we could pick oldest and 
newest version from every compiler family for the CI build test. 

Thanks,

Andrew Fish


> 
> -- 
> Rebecca Cran
> 


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Re: [edk2-devel] [PATCH v2 1/1] MdePkg: Add STATIC_ASSERT macro

[rebecca]

On 2019-08-16 16:58, Andrew Fish via Groups.Io wrote:
>
> I'm all for modernization of the C code as long we are thoughtful
> about compatibility. For example I still see that VS2008 is a
> supported BaseTools/Conf/tools_def.template.


It would be interesting to see who's using the older toolchains against
current/newer revisions of the edk2.

For example at work we build a UEFI driver using VS2012, but it's
against the UDK2014.SP1 branch, and being for a legacy product we'll
never migrate to a newer UDK release or master tag.


-- 
Rebecca Cran


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[edk2-devel] [PATCH v1 3/3] MdePkg: Drop VERIFY_SIZE_OF in favour of STATIC_ASSERT

[Vitaly Cheptsov via Groups.Io]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2048

New STATIC_ASSERT macro supersedes VERIFY_SIZE_OF as being more functional.

Signed-off-by: Vitaly Cheptsov 
---
 MdePkg/Include/Base.h | 13 -
 1 file changed, 13 deletions(-)

diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h
index d871422cd6..ed85b98318 100644
--- a/MdePkg/Include/Base.h
+++ b/MdePkg/Include/Base.h
@@ -28,19 +28,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #pragma warning ( disable : 4200 )
 #endif
 
-/**
-  Verifies the storage size of a given data type.
-
-  This macro generates a divide by zero error or a zero size array declaration 
in
-  the preprocessor if the size is incorrect.  These are declared as "extern" so
-  the space for these arrays will not be in the modules.
-
-  @param  TYPE  The date type to determine the size of.
-  @param  Size  The expected size for the TYPE.
-
-**/
-#define VERIFY_SIZE_OF(TYPE, Size) extern UINT8 
_VerifySizeof##TYPE[(sizeof(TYPE) == (Size)) / (sizeof(TYPE) == (Size))]
-
 //
 // The Microsoft* C compiler can removed references to unreferenced data items
 //  if the /OPT:REF linker option is used. We defined a macro as this is a
-- 
2.20.1 (Apple Git-117)


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[edk2-devel] [PATCH v1 0/3] Replace VERIFY_SIZE_OF with STATIC_ASSERT

[Vitaly Cheptsov via Groups.Io]

Things to note:

- This patchset should go after STATIC_ASSERT implementation:
  https://edk2.groups.io/g/devel/topic/32917749
- It is suggested that unlike the previous patch, which in my
  opinion should appear in edk2-stable201908, this patchset should
  land in edk2-stable2019011. This will let more people to comment
  whether they are ready to use it as is.

Vitaly Cheptsov (3):
  MdeModulePkg/ResetUtilityLib: Use STATIC_ASSERT macro
  MdePkg: Use STATIC_ASSERT macro
  MdePkg: Drop VERIFY_SIZE_OF in favour of STATIC_ASSERT

 MdePkg/Include/Base.h   | 92 +---
 MdeModulePkg/Library/ResetUtilityLib/ResetUtility.c |  5 +-
 2 files changed, 44 insertions(+), 53 deletions(-)

-- 
2.20.1 (Apple Git-117)


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[edk2-devel] [PATCH v1 1/3] MdeModulePkg/ResetUtilityLib: Use STATIC_ASSERT macro

[Vitaly Cheptsov via Groups.Io]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2048

Use new STATIC_ASSERT macro instead of VERIFY_SIZE_OF.

Signed-off-by: Vitaly Cheptsov 
---
 MdeModulePkg/Library/ResetUtilityLib/ResetUtility.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Library/ResetUtilityLib/ResetUtility.c 
b/MdeModulePkg/Library/ResetUtilityLib/ResetUtility.c
index 2b5af4b95a..bb151d0331 100644
--- a/MdeModulePkg/Library/ResetUtilityLib/ResetUtility.c
+++ b/MdeModulePkg/Library/ResetUtilityLib/ResetUtility.c
@@ -20,7 +20,10 @@ typedef struct {
 } RESET_UTILITY_GUID_SPECIFIC_RESET_DATA;
 #pragma pack()
 
-VERIFY_SIZE_OF (RESET_UTILITY_GUID_SPECIFIC_RESET_DATA, 18);
+STATIC_ASSERT (
+  sizeof (RESET_UTILITY_GUID_SPECIFIC_RESET_DATA) == 18,
+  "sizeof (RESET_UTILITY_GUID_SPECIFIC_RESET_DATA) is expected to be 18 bytes"
+  );
 
 /**
   This is a shorthand helper function to reset with reset type and a subtype
-- 
2.20.1 (Apple Git-117)


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[edk2-devel] [PATCH v1 2/3] MdePkg: Use STATIC_ASSERT macro

[Vitaly Cheptsov via Groups.Io]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2048

Use new STATIC_ASSERT macro instead of VERIFY_SIZE_OF.

Signed-off-by: Vitaly Cheptsov 
---
 MdePkg/Include/Base.h | 79 ++--
 1 file changed, 40 insertions(+), 39 deletions(-)

diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h
index ec096133ba..d871422cd6 100644
--- a/MdePkg/Include/Base.h
+++ b/MdePkg/Include/Base.h
@@ -41,45 +41,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 #define VERIFY_SIZE_OF(TYPE, Size) extern UINT8 
_VerifySizeof##TYPE[(sizeof(TYPE) == (Size)) / (sizeof(TYPE) == (Size))]
 
-//
-// Verify that ProcessorBind.h produced UEFI Data Types that are compliant with
-// Section 2.3.1 of the UEFI 2.3 Specification.
-//
-VERIFY_SIZE_OF (BOOLEAN, 1);
-VERIFY_SIZE_OF (INT8, 1);
-VERIFY_SIZE_OF (UINT8, 1);
-VERIFY_SIZE_OF (INT16, 2);
-VERIFY_SIZE_OF (UINT16, 2);
-VERIFY_SIZE_OF (INT32, 4);
-VERIFY_SIZE_OF (UINT32, 4);
-VERIFY_SIZE_OF (INT64, 8);
-VERIFY_SIZE_OF (UINT64, 8);
-VERIFY_SIZE_OF (CHAR8, 1);
-VERIFY_SIZE_OF (CHAR16, 2);
-
-//
-// The following three enum types are used to verify that the compiler
-// configuration for enum types is compliant with Section 2.3.1 of the
-// UEFI 2.3 Specification. These enum types and enum values are not
-// intended to be used. A prefix of '__' is used avoid conflicts with
-// other types.
-//
-typedef enum {
-  __VerifyUint8EnumValue = 0xff
-} __VERIFY_UINT8_ENUM_SIZE;
-
-typedef enum {
-  __VerifyUint16EnumValue = 0x
-} __VERIFY_UINT16_ENUM_SIZE;
-
-typedef enum {
-  __VerifyUint32EnumValue = 0x
-} __VERIFY_UINT32_ENUM_SIZE;
-
-VERIFY_SIZE_OF (__VERIFY_UINT8_ENUM_SIZE, 4);
-VERIFY_SIZE_OF (__VERIFY_UINT16_ENUM_SIZE, 4);
-VERIFY_SIZE_OF (__VERIFY_UINT32_ENUM_SIZE, 4);
-
 //
 // The Microsoft* C compiler can removed references to unreferenced data items
 //  if the /OPT:REF linker option is used. We defined a macro as this is a
@@ -857,6 +818,46 @@ typedef UINTN  *BASE_LIST;
   #define STATIC_ASSERT _Static_assert
 #endif
 
+//
+// Verify that ProcessorBind.h produced UEFI Data Types that are compliant with
+// Section 2.3.1 of the UEFI 2.3 Specification.
+//
+
+STATIC_ASSERT (sizeof (BOOLEAN) == 1, "sizeof (BOOLEAN) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT8)== 1, "sizeof (INT8) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT8)   == 1, "sizeof (UINT8) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT16)   == 2, "sizeof (INT16) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT16)  == 2, "sizeof (UINT16) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT32)   == 4, "sizeof (INT32) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT32)  == 4, "sizeof (UINT32) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT64)   == 8, "sizeof (INT64) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT64)  == 8, "sizeof (UINT64) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (CHAR8)   == 1, "sizeof (CHAR8) does not meet UEFI 
Specification Data Type requirements");
+STATIC_ASSERT (sizeof (CHAR16)  == 2, "sizeof (CHAR16) does not meet UEFI 
Specification Data Type requirements");
+
+//
+// The following three enum types are used to verify that the compiler
+// configuration for enum types is compliant with Section 2.3.1 of the
+// UEFI 2.3 Specification. These enum types and enum values are not
+// intended to be used. A prefix of '__' is used avoid conflicts with
+// other types.
+//
+typedef enum {
+  __VerifyUint8EnumValue = 0xff
+} __VERIFY_UINT8_ENUM_SIZE;
+
+typedef enum {
+  __VerifyUint16EnumValue = 0x
+} __VERIFY_UINT16_ENUM_SIZE;
+
+typedef enum {
+  __VerifyUint32EnumValue = 0x
+} __VERIFY_UINT32_ENUM_SIZE;
+
+STATIC_ASSERT (sizeof (__VERIFY_UINT8_ENUM_SIZE) == 4, "Size of enum does not 
meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (__VERIFY_UINT16_ENUM_SIZE) == 4, "Size of enum does not 
meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not 
meet UEFI Specification Data Type requirements");
+
 /**
   Macro that returns a pointer to the data structure that contains a specified 
field of
   that data structure.  This is a lightweight method to hide information by 
placing a
-- 
2.20.1 (Apple Git-117)


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Re: [edk2-devel] [PATCH v2 1/1] MdePkg: Add STATIC_ASSERT macro

[Vitaly Cheptsov via Groups.Io]

Andrew, Mike,

Actually thanks for making me recheck it. I have just installed doxygen, and 
can confirm that it can generate parameters for non-functional macros. This was 
my main reason for going with /// comment style, which is used for all other 
plain macros. I have just submitted V3 version with this fixed.

With C language modernisation I fully agree that it needs to be done 
reasonably, and that is why I also try to be very realistic on what people 
actually use. For instance, one of the issues that caused several problems is 
the use of 1-sized arrays instead of flexible array members. A couple years ago 
that was still there just because there still existed some compilers that did 
not support [] syntax.

Best wishes,
Vitaly

> 17 авг. 2019 г., в 1:58, Andrew Fish  написал(а):
> 
> 
> 
>> On Aug 16, 2019, at 2:40 PM, Vitaly Cheptsov via Groups.Io 
>> mailto:vit9696=protonmail@groups.io>> 
>> wrote:
>> 
>> Mike,
>> 
>> I missed your message while writing mine, but I am afraid I disagree with 
>> the functional macro usage for this feature.
>> 
>> I explicitly quoted C standard static_assert definition in one of my 
>> previous messages, and I want EDK II to be as close to standard C as 
>> possible.
>> 
>> This will avoid a lot of confusion for newcomers and will let us later adopt 
>> a more flexible single and double argument interface when it gets 
>> standardised.
>> 
>> For these reasons altogether, I am not positive the macro could get a 
>> doxygen documentation as it is not designed to have any arguments in the 
>> first place.
>> 
> 
> Vitaly,
> 
> I don't understand your logic? It is always possible to write a comment in C 
> code?
> 
> In terms of the C standard and the EFI type system we kind of have a long 
> history of how the code ended up like it is. The (U)EFI spec defined its own 
> type system (and ABI) as a way of specifying interoperability so the code got 
> built on top of that. 20 years ago we shied away from having and EFI code 
> base produce definitions of standard C things as we wanted to make it easier 
> to import chunks of code in OS loaders that needed to get ported to EFI from 
> lots of different vendors. Also one of the early compilers that we 
> standardized on was VC2003 and that does not even fully support C99. For some 
> reason it seems VC2008 was also a popular target for some time. I don't think 
> VC++ got around to C99 until 2013/2015. So that is kind how the edk2 ended up 
> with its own type system. 
> 
> I'm all for modernization of the C code as long we are thoughtful about 
> compatibility. For example I still see that VS2008 is a supported 
> BaseTools/Conf/tools_def.template.
> 
> Thanks,
> 
> Andrew Fish
> 
> 
>> Best wishes,
>> Vitaly
>> 
>> On сб, авг. 17, 2019 at 00:04, Kinney, Michael D > > wrote:
>>> 
>>> Laszlo,
>>> 
>>> I agree that better comments/documentation of STATIC_ASSERT()
>>> for EDK II usages is required. For example, EDK II defines
>>> the ASSERT() macro which is based on the standard C function
>>> assert(), but we still document it fully for EDK II usage.
>>> 
>>> /**
>>> Macro that calls DebugAssert() if an expression evaluates to FALSE.
>>> 
>>> If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED
>>> bit of PcdDebugProperyMask is set, then this macro evaluates the Boolean
>>> expression specified by Expression. If Expression evaluates to FALSE, then
>>> DebugAssert() is called passing in the source filename, source line number,
>>> and Expression.
>>> 
>>> @param Expression Boolean expression.
>>> 
>>> **/
>>> #if !defined(MDEPKG_NDEBUG)
>>> #define ASSERT(Expression) \
>>> do { \
>>> if (DebugAssertEnabled ()) { \
>>> if (!(Expression)) { \
>>> _ASSERT (Expression); \
>>> ANALYZER_UNREACHABLE (); \
>>> } \
>>> } \
>>> } while (FALSE)
>>> #else
>>> #define ASSERT(Expression)
>>> #endif
>>> 
>>> I would like to see the macro documentation for
>>> STATIC_ASSERT() with the Doxygen style description of the
>>> parameters. The fact I asked if STATIC_ASSERT() supported
>>> the 2nd message parameter should have been a trigger
>>> for me to ask for the more complete macro comment block.
>>> The fact that this macro can be directly mapped to
>>> built in compiler name makes the implementation simple,
>>> but other implementations are possible for compilers
>>> that do not support this feature directly. This is why
>>> the complete description of the EDK II version is required.
>>> 
>>> I would like to see a V3 with the complete description.
>>> 
>>> In general, I agree it is better if there is code that
>>> uses a new feature in the code base, so the feature can
>>> be tested. A second option we can consider going forward
>>> is for unit test code to be submitted with a new feature,
>>> so even if there are no consumers from the EDK II repos,
>>> the feature can still be tested as the EDK II repos are
>>> maintained. A third option is for community members to
>>> provide